CN1147789C

CN1147789C - Method for detecting clock loss and burr in embedded microprocessor application system

Info

Publication number: CN1147789C
Application number: CNB001168622A
Authority: CN
Inventors: 谢建良; 许俊文; 文峰
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2000-06-29
Filing date: 2000-06-29
Publication date: 2004-04-28
Anticipated expiration: 2020-06-29
Also published as: CN1317741A

Abstract

The present invention provides a method for detecting lock losses and burs in an embedded microprocessor application system. The present invention detects and compares the frequency ratio of a clock to be detected to a system clock so as to detect the loss of the clock to be detected or the burs; the entire process can be achieved inside a programmable logic device. The method is used a multi-channel communication controller (QMC) inside a currently widely used MPC860CPU produced by Motorola and has favorable effect. The method not only omits a chip but also achieves functions and performance that the chip can not achieve.

Description

Loss of clock and burr detection method in the embedded microprocessor application system

The invention belongs to the computer clock detection range, specifically, relate to the detection method of clock quality general in a kind of embedded microprocessor application system.

At present, in embedded microprocessor application system, except that the needs system clock, also has the clock (as distant serial synchronous telecommunications clock, switched circuit clock or the like) of other kind.These clocks will produce burr or temporary transient losing sometimes, and (burr refers to the high frequency clutter that superposes on the clock waveform of standard, temporarily the losing of clock shows as clock signal and presents single high level or low level), these burrs or lose not quite to the influence of total system sometimes therefore often adopt monostable circuit (as 74HC123 etc.) to detect losing of clock and inform microprocessor.But also have in the suitable application, in a single day burr occurs with the situation of losing, will produce serious influence, as in the use of the multichannel communication controller (QMC) of the MPC860 of present widely used Motorola CPU inside, if supply with its clock generating burr or temporarily lose, even the very fast recovery of clock, the multichannel communication controller also can't recover, can carry out the transmitting-receiving of erroneous packets always, cause the forfeiture of multichannel communication controller function.The appearance of this situation is a very serious problem for total system.At this moment can not reach requirement with above-mentioned prior art circuits.

In some patents (is JP02226432A and EP00676695B1 etc. as the patent No.), physical circuit at the clock failure proposition, use in the embedded microprocessor application system, do not exist the controllability of versatility and precision high and be not easy to problems such as enforcement, and still do not have the report of pertinent literature for the burr fault detection method of clock upper frequency.

Therefore, provide the clock detection method of the controllability that a kind of embedded microprocessor application system possesses versatility and precision to be of great practical significance.

The objective of the invention is to the characteristics at present embedded microprocessor application system, proposing a kind of is benchmark with the system clock, and in conjunction with programmable logic device (PLD) losing or method that the burr of clock detects clock.

Design of the present invention is such:

In the embedded microprocessor application system, with system clock as benchmark, when clock to be checked (as the serial type communication clock, synchronous and the bit clock of exchange network) just often, the frequency ratio of system clock and clock to be checked should be certain value n, if allow both error to be arranged frequency ratio, then frequency ratio should be at n ₁～n ₂Between (n ₁＜n＜n ₂), when clock loss of clock to be checked, this moment, clock to be checked presented always for high or be low state, was equivalent to frequency and is zero clock, and both frequency ratios are greater than error upper limit n ₂When burr appearred in clock to be checked, this moment, clock to be checked was equivalent to become a high frequency clock, and then both frequency ratios are less than error lower limit n ₁

Thus, as long as the frequency ratio of clock to be checked and system clock is detected and compares, can realize to clock to be checked lose or burr detects.

The technical scheme that realizes the object of the invention in turn includes the following steps:

1. preestablish the frequency ratio (n=system clock frequency/clock frequency to be checked) of system clock and clock to be checked, n ₁And n ₂(n ₁＜n＜n ₂), n ₁=n-i, n ₂=n+j can establish i=1,2 or 3 according to accuracy requirement, j=1,2 or 3.n ₁And n ₂Value set respectively in clock bur comparer and the loss of clock comparer;

2. by the zero clearing of a system clock counter of pulse signal control, after the zero clearing, counter starts anew system clock is counted;

3. catch the rising edge (being signal is transferred to high level by low level the moment) of clock to be checked by a trigger;

4. the state of trigger being caught by a pulse producer sends corresponding pulse signal;

5. by two comparers, loss of clock comparer and clock bur comparer, with the count value of counter respectively with the n that sets ₁, n ₂Compare;

6. comparative result is informed CPU.

Whole process can be in the inner realization of programmable logic device (PLD).Said programmable logic device (PLD) can adopt the commercially available prod, as the programmable logic device (PLD) of altera corp.Below in conjunction with accompanying drawing detailed content of the present invention is set forth.

Fig. 1 is clock to be checked wave simulation result just often.

Wave simulation result when Fig. 2 is a loss of clock to be checked.

Wave simulation result when Fig. 3 burr occurs for clock to be checked.

Fig. 4 is a logical flow chart.

Fig. 5 realizes circuit diagram for FPGA (Field Programmable Gate Array).

The meaning of each waveform is in Fig. 1～3: waveform 1 is system clock, is the system works clock in the embedded microprocessor application system; Waveform 2 is a clock to be checked, is the clock that will detect, (as serial type communication synchronization clock, the synchronous and bit clock of exchange network), and waveform 3 is a pulse signal, is by the pulse of pulse producer according to clock generating to be checked, is used for control counter zero clearing etc.; Waveform 4 produces high level when expressing current clock and lose for loss of clock; Signal became high level by low level when waveform 5 was represented burr to occur for clock bur; Waveform 6 is zero clearing control, refers to CPU this clock detection circuit that is used for resetting; Waveform 7 is lost or during the burr generation for being meant to CPU when clock, this testing circuit will produce middle fracture or the I/O mouth of a high level to CPU, after CPU detects this signal, and should be with the zero setting of zero clearing control end to remove this signal, then the zero clearing control end is put height, make that testing circuit continues to detect.

As seen from Figure 1, when clock to be checked just often, pulse signal produces two pulses in the cycle of a clock to be checked;

As seen from Figure 2, when clock transient loss to be checked, clock to be checked shows as high level, and the interval of pulse signal surpasses a normal clock period to be checked;

As seen from Figure 3, when burr appearred in clock to be checked, clock to be checked showed as the high frequency waveforms of a narrower width, and this moment, the interval of pulse signal was lower than a normal clock period to be checked.

As seen from Figure 4, this method may further comprise the steps:

1. start detection circuit;

2. begin system clock is counted by counter 8;

3. catch the rising edge of clock to be checked by trigger 9.Arrive trigger upset, its state input pulse generator 10 as rising edge;

4. pulse producer sends corresponding pulse signal, and order set clock counter 8 zero clearings on the one hand of this pulse signal restart counting; On the other hand with the count value of counter before the zero clearing 8 and the setting value error lower limit n in the clock bur comparer 11 ₁Compare, the principle of work of clock bur comparer 11 is that the pulse signal of pulse producer is as its enable signal, when having pulse signal, if count value is less than n ₁, the output high level, on the contrary be low level.

If loss of clock 5. to be checked, then rising edge can not arrive, this moment by loss of clock comparer 12 at any time with count value and setting value error upper limit n ₂Compare.The principle of work of loss of clock comparer 12 is, when count value greater than n ₂The time, be output as high level, otherwise be low level;

If 6. the comparative result of loss of clock comparer 12 and clock bur comparer 11 is true, promptly signal becomes high level by low level, then reports and submits the CPU13 explanation to produce loss of clock or clock bur phenomenon;

6. counter 8 constantly carries out under pulse signal control, and therefore whole clock detection is constantly carried out.

This scheme there are 3 explanations:

(1) adopt rising edge as the counting benchmark, be the characteristics of considering burr itself, general burr is narrower, even negative edge occurs earlier, just rising edge can appear subsequently, and be feasible as the counting benchmark therefore with rising edge, as require with the negative edge be the counting benchmark, only need add a phase inverter and get final product, also two kinds of circuit can be joined together, the rising and falling edges with burr during department is the counting benchmark;

(2) for the burr of width less than system clock, still can capture, this is described in the following detailed description;

When (3) reality was used this method, judgement was lost the count value of clock and burr appearance and can be set promptly reasonable specification error lower limit n according to the precision that will control flexibly ₁With error upper limit n ₂Size, be similar to a bandpass filter, at n ₁＜count value＜n ₂The time be normal, n ₁And n ₂Scope big more, the precision of detection is low more, otherwise then high more.Generally, n can recently determine according to the frequency of system clock and clock to be detected, and n=system clock frequency/clock frequency to be checked detects the clock of 4M as the system clock with 64M, and then n=64/4=16 can select n ₁=15, n ₂=17, if phase place of allowing the 4MHz clock etc. has than mistake, can suitably relax span, as n ₁=14, n ₂=18.

Fig. 5 realizes circuit diagram for FPGA (Field Programmable Gate Array).

According to the realization circuit diagram of the concrete FPGA (Field Programmable Gate Array) of scheme block diagram shown in Figure 4 as shown in Figure 5, the MaxPlus II software of this available altera corp of figure is realized.FPGA (Field Programmable Gate Array) realized that circuit finishes in FPGA (Field Programmable Gate Array) design software environment, compiling and burned programmable logic device (PLD) with system clock and clock entering apparatus pin to be checked, can realize this method and output pin linked to each other with CPU.With system clock 64M, clock 4M to be detected is an example among the figure, and then both sides relation is 16 times, and circuit is with greater than 18 with less than 14 as judgment condition in the drawings, judges whether clock is lost or burr occurred.

As seen from Figure 5, this realization circuit comprises:

Pulse producer 22, three inputs or door 23 that the trigger 19 that the clock bur comparer 16 that the d type flip flop 15 of the counter 25 with synchronous clear terminal, loss of clock comparer 14, comparer 26 and a band Enable Pin constitutes, T trigger 17 and d type flip flop 18 constitute, d type flip flop 20 and XOR gate 21 constitute and the state retaining circuit that constitutes with door 24.

The synchronous zero clearing control signal of counter 25 is from pulse producer 22; The signal of loss of clock comparer 14 is from counter 25, and its judgement is worked as count value greater than n ₂Greater than 18 o'clock, be output as high level, otherwise be low level; The Enable Pin signal of clock bur comparer 16 is from pulse producer～22;

The T termination VCC that forms the T trigger 17 of trigger 19, therefore as long as the pulse width of coming greater than the trigger Time Created (generally less, as 8ns) of programmable logic device (PLD), just can make 5 upsets of T trigger, thereby detect, this method can reach higher precision and just be this.The effect of d type flip flop 18 is with system clock synchronously once, so that the pulse width that the pulse producer 22 of back produces keeps constant;

Three inputs or door 23 and the high level signal that is used to keep loss of clock or clock bur to produce with door 24 are the interface sections of entire circuit and CPU.The effect of circuit generation herein is among Fig. 5, in case loss of clock or burr occur, just the high level that produces is maintained and be passed to CPU, till the CPU response concurrent goes out reset signal.This part can be made amendment as required to meet the needs of various CPU.

Output signal in the FPGA (Field Programmable Gate Array) realization circuit can directly be linked the interruption pin of CPU, also this output signal can be connected to the general I/O pin of CPU, as shown in Figure 6.Also have an other I/O pin to connect the zero clearing control pin of clock detection circuit among Fig. 6, be used for the zero clearing and the startup of CPU control clock detection circuit.

Foregoing circuit is in when work, and pulse signal produces two pulses in the cycle of a clock to be checked, and the count value of counter is 14 between 18 the time, and clock to be checked is normal; Be greater than or less than 14 or at 18 o'clock, be loss of clock or produce burr.In actual applications, precision is adjusted this two values as requested, thereby can use this method very neatly.

Said method and realization circuit use in several designing boards, as the use in the multichannel communication controller (QMC) of the MPC860 of present widely used Motorola CPU inside, after using this method, in case clock burr occurs or loses, this circuit can notify CPU to handle, be unlikely to the ceaselessly operation under error condition of multichannel communication controller, respond well.Detect clock with the special chip of the use of routine (as monostable circuit) and compare, this Method and circuits has not only omitted chip, and has realized chip irrealizable function of institute and performance.So, in the application of embedded microprocessor system widely, if there is the clock detection problem, as long as use this highly versatile, high-precision Method and circuits, can be very simple and direct, effectively deal with problems.

Claims

1. loss of clock and burr detection method in the embedded microprocessor application system is characterized in that this method in turn includes the following steps:

1. start detection circuit;

2. begin system clock is counted by counter (8);

3. catch the rising edge of clock to be checked by trigger (9); Arrive trigger (9) upset, its state input pulse generator (10) as rising edge;

4. pulse producer (10) sends corresponding pulse signal, and this pulse signal is order set clock counter (8) zero clearing on the one hand, restarts counting; On the other hand with the count value of counter before the zero clearing and the setting value error lower limit n of clock bur comparer ₁Compare;

If loss of clock 5. to be checked, then rising edge can not arrive, and loss of clock comparer (12) is at any time with count value and setting value error upper limit n ₂Compare;

If 6. the comparative result of loss of clock comparer (12) and clock bur comparer (11) is true, promptly report and submit CPU (13);

7. counter (8) is counted under pulse signal control continuously, and whole clock detection is carried out continuously.

2. the method for claim 1 is characterized in that, n ₁=n-i, n ₂=n+j, i are 1,2 or 3, and j is 1,2 or 3, and n is a system clock frequency and the ratio of clock frequency to be checked.

3. the method for claim 1 is characterized in that, clock to be checked is the counting benchmark with the negative edge after by a phase inverter.

4. the method for claim 1 is characterized in that, the rising and falling edges with clock to be checked serves as that the counting benchmark is caught rising edge and negative edge burr simultaneously simultaneously.