CN2725904Y

CN2725904Y - Clock detector

Info

Publication number: CN2725904Y
Application number: CN 200420009097
Authority: CN
Inventors: 周恩松
Original assignee: Harbour Networks Holdings Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2004-06-09
Filing date: 2004-06-09
Publication date: 2005-09-14
Anticipated expiration: 2014-06-09

Abstract

The utility model provides a clock detector for detecting the clock state in real time, especially for detecting whether the clock exists or not sensitively. The clock detector of the utility model comprises two counters which are respectively switched in reference clock signals and are respectively switched in the signal of the detected clock in forward and reverse directions. The counters respectively output the count results to two detecting modules which output ultimate detection result by using an AND gate. The work of the clock detector is implemented by a programmable logic device. One counter is connected with the signal of the detected clock, the other counter is connected with an inverter, and the other end of the inverter is connected with the detected signal. The signal of the reference clock is generated by a crystal resonator. If the detected clock exists, the zero-clearing action of the two counters are alternatively realized without stopping, and the maximum value can not be countered forever. If the detected clock is lost, no matter the low level or the high level is kept, the one counter must be counted to the maximum value because the zero-clearing action of the one counter can not be reset; therefore, the detection of the detected clock is implemented.

Description

Clock detecting device

Affiliated technical field:

The utility model belongs to data communication field, relates in particular to the clock detecting device in a kind of data communication system.

Background technology:

In data communication system, the stability of system usually requires very high, and clock often is a signal indispensable in the total system, if loss of clock, the total system state that will paralyse can't normally move.So, in system, pay special attention to the quality of clock status, this just need carry out clock detection.

Clock monitoring method commonly used is the mode that adopts counter, and as shown in Figure 1, counter is unidirectional not round-robin counter, counts from zero after promptly resetting, and stops to remain unchanged after meter is full.The asynchronous reset pin of counter is connected on the global reset signal, when system reset, and counter O reset.Measured clock is connected on the input pin of counter, if measured clock exists, the end back counter that then resets begins normal counting, stops to keep after meter is full.Detection module realized by a comparer, when the count results of counter greater than the numerical value of setting in advance (can be one greater than zero and less than the peaked number of counter), testing result output high level then, the expression measured clock is correct.Otherwise if measured clock does not exist, then counter can not counted, and remains zero constantly always, and the result of comparer comparison is the numerical value that is not more than prior setting, and the testing result output low level illustrates that measured clock is incorrect.

Consider a spot of counting that the interference above the signal may cause when need filter out measured clock did not exist, usually the comparison numerical value of prior setting be provided with big a little, monitoring result may be better.But this detection measured clock method, if measured clock originally be exist but work a period of time lost, according to above method, because the count results of counter remains unchanged, so have no idea to detect.

The utility model content:

Whether the purpose of this utility model is to provide a kind of clock detecting device, detects clock status in real time, particularly sensitive detect clock and exist, and promptly can detect soon behind loss of clock.

Clock detecting device of the present utility model, comprise two counters, each all inserts reference clock signal counter, and inserts positive and negative two respectively to the measured clock signal, counter is respectively to two detection modules output count results, and two detection modules are by exporting final detection result with door.

Above-mentioned clock detecting device is realized by programmable logic device (PLD).

One of two counters directly insert the measured clock signal, and another inserts measured signal by phase inverter.

Reference clock signal produces by crystal oscillator.

Clock detecting device described in the utility model is counted reference clock by two unidirectional not round-robin counters, gives two counter O resets (a high level zero clearing, another low level zero clearing) by measured clock.If measured clock exists, then two counters quilt that will not stop replaces zero clearing, and no matter accounting if measured clock has been lost, has kept low level or high level to maximal value never, must have a counter to count maximal value because of the zero clearing that can not get resetting.Thereby by the detection of testing circuit realization to measured clock.

The clock detection method of mentioning in the utility model, detection clock status that can be real-time, can be sensitive detect clock and whether exist promptly can detect behind loss of clock soon.

The clock detection method of mentioning in the utility model, can be applied to needs in any system of clock detection.Especially be applied to the exigent system of testing result.

Clock detection method described in the utility model can also be applied in computing machine or the communication facilities in any communicating equipment product that the clock detection demand arranged, and is with a wide range of applications.

Description of drawings:

Fig. 1 is a kind of theory diagram that carries out the method for clock detection by counter

Fig. 2 is a kind of theory diagram of clock detection circuit

Embodiment:

The utility model implementation procedure is:

1) two counters of design, unidirectional not round-robin, promptly the completely back count value of counter meter remains unchanged;

2) input end of counter inserts reference clock, and this clock is directly produced by crystal oscillator, can not lose, if two counters do not reset, will start from scratch and count maximal value and stop;

3) the asynchronous reset interface of a counter inserts measured clock, the asynchronous reset interface of another counter inserts the reverse signal of measured clock, like this, if measured clock exists, then two counters quilt that will not stop replaces zero clearing, and accounting is to maximal value, if measured clock has been lost never, no matter be parked in high level or low level, a counter meter will be arranged to maximal value;

4) detect the count results of two counters by testing circuit, if the count results of two counters is not a maximal value, illustrate that then measured clock exists and do not lose, if the count results meter of any one counter has arrived maximal value, illustrate that then measured clock does not exist or lost.

As shown in Figure 2, counter 1 sum counter 2 all is 4 a counter, and their counting region is 0-15, and do not circulate, both when the counter meter to 15 the time, if do not reset, it will keep 15 constant always, even the clock input is arranged, it can not return 0 counting again yet; In addition, counter 1 is that high level resets, and counter 2 is that low level resets.

Two count results detection modules are identical, and it is realized by a comparer, when the input of comparer equals 15, and count results detection module output high level then, when the input of comparer is not equal to 15, count results detection module output low level then.

The incoming frequency of reference clock is the crystal oscillator output of 50M, and the clock frequency of measured clock can be high and 2M and the clock that is lower than 200M.The frequency that why limits measured clock need be higher than 2M, be to determine by the frequency of reference clock and the counting region of two counters, because it is 280ns that the reference clock of 50M count down to for 15 needed times, so, if the frequency of measured clock is lower than 2M, then before counter meter to 15, zero clearing may be also had little time, testing goal can't be realized; The frequency that why limits measured clock need be lower than 200M, is that the level width by the asynchronous resetting signal of general counter (particularly can by becoming logic realization) can not too short deciding of time.

The output of two count results detection modules through one with behind the door, output as whole clock detection circuit, the output of having only two count results detection modules all is high level, the output of whole clock detection circuit can be high level, thereby reaches the purpose that real-time, sensitive detection clock has or not.

Claims

1, a kind of clock detecting device, comprise two counters, two detection modules, it is characterized in that counter all inserts reference clock signal, and insert positive and negative two respectively to the measured clock signal, counter connects two detection modules respectively, and two detection modules are output as final detection result by being connected with door with door.

2, clock detecting device as claimed in claim 1 is characterized in that one of two counters connect the measured clock signal, and another counter connects a phase inverter, and the phase inverter other end connects the measured clock signal.

3, clock detecting device as claimed in claim 1 or 2 is characterized in that reference clock signal produces by crystal oscillator.