CN2599652Y

CN2599652Y - Entrance guard dog checking circuit

Info

Publication number: CN2599652Y
Application number: CNU022891382U
Authority: CN
Inventors: 李延松
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-12-04
Filing date: 2002-12-04
Publication date: 2004-01-14
Anticipated expiration: 2012-12-04

Abstract

A dog clearance circuit for watchdogs is arranged between a processor and a watchdog timer, including a decoder, address signals form the processor, data signals, an input terminal to input write signals into the decoder, as well as a counter and a counting enable controller. Wherein, the output terminal of the decoder is connected with the clear terminal of the counter; the external clock signals from the dog clearance circuit for watchdogs are input to the clock terminal of the counter; any output signal of the counter is treated as dog clearance signal and input to the dog clearance terminal of the watchdog timer; one or more than one output signal of the counter is respectively input to the input terminal of the counting enable controller; the output terminal of the counting enable controller is connected with the enable terminal of the counter; and the control signal from the processor is input to the selection input terminal of the counting enable terminal. The utility model solves the problem of being unable to handle the dog clearance in time when the processor is busy and flexibly sets up or adjusts the time interval of dog clearance by processor.

Description

The clear dog circuit of a kind of house dog

Technical field

The utility model relates to processor monitoring field, specifically, relates to the clear dog circuit of a kind of house dog.

Background technology

In built-in fields such as network service, process control, intelligence instruments, the reliability of system is an important indicator.Under the electromagnetic interference (EMI) in the external world, processor may cause service disconnection even accident because deadlock appears in address or error in data.For fear of human intervention, usually require system to return to original state by automatically reseting, restart operation then.Usually, adopt the processor supervisory circuit to come the assurance system to recover normal operation from soft, hard error, described processor supervisory circuit is called WatchDog Timer (WDT) again.

The ultimate principle of WDT is: when the processor operate as normal, processor constantly sends clear dog pulse to WDT in the official hour interval, when processor crashes, because inner treater can not send clear dog pulse to WDT at the official hour interval, WDT will produce reset signal with processor reset, after this, processor restarts executive routine, and continues clear on time dog.

In the embedded system of using WDT, adopt clear dog mode as shown in Figure 1 usually.Programmable logic device (PLD) (PLD, Programmable Logic Device) address signal, data-signal and the write signal of from processor are deciphered, export clear dog signal at a certain time interval and give the clear dog end WDI of WDT circuit, the reset signal of WDT circuit output is then given processor and other important circuit.

Yet, because processor heavy traffic sometimes, cause processor to surpass the maximum clear dog time interval and can't export clear dog signal, cause WDT to take for processor and break down and maloperation takes place, export reseting signal reset processor and total system, thereby cause the termination of regular traffic.

For example, the processor supervisory circuit is ADM706 or MAX706 WatchDog Timer, and the maximum clear dog time interval of its requirement is 1.6 seconds, and can not revise.If processor is in time unclear dog in 1.6 seconds, WDT will export reseting signal reset processor and total system, the operation of termination handler regular traffic.

Although now adjustable processor supervisory circuit of the clear dog time interval occurred, be to use not extensively, cost is also higher, and the time interval adjustable extent of clear dog can not be provided with according to actual needs flexibly.

The utility model content

The purpose of this utility model is to provide a kind of house dog clear dog circuit, solving under the situation of processor heavy traffic the problem of clear dog in time, and is provided with or adjusts the time interval of the clear dog of processor as required flexibly.

The utility model is realized by following concrete technical scheme:

The clear dog circuit of a kind of house dog, between processor and WatchDog Timer, comprise a code translator, the address signal of from processor, data-signal, and write signal inputs to the input end of described code translator, the clear dog circuit of described house dog comprises that also counter and counting enable controller, wherein, the output terminal of code translator is connected to the clear terminal of counter, input to the clock end of counter from the clock signal of the clear dog circuit of house dog outside, arbitrary count output signal of counter inputs to the clear dog end of WatchDog Timer as clear dog signal, the one or more count output signal of counter inputs to the input end that described counting enables controller respectively, count the Enable Pin that the output terminal that enables controller is connected to counter, the control signal of from processor inputs to the selection input end that counting enables controller.

The output signal of the rolling counters forward output terminal that links to each other with the clear dog end of described WatchDog Timer satisfies the requirement of the clear dog signal frequency of watchdog circuit.

Enabling the time interval that rolling counters forward output terminal that the input end of controller links to each other exports the required prolongation of clear dog signal according to processor with described counting chooses.

Described counting enables controller and imports one tunnel selection circuit of exporting for the N road, and wherein N delivers to the way of described selection circuit for the rolling counters forward output signal.

Described code translator, counter and counting enable controller and can be realized by programmable logic device (PLD).

Described clock signal is a monoboard clock signal.

The utility model set up a counter before the clear dog end of WDT and counting enables controller, has following characteristics:

(1) owing to export the clear dog end that clear dog signal is delivered to WDT with the output signal simulation processor of counter, solved processor can not be in time when heavy traffic the problem of dog clearly, need not processor and participate in clear dog.

(2) because according to the requirement of watchdog circuit to clear dog signal, the output signal of the various frequencies of gated counter makes the clear dog circuit of this house dog be applicable to the WatchDog Timer of various chip models as clear dog signal neatly.

(3) according to time of the required prolongation of the time interval of the clear dog of processor, the output signal that any output signal of choosing counter neatly enables controller as counting feeds back to the Enable Pin of counter, counting with control counter, thereby realized being provided with or adjusting flexibly as required the time interval of the clear dog of processor, and when processor is carried out time-consuming operation, can not cause the veneer exceptional reset owing to having little time clearly dog.

(4) because enabling all available PLD of controller, the counter, code translator, the counting that are adopted realize that for the veneer that uses the PLD circuit, change and only limit to PLD inside, the hardware configuration of veneer changes little, has simplified design soft, hardware.

Description of drawings

Fig. 1 is the clear dog mode synoptic diagram of prior art;

Fig. 2 exports the circuit theory diagrams in the time interval of clear dog signal for prolonging processor;

Fig. 3 is the oscillogram of the clear dog circuit of the utility model house dog.

Embodiment

For make the purpose of this utility model, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the utility model is further described.

The utility model is exported the time interval of clear dog signal in order to prolong processor, before the clear dog end of WDT, set up a counter and counting enables controller, export clear dog signal and deliver to the clear dog end of WDT with the output signal simulation processor of counter, enable the gate time of controller control counter with counting, with realization be set the time interval of dog clearly as required flexibly, and processor needn't be exported clear dog signal at interval by the maximum time of WDT.

Referring to shown in Figure 2, Fig. 2 exports the circuit theory diagrams in the time interval of clear dog signal for prolonging processor.The clear dog circuit of this house dog comprises that at least code translator, counter, counting enable controller, in Fig. 2, is that example illustrates with 8 digit counters.The address signal of from processor, data-signal and write signal input to the input end of code translator, and the output signal of code translator is delivered to the clear terminal of counter as the reset signal of counter; Deliver to the clock end of counter as the count pulse of counter from the clock signal of veneer, arbitrary count output signal of counter output is delivered to the clear dog end of WDT as clear dog signal, because the count output signal cycle of the different terminal count outputs of counter is all inequality, can require to select according to the clear dog signal frequency of WDT circuit, as long as clear dog signal exists always, the WDT circuit just can be with processor reset, for example, and with the terminal count output Q of counter among Fig. 2 ₀Output signal export the clear dog end of WDT to as clear dog signal; Export the time of the required prolongation of the time interval of clear dog signal according to processor, one or more count output signals of choosing counter input to the input end that counting enables controller, count the output signal that enables controller and deliver to the counting Enable Pin of counter, the control signal of from processor is delivered to the selection input end that counting enables controller, in Fig. 2, the input signal that counting enables controller is taken from high 4 terminal count output signals of counter, and this circuit can be imported 4 of 1 tunnel output and select one to select circuit for one 4 the tunnel.Described counting enables controller two effects, and the one, be used for the control that enables of counter, i.e. counting or maintenance, in case reach predefined count value, counter will stop counting, no longer exports clear dog signal simultaneously; The 2nd, the output signal of counter is selected, promptly, enable the output signal of control signal by the road signal of selecting signal to choose in the input signal that counting enables controller as counting, the time interval of therefore clear dog can be chosen flexibly according to actual conditions.

Above-mentioned code translator, counter, counting enable controller and can use discrete circuit to realize, also available programmable logic device (PLD) realizes.

Further specify the principle of work of this clear dog circuit below in conjunction with the oscillogram of clear dog circuit shown in Figure 3.

When the address of processor output appointment, data and write signal, low level width of code translator output is greater than the output signal of clock period, with counter O reset, counter restarts counting, the signal that the counter output signal frequency is satisfied the clear dog semaphore request of WDT is as clear dog signal, promptly, the clear dog signal period is less than the maximum clear dog time interval of clear dog signal among the figure, for example ADM706 or MAX706 WatchDog Timer, the clear dog signal period should be less than 1.6 seconds, when the zero clearing of the decoded once more device output signal of counter, counter is counted again.Interval between above-mentioned adjacent two code translator output low level signals is the actual clear dog time interval of processor, and in this time interval, processor does not participate in generating clear dog signal, therefore prolonged the clear dog time interval of processor, needn't worry that processor can't clear on time dog because of heavy traffic.

In addition, also can enable controller by counting comes the control counter counting to reach predetermined count value.For example, if enabling controller, counting chooses counter output Q ₄Output signal as the control that enables of counter, then as counter Q ₄Output is during high level, and counting arrives predetermined count value, and counter just stops counting, no longer exports clear dog signal simultaneously, if clock signal period is 1 second, then can be by the regularly clear dog of clear dog circuit in 32 seconds, and do not need processor to participate in.Therefore, the output signal of gated counter output terminal enables the input signal of controller as counting neatly, suitably select clock signal period, the maximum time that can realize the clear dog of processor choosing flexibly at interval, even when no code translator output signal zero clearing, also can be set in certain time interval and provide dog signal clearly, break away from the restriction of code translator output signal by counter.In this case, be to guarantee reliability, must be before counter stops counting the clear once more dog of processor.

Claims

1, the clear dog circuit of a kind of house dog, between processor and WatchDog Timer, comprise a code translator, the address signal of from processor, data-signal, and write signal inputs to the input end of described code translator, it is characterized in that, the clear dog circuit of described house dog comprises that also counter and counting enable controller, wherein, the output terminal of code translator is connected to the clear terminal of counter, input to the clock end of counter from the clock signal of the clear dog circuit of house dog outside, the output signal of arbitrary terminal count output of counter inputs to the clear dog end of WatchDog Timer as clear dog signal, the one or more output signal of counter inputs to the input end that described counting enables controller respectively, count the Enable Pin that the output terminal that enables controller is connected to counter, the control signal of from processor inputs to the selection input end that counting enables controller.

2, the clear dog circuit of house dog according to claim 1 is characterized in that, the output signal of the rolling counters forward output terminal that links to each other with the clear dog end of described WatchDog Timer satisfies the requirement of the clear dog signal frequency of watchdog circuit.

3, the clear dog circuit of house dog according to claim 1 is characterized in that, enables the time interval that rolling counters forward output terminal that the input end of controller links to each other exports the required prolongation of clear dog signal according to processor with described counting and chooses.

4, the clear dog circuit of house dog according to claim 1 is characterized in that, described counting enables controller and imports one tunnel selection circuit of exporting for the N road, and wherein N delivers to the way of described selection circuit for the rolling counters forward output signal.

5, the clear dog circuit of house dog according to claim 1 is characterized in that, described code translator, counter and counting enable controller and realized by programmable logic device (PLD).

6, the clear dog circuit of house dog according to claim 1 is characterized in that, described clock signal is a monoboard clock signal.