CN104216807B - A kind of spaceborne computer self-refresh cuts machine system - Google Patents
A kind of spaceborne computer self-refresh cuts machine system Download PDFInfo
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- CN104216807B CN104216807B CN201410441551.1A CN201410441551A CN104216807B CN 104216807 B CN104216807 B CN 104216807B CN 201410441551 A CN201410441551 A CN 201410441551A CN 104216807 B CN104216807 B CN 104216807B
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Abstract
The invention provides a kind of spaceborne computer self-refresh and cut machine system, self-refresh design is adopted to improve arbitration circuit self anti-single particle ability, adopt system reset program independently to switch minimizing and cut machine number of times, overcome tradition and cut the protection of self single-particle of machine system less, cut machine shortcoming frequently.Because FPGA sensitivity in space environment of SRAM technique easily single event occurs, high-grade anti-fuse FPGA price is high not easily to be purchased, FPGA is not used in the present invention, adopt succinct digital circuit, control equipment cost, improve reliability, there is the feature of price economy, good reliability.
Description
Technical field
The invention belongs to electronic technology field on Satellite, particularly a kind of spaceborne computer self-refresh cuts machine system.
Background technology
Spaceborne computer is the core component of electronic system on Satellite, and usually need management and the control task of responsible whole star, its reliability directly affects the reliability of whole star.The ruuning situation of a large amount of satellite in orbit shows; due to the impact by space environment; even if take a series of radioresistance measure; board computer system still inevitably affects by space environment factor and occurs that logic is abnormal or lost efficacy; safe and reliable in order to ensure whole star, spaceborne computer adopts the mode of standby machine dual-host backup usually.
Board computer system resets and can get rid of the fault recovered of burst to a certain extent.When can not remove fault when resetting, by cutting machine to get rid of.Practical situations shows, can effectively fix a breakdown although cut machine, also brings the loss of the spaceborne computer operational data of work at present.Therefore, from the angle of the continuous reliability service of whole star, it is desirable to ensureing that on the basis that fault is effectively got rid of, machine number of times is cut in minimizing as far as possible.
Existing spaceborne computer is cut machine and is detected mainly through house dog the accumulation occurrence number that dog stings signal, as long as accumulation reaches 2 times or 3 times, just carries out autonomous active-standby switch.
Application number 201010298019.0, denomination of invention for " a kind of spaceborne computer based on FPGA independently cuts machine system " although Chinese invention patent solve fault under independently cut the problem of machine, but, first, this patent is not to the consideration that the anti-single particle ability of arbitration circuit itself designs, when single-particle inversion occurs arbitration circuit itself, wholely cut dynamo-electric road and will occur unexpected output, cause the system failure; The second, this patent adopts the higher FPGA of price to design, and cost performance is not high.
In space environment, the application of single event to electronic product has extreme influence, main space single-particle inversion phenomenon.For adapting to space radiation environment, spaceborne computer is generally two-shipper or multimachine design, when airliner fault to a certain extent after, to be undertaken when airliner switches by cutting dynamo-electric road, thus raising system anti event of single particle ability.Traditional machine of cutting design functionally can realize independently cutting machine under fault, but ignore arbitration circuit itself and the risk of single-particle inversion occurs, single-particle inversion risk occurs will lead to system abnormity that appearance is such as improper cuts the abnormal resultses such as machine if form the FPGA that cuts dynamo-electric road and middle small scale integrated circuit self.
Summary of the invention
In order to solve the defect existed in prior art, the invention provides a kind of spaceborne computer self-refresh and cut machine system, arbitration circuit self anti-single particle ability can be improved, reduce and cut machine number of times, overcome tradition and cut the protection of self single-particle of machine system less, the shortcoming of machine is cut in easy false triggering.
In order to achieve the above object, this invention takes following technical scheme:
A kind of spaceborne computer self-refresh cuts machine system, and described spaceborne computer adopts two-shipper cold standby mechanism, and described system comprises processor minimum system, cuts machine logical circuit, steady state trigger and active-standby switch relay circuit; Processor minimum system comprises cpu circuit; The machine logical circuit of cutting comprise N number of d type flip flop, timer, one with door and one or, wherein, the D termination 5V pull-up of N>2, d type flip flop D1; The Q input end of the upper d type flip flop connected successively connects the D end of next d type flip flop; The reset signal of CPU is input to the CLK end of four d type flip flops, the Q output terminal of timer connects the R end of N number of d type flip flop, the Q output terminal of N number of d type flip flop be connected respectively to the input of door and or the input of door, steady state trigger is connected with the output terminal of door, or the output terminal of door connects the RST end of timer, the output terminal of steady state trigger connects active-standby switch relay circuit; When CPU produces reset signal, after d type flip flop D1 detects pulse, output terminal Q exports high level, and Q outputs to the RST end of timer simultaneously, and timer starts timing; When CPU sends N reset within the time that timer sets, N number of d type flip flop export high level by with send to steady state trigger behind the door, steady state trigger exports positive pulse and drives active-standby switch relay to realize spaceborne computer master to cut standby operation.
Wherein, described processor minimum system comprises CPU, SRAM, watchdog circuit, processor logic and nonvolatile flash memory NorFlash; Program is stored in Norflash, runs in sram; For preventing single-particle inversion from damaging executive routine initiating failure, program stores N part in Norflash, and automatic switchover address is found lower a program and run by each reset, and N part program adopts annular storage.
The invention has the beneficial effects as follows: the spaceborne computer self-refresh that the present invention proposes cuts machine system, self-refresh design is adopted to improve arbitration circuit self anti-single particle ability, adopt system reset program independently to switch minimizing and cut machine number of times, overcome tradition and cut the protection of self single-particle of machine system less, cut machine shortcoming frequently.Because FPGA sensitivity in space environment of SRAM technique easily single event occurs, high-grade anti-fuse FPGA price is high not easily to be purchased, FPGA is not used in the present invention, adopt succinct digital circuit, control equipment cost and improve reliability, there is the feature of price economy, good reliability.
Accompanying drawing explanation
Fig. 1 is the processor minimum system block diagram that spaceborne computer self-refresh of the present invention cuts machine system;
Fig. 2 is the structural drawing that spaceborne computer self-refresh of the present invention cuts machine system.
Embodiment
Illustrate below in conjunction with accompanying drawing and embodiment the present invention is further described.
As shown in Figure 1, the processor mini system that spaceborne computer self-refresh of the present invention cuts machine system comprises central processor unit CPU, static RAM SRAM, watchdog circuit, processor logic and nonvolatile flash memory NorFlash.Spaceborne computer adopts two-shipper cold standby mechanism, and unit is core with processor, and program is stored in Norflash, runs in sram.For preventing single-particle inversion from damaging executive routine initiating failure, program stores four parts in Norflash, and automatic switchover address is found lower a program and run by each reset, and four parts of programs adopt annular storage.Adopt aforesaid operations, can as much as possible by system reset by Failure elimination, reduce cut machine number of times.Repeatedly reset when detecting in certain hour section, system thinks that unit on duty is insincere, carries out cutting machine.Cut machine logical circuit to gather the reset signal that spaceborne computer sends, undertaken leading cut standby operation by producing control signal pilot relay after logical circuit process.
Be described for N=4, when the machine logical circuit of cutting to determine in 128 seconds (every part power on after a full cycle of operation time need 32 seconds), more than 4 times, (computer system stores 4 parts of programs to spaceborne computer module resets, often reset and once switch portion, as 4 parts of equal exceptional resets of program then carry out cutting machine), cut machine logical circuit control spaceborne computer power supply relay realization master and cut standby.
Accompanying drawing 2 is structural drawing that spaceborne computer self-refresh of the present invention cuts machine system, comprises processor minimum system, cuts machine logical circuit, steady state trigger and active-standby switch relay circuit.Processor minimum system comprises cpu circuit, and cpu circuit comprises main part CPU and backup CPU.Be described for N=4.The machine logical circuit of cutting comprise 4 d type flip flops, timer, one with door and one or, wherein, the D termination 5V pull-up of d type flip flop D1, the Q input end of a upper d type flip flop connects the D end of next d type flip flop, cpu reset signal is input to the CLK end of four d type flip flops, the Q output terminal of timer connects the R end of four d type flip flops, the Q input end of four d type flip flops is connected respectively to and door or door, be connected steady state trigger with the output terminal of door, or the output terminal of door connects the RST end of timer.The output terminal of steady state trigger connects active-standby switch relay circuit.
When CPU produces reset signal, d type flip flop D1 exports high level to output terminal Q after pulse being detected, and Q outputs to the RST end of timer Counter simultaneously, and timer Counter starts counting.Set timer is 128 seconds.
When CPU sent four resets in 128 seconds, four d type flip flops export high level by with send to steady state trigger (74LS123) behind the door, steady state trigger 74LS123 exports 160 ± 10ms positive pulse and drives magnetic latching relay to realize spaceborne computer master to cut standby.
D type flip flop is the key realizing logic in invention, is easier to in-orbit space single-particle inversion occurs.The present invention avoids single event upset by ingenious combination and causes and cut the false triggering of machine switch.(" 0 " is exported during any one d type flip flop generation single-particle inversion, upset is " 1 "), have employed and door owing to exporting, false triggering can not cut machine switch, simultaneously, any d type flip flop output terminal Q be " 1 " by enable timer, after timer timing in 128 seconds terminates, 4 d type flip flop output states refresh clear " 0 " by system.
Because FPGA sensitivity in space environment of SRAM technique easily single event occurs, high-grade anti-fuse FPGA price is high not easily to be purchased, and does not use FPGA, adopts succinct digital circuit, control equipment cost and improve reliability in the present invention.
Under the guiding theory of microsatellite " fast, good, province ", the present invention starts with from system, self-refresh design is adopted to improve arbitration circuit self anti-single particle ability, adopt system reset program independently to switch minimizing and cut machine number of times, overcome tradition and cut the protection of self single-particle of machine system less, cut machine shortcoming frequently.The present invention has the feature of price economy, good reliability.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (7)
1. spaceborne computer self-refresh cuts a machine system, and described spaceborne computer adopts two-shipper cold standby mechanism, it is characterized in that, described system comprises processor minimum system, cuts machine logical circuit, steady state trigger and active-standby switch relay circuit; Processor minimum system comprises cpu circuit; The machine logical circuit of cutting comprise N number of d type flip flop, timer, one with door and one or, wherein, the D termination 5V pull-up of N>2, d type flip flop D1; The Q input end of the upper d type flip flop connected successively connects the D end of next d type flip flop; The reset signal of CPU is input to the CLK end of N number of d type flip flop, the Q output terminal of timer connects the R end of N number of d type flip flop, the Q output terminal of N number of d type flip flop is all connected to the input with door, the Q output terminal of N number of d type flip flop is all connected to or the input of door, steady state trigger is connected with the output terminal of door, or the output terminal of door connects the RST end of timer, the output terminal of steady state trigger connects active-standby switch relay circuit; When CPU produces reset signal, after d type flip flop D1 detects pulse, output terminal Q exports high level, and Q outputs to the RST end of timer simultaneously, and timer starts timing; When CPU sends N reset within the time that timer sets, N number of d type flip flop export high level by with send to steady state trigger behind the door, steady state trigger exports positive pulse and drives active-standby switch relay to realize spaceborne computer master to cut standby operation.
2. spaceborne computer self-refresh according to claim 1 cuts machine system, it is characterized in that: described processor minimum system comprises CPU, SRAM, watchdog circuit, processor logic and nonvolatile flash memory NorFlash; Program is stored in Norflash, runs in sram; For preventing single-particle inversion from damaging executive routine initiating failure, program stores N part in Norflash, and automatic switchover address is found lower a program and run by each reset, and N part program adopts annular storage.
3. spaceborne computer self-refresh according to claim 2 cuts machine system, it is characterized in that: described N be greater than 2 round values.
4. spaceborne computer self-refresh according to claim 1 cuts machine system, it is characterized in that: described timer is set greater than and equals 32*N second.
5. spaceborne computer self-refresh according to claim 1 cuts machine system, it is characterized in that: the model of described steady state trigger is 74LS123.
6. spaceborne computer self-refresh according to claim 1 cuts machine system, it is characterized in that: steady state trigger exports 160ms ± 10ms positive pulse.
7. spaceborne computer self-refresh according to claim 1 cuts machine system, it is characterized in that: described active-standby switch relay is magnetic latching relay.
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| CN107994890B (en) * | 2017-12-28 | 2023-09-01 | 中国科学院西安光学精密机械研究所 | Internal reset circuit and method for satellite-borne refrigerator controller based on anti-fuse FPGA |
| CN108762994B (en) * | 2018-06-06 | 2022-04-12 | 哈尔滨工业大学 | Satellite-borne computer system based on multi-computer backup and computer switching method of system |
| CN110988649B (en) * | 2019-11-22 | 2021-11-09 | 中国电子科技集团公司第五十八研究所 | Anti-fuse type FPGA programming waveform generation circuit and anti-fuse detection method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101833536A (en) * | 2010-04-16 | 2010-09-15 | 北京航空航天大学 | Reconfigurable on-board computer of redundancy arbitration mechanism |
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| CN101968756B (en) * | 2010-09-29 | 2012-07-18 | 航天东方红卫星有限公司 | Satellite-borne computer autonomously computer switching system based on field programmable gata array (FPGA) |
| CN103116535B (en) * | 2011-11-17 | 2016-09-07 | 上海航天测控通信研究所 | Spaceborne dual redundant main frame working state monitoring and the autonomous switching device of fault |
| CN102650962B (en) * | 2012-04-10 | 2015-04-08 | 北京航空航天大学 | Soft core fault-tolerant spaceborne computer based on FPGA (Field Programmable Gata Array) |
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| CN101833536A (en) * | 2010-04-16 | 2010-09-15 | 北京航空航天大学 | Reconfigurable on-board computer of redundancy arbitration mechanism |
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Address after: 518000 whole building of satellite building, 61 Gaoxin South Jiudao, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Aerospace Dongfanghong Satellite Co.,Ltd. Address before: 518057 room 910, block D, Shenzhen Institute of space technology innovation, South 10th Road, Science Park, Nanshan District, Shenzhen City, Guangdong Province Patentee before: AEROSPACE DONGFANGHONG DEVELOPMENT Ltd. |
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