CN100542076C - A kind of watchdog circuit input pulse time interval monitoring - Google Patents

Abstract

The present invention relates to a kind of watchdog circuit input pulse time interval monitoring, comprising: module one: the pulse signal of software being exported to watchdog circuit is converted to level signal output; Module two: comprise a counter, the clear terminal of this counter is connected with the output of module one, and the counter outputting data signals is given module three; Module three: the data message of record and storage input.Utilize the time interval of device of the present invention logging software output pulse in system's running and produce warning information, simplify the test that software is exported to the pulse interval of watchdog circuit, can play very big help for the location of exceptional reset problem.

Description

A kind of watchdog circuit input pulse time interval monitoring

Technical field

The present invention relates to the software test field, refer to especially a kind of software be exported to the device that the pulse interval of watchdog circuit is monitored.

Background technology

In order to guarantee the reliability of telecommunication apparatus software and hardware system, all there is watchdog circuit (Watch Dog) in general system, and whether the software work that is used for monitoring system is normal.Usually software is by regularly sending pulse to give watchdog circuit, and the expression software work is normal; If the overtime pulse signal of not receiving of watchdog circuit then can be thought software anomaly and resetting system.Watchdog circuit all has the input pulse time interval of a maximum, in case twice input pulse interval greater than this maximum time at interval, system will be reset.In order to guarantee under the normal condition that the task that software may be carried out can not cause system reset, the actual input pulse time interval of general design will be far smaller than maximum impulse interval input time of " house dog " circuit.But when some particular tasks of software processes, may not guarantee in time to export pulse and give watchdog circuit.

When we test a software, can be in all cases, the actual pulse interval of exporting to house dog of testing software, common watchdog pulse interval input time method of testing is: the various condition of work of manufacturing system, give with the oscilloscope monitoring software watchdog circuit pulse signal maximum time at interval, guarantee that this spaced far less than the maximum input pulse time interval of watchdog circuit maximum time.After software has change, carry out this maximum burst length again and test at interval, the assurance system can be owing to untimely being reset exported in pulse.But in fact be difficult to all working conditions of simulation softward, this will cause test to omit.On the other hand, if it is not comprehensive that the software of revising is not carried out the test or the test of this respect, all the problem that system under normal circumstances resets might appear.

When system powered on, before the normal operation of CPU, the pulse interval that software is exported to house dog more be cannot say for sure card, and is difficult to record, and going wrong is difficult to the location.

Summary of the invention

In view of the foregoing, the invention provides a kind of input pulse time interval monitoring of watchdog circuit, export to the pulse interval information of watchdog circuit in order to record, storing software, and can when pulse interval surpasses the thresholding that presets, produce alarm.

A kind of watchdog circuit input pulse time interval monitoring of the present invention comprises: module one, module two and module three, wherein:

Described module one comprises: three first d type flip flops, input anti-phase with door and one first or door, the clock signal input terminal of described three first d type flip flops is connected, the data terminal of first first d type flip flop receives the pulse signal of watchdog circuit, the output of first first d type flip flop connects the data terminal of second first d type flip flop, the output of second first d type flip flop connects the data terminal and the positive input described and door of the 3rd first d type flip flop respectively, the output of the 3rd first d type flip flop connects inverting input described and door, described with the door output termination first or the door an input, first or another input of door connect reset signal, this is first or the output outputs level signals of door years old;

Described module two comprises: a counter of presetting a plurality of time thresholds, one second or door and a plurality of second d type flip flop, the clear terminal of described counter is connected with the output of first or door of module one, the output of counter links to each other with data/address bus, the clock end of described each second d type flip flop connects the different pieces of information line of described data/address bus respectively according to the different time thresholding of setting, and the output of each second d type flip flop is exported the alarm signal of different stage respectively; Described second or input of door connect reset signal, another input receives the alarm clearance signal that is used to remove alarm, this second or the output of door be connected with the asynchronous resetting end of each second d type flip flop;

Described module three comprises: first latch, second latch, comparator, selector and fifo queue module; The output of first first d type flip flop in the clock end difference link block one of described first latch, second latch and fifo queue module; The data terminal of described first latch and fifo queue module is by the output of counter in the data/address bus link block two, the output of described first latch connects an input of comparator and selector respectively, the output of described comparator connects the selecting side of selector, the output of selector connects the input of second latch, to the big person of two input inputs of the second latch input selector, the output of described second latch connects another input of comparator and selector respectively; Described first latch is output as the intermediate data that latchs, and described selector gets off the pulse interval data record of current maximum; Described fifo queue module is used for writing down the watchdog circuit input pulse time interval information in a period of time.

Described counter is 16 digit counters of band asynchronous resetting end.

Utilize device of the present invention, surpassing the different time pocket door of setting in input pulse time interval prescribes a time limit, produce the alarm of different stage, and record watchdog circuit input pulse time interval information, in time pinpoint the problems and revise, avoid testing the system reset problem that causes of omitting, simplify the test that software is exported to the pulse interval of watchdog circuit.

Description of drawings

Fig. 1 is the structural representation of module one and module two in the supervising device of the embodiment of the invention.

Fig. 2 is the structural representation of module three in the supervising device of the embodiment of the invention.

Embodiment

Be example so that two time interval thresholdings to be set below, specify structure of the present invention and worker and organize principle.

If the maximum input pulse time interval of watchdog circuit is 1.2 seconds, when surpassing 0.5 second, software output pulse interval produces minor alarm, produce high severity alarm when pulse interval surpasses 1 second, promptly be provided with 0.5 second and 1 second two pulse interval thresholding (quantity of alarming threshold and threshold value can be provided with according to actual needs).

Apparatus structure of the present invention is divided into three modules as shown in Figure 1 and Figure 2, and module one is finished the conversion of porch to level signal; Module two is alarmed with producing at interval by the counting mode monitoring time; Module three is finished the stored record of input pulse time interval.

Among Fig. 1:

FEED is that software is exported to the watchdog circuit pulse signal;

CK10M is the clock of 10MHz;

RESET is the reset signal of system, the high level resetting system;

CK1K is the clock signal of 1KHz;

CLR is the signal that is used for the overtime alarm of the erase pulse time interval of software output, and high level is removed;

CLEAR exports the signal that pulses switch becomes level with software, and high level is used for counter O reset;

ALM0 is minor alarm output signal (alarm when pulse interval surpasses 0.5 second), and high level is represented alarm;

ALM1 is high severity alarm output signal (alarm when pulse interval surpasses 1 second), and high level is represented alarm;

LOAD is used for the clock signal (using in module three) that burst length information latchs.

As shown in Figure 1, three d type flip flop FD adopt the cascade of CK10M clock signal in the module one.The FEED pulse signal of software output is connected to the data terminal of first order trigger, and the CK10M clock signal is connected to the clock end of trigger; The Q end (output) of first order trigger is the LOAD signal, is used for the latch signal (using in module three) of house dog input pulse time interval information; The output of the second level and third level trigger through an input anti-phase with door AND2B1 with, with output conduct or the input of an OR2; Or another of door be input as RESET signal (reset signal), or the signal of CLEAR as a result be used for the zero clearing of module two counters.This circuit is converted to the rising edge of FEED pulse high level---the CLEAR signal of a CK10M clock cycle width, and avoiding the FEED Chief Signal Boatswain time is the circuit malfunction that fixing level causes.

Module two mainly is made up of the 16 digit counter CC16CE of band asynchronous resetting end and the d type flip flop FDC of two band asynchronous resetting ends.The clock signal C K1K of 1KHz is connected to the clock end of counter, and the CLEAR reset signal of module one output is connected to the asynchronous resetting end of counter, and the output of counter is connected to data/address bus Q15～Q0; The alarm clearance signal CLR of reset signal RESET and software output through or door OR2 mutually or, export the asynchronous resetting end that is connected to two trigger FDC; The data terminal of two triggers is received VCC (power end); Data-signal Q9 is connected to the clock end of first trigger, and the output of this trigger is exactly minor alarm signal ALM0; Data-signal Q10 is connected to the clock end of second trigger, and the output of this trigger is exactly high severity alarm signal ALM1.ALM0, ALM1 alarm signal be in case produce, and it is normal and eliminate can not export pulse-recovery because of software, has only by the alarm of CLR signal removal, can guarantee like this that the pulse interval of moment is long also can be caught in.

Among the present invention, the pulse signal that module one is sent software is converted to level the counter in the module two is carried out zero clearing, and counter restarts counting after the zero clearing.Also do not receive pulse next time if surpass the time interval thresholding of first setting, just produce other alarm of lowermost level; The time interval thresholding that surpasses second setting is not received pulse next time yet, just produces the alarm of next higher level.By that analogy, a plurality of pulse interval thresholdings and alarm can be set.

Fig. 2 is the structural representation of module three.

Among Fig. 2:

The LOAD signal is the clock signal that is used to latch watchdog circuit input pulse time interval information that module one produces;

Q[15:0] be the data/address bus of counter output in the module two, expression Q15～Q0;

S[15:0] be the intermediate data that Q latchs through one-level, expression S15～S0;

R[15:0] be the pulse maximum time interval of the software output of record, expression R15～R0;

In the module three with the data/address bus of module two counters output Q[15:0] be connected to the data terminal of latch 1, the LOAD signal of clock end connection module one output of latch 1, latch is output as the intermediate data S[15:0 that latchs]; Intermediate data S[15:0] and the maximum burst length of record R[15:0 at interval] being connected respectively to two inputs of comparator, comparative result is connected to the selecting side of selector; Two inputs of selector connect R[15:0 respectively] and S[15:0], the output result is big person between the two, and is connected to the input of latch 2, the LOAD signal is connected to the clock end of latch 2, and the pulse interval data record of current maximum is got off; FIFO is a fifo queue, the counter output in its data terminal link block two, and clock end connects the LOAD signal, is used for writing down the watchdog circuit input pulse time interval information in a period of time.Software can be by the maximum burst length interval and the interior for the previous period pulse spacing information of external interface access record.By these data, can export the variation of pulse interval and carry out labor unusually software, the location clue of output pulse interval problem under the various situations in back that power on is provided.

Export in the pulse interval test of watchdog circuit at software, utilize device of the present invention, just can test easily, the influence at interval of assessment software each several part paired pulses output time.The time interval and the warning information of logging software output pulse can play very big help for the location of exceptional reset problem in system's running.

After software has been done to revise, there is no need specialize software output this test of burst length, after a period of time, only observe pulse output time alarm and data just passable at running software.When the exceptional reset reason of location, only need check the time interval data of software output pulse and software work state at that time, just can easily orientation problem.

Because the effect of this alarm and data record, even do not do the test of pulse output time, in the checking running of software, some time intervals, big slightly pulse output function also can reflect automatically, remind the developer where to need to revise, avoided the omission of problem.

Claims (2)

1, a kind of watchdog circuit input pulse time interval monitoring is characterized in that comprising: module one, module two and module three, wherein:

Described module one comprises: three first d type flip flops, input anti-phase with door and one first or door, the clock signal input terminal of described three first d type flip flops is connected, the data terminal of first first d type flip flop receives the pulse signal of watchdog circuit, the output of first first d type flip flop connects the data terminal of second first d type flip flop, the output of second first d type flip flop connects the data terminal and the positive input described and door of the 3rd first d type flip flop respectively, the output of the 3rd first d type flip flop connects inverting input described and door, described with the door output termination first or the door an input, first or another input of door connect reset signal, this is first or the output outputs level signals of door years old;

Described module two comprises: a counter of presetting a plurality of time thresholds, one second or door and a plurality of second d type flip flop, the clear terminal of described counter is connected with the output of first or door of module one, the output of counter links to each other with data/address bus, the clock end of described each second d type flip flop connects the different pieces of information line of described data/address bus respectively according to the different time thresholding of setting, and the output of each second d type flip flop is exported the alarm signal of different stage respectively; Described second or input of door connect reset signal, another input receives the alarm clearance signal that is used to remove alarm, this second or the output of door be connected with the asynchronous resetting end of each second d type flip flop;

Described module three comprises: first latch, second latch, comparator, selector and fifo queue module; The output of first first d type flip flop in the clock end difference link block one of described first latch, second latch and fifo queue module; The data terminal of described first latch and fifo queue module is by the output of counter in the data/address bus link block two, the output of described first latch connects an input of comparator and selector respectively, the output of described comparator connects the selecting side of selector, the output of selector connects the input of second latch, to the big person of two input inputs of the second latch input selector, the output of described second latch connects another input of comparator and selector respectively; Described first latch is output as the intermediate data that latchs, and described selector gets off the pulse interval data record of current maximum; Described fifo queue module is used for writing down the watchdog circuit input pulse time interval information in a period of time.

2, supervising device as claimed in claim 1 is characterized in that: described counter is 16 digit counters of band asynchronous resetting end.

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