CN114860495A - Signal monitoring method, system, equipment and storage medium - Google Patents
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Abstract
The invention provides a method, a system, equipment and a storage medium for signal monitoring, wherein the method comprises the following steps: setting a register in a processor for storing an abnormal signal and setting a data reading address pointer and a data writing address pointer; setting a timer in a processor, reading a count value of the timer in response to detecting an abnormal signal, and storing the count value into the register; storing the state of the abnormal signal to a data writing address, and moving a data writing address pointer to a first direction; and responding to the communication interval time between the processor and the BMC exceeding a threshold value, and using the time of triggering the interrupt as the time of occurrence of the next received abnormal data. The invention adopts a CPLD and BMC bidirectional timing mechanism to record the time triggered by the abnormal signal, so that the subsequent maintenance personnel can locate the reason of the abnormality according to the time of the abnormality.
Description
Technical Field
The present invention relates to the field of servers, and more particularly, to a method, system, device and storage medium for signal monitoring.
Background
In a server, a main board CPLD (Complex Programmable Logic Device) is mainly used to implement the functions of controlling the power-on and power-off timing of a board card and monitoring signals. In the running process of the server, the abnormal power failure of the server can be caused due to circuit problems or improper operation and the like. In subsequent maintenance, the power failure reason needs to be analyzed according to the abnormal power failure point, so that the CPLD is needed to record the states of all timing signals and alarm signals at the power failure moment.
The prior art method mainly includes that a CPLD monitors a timing signal and an alarm signal in real time, latches the state of a current signal into a CPLD register when an abnormal power failure or alarm occurs, and triggers an interrupt signal of a BMC (Baseboard Management Controller) through a General Purpose Input Output (GPIO) to notify the BMC to receive data. The BMC reads the data transmitted by the CPLD and records the current time. After the BMC reads successfully, the CPLD is informed to clear the data of the current register. After the data is cleared, the CPLD will continue to monitor the signal state. However, the prior art method cannot simultaneously detect two abnormal signals with short intervals. In the process of abnormal data transmission, the register for storing the signal state is in a latch state, and if the abnormal data transmission occurs again, the signal state cannot be recorded, so that the abnormal data is lost.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for signal monitoring, in which a CPLD and a BMC bidirectional timing mechanism are used to record the time of triggering an abnormal signal, so that a subsequent maintainer can locate the reason of the abnormality according to the time of the abnormality, and the problem of abnormal signal loss caused by the communication delay between the CPLD and the BMC can be avoided.
In view of the above, an aspect of the embodiments of the present invention provides a method for signal monitoring, including the following steps: setting a register in a processor for storing an abnormal signal and setting a data reading address pointer and a data writing address pointer; setting a timer in a processor, reading a count value of the timer in response to detecting an abnormal signal, and storing the count value into the register; storing the state of the abnormal signal to a data writing address, and moving a data writing address pointer to a first direction; and responding to the communication interval time between the processor and the BMC exceeding a threshold value, and using the time of triggering the interrupt as the time of occurrence of the next received abnormal data.
In some embodiments, the method further comprises: the BMC reads the current data according to the position of the data reading address pointer, clears the current data of the register in response to the completion of reading of the BMC, and moves the data reading address pointer to the first direction.
In some embodiments, said setting a register in a processor for storing an exception signal comprises: connecting the starting point and the end point of the register.
In some embodiments, said setting a register in a processor for storing an exception signal comprises: setting a second data read pointer to indicate a start point or an end point of the register to avoid overwriting previously stored data when storing.
In some embodiments, said moving said data write address pointer to a first direction comprises: and in response to the data write address pointer moving to the maximum capacity address of the register, returning to the initial position of the register.
In some embodiments, the setting the data read address pointer and the data write address pointer comprises: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the method further comprises: and in response to the register not being empty, triggering the BMC to interrupt and informing the BMC to receive an abnormal signal state.
In another aspect of the embodiments of the present invention, a system for monitoring a signal is provided, including: the application module is configured for setting a register in the processor for storing the abnormal signal and setting a data reading address pointer and a data writing address pointer; the reading module is configured to set a timer in the processor, respond to the detection of the abnormal signal, read the count value of the timer and store the count value into the register; the storage module is configured to store the state of the abnormal signal to a data writing address and move a data writing address pointer to a first direction; and the time module is configured to respond to the condition that the communication interval time between the processor and the BMC exceeds a threshold value, and the time of triggering the interrupt is used as the time of occurrence of the next received abnormal data.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the CPLD and BMC bidirectional timing mechanism is adopted to record the time triggered by the abnormal signal, so that subsequent maintenance personnel can locate the reason of the abnormality according to the time when the abnormality occurs, the problem of abnormal signal loss caused by communication delay of the CPLD and the BMC can be avoided, meanwhile, the space reuse rate of the register can be improved by using the annular register, compared with a rectangular space data storage form, data only has two states of reading and writing, and consumption and risk caused by data movement are avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method of signal monitoring provided by the present invention;
FIG. 2 is a schematic diagram of an embodiment of a system for signal monitoring provided by the present invention;
FIG. 3 is a schematic diagram of a hardware structure of an embodiment of a computer device for signal monitoring provided by the present invention;
FIG. 4 is a schematic diagram of an embodiment of a computer storage medium for signal monitoring provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of embodiments of the present invention, embodiments of a method for signal monitoring are provided. Fig. 1 is a schematic diagram of an embodiment of a signal monitoring method provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, setting a register in the processor for storing an abnormal signal, and setting a data reading address pointer and a data writing address pointer;
s2, setting a timer in the processor, reading the count value of the timer in response to the detection of the abnormal signal, and storing the count value in the register;
s3, storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and
and S4, responding to the fact that the communication interval time between the processor and the BMC exceeds a threshold value, and using the time of triggering the interrupt as the time of occurrence of the next received abnormal data.
A register is provided in the processor for storing an exception signal, and a data read address pointer and a data write address pointer are provided. Processors include, but are not limited to, CPLDs and FPGAs (Field-Programmable Gate arrays).
In some embodiments, said setting a register in a processor for storing an exception signal comprises: connecting the starting point and the end point of the register. The embodiment of the invention can apply a register in the CPLD for storing the abnormal signal.
In some embodiments, the setting the data read address pointer and the data write address pointer comprises: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
A register is applied in the CPLD for storing an abnormal signal, two pointers are arranged for indicating a data reading address and a data writing address, and the two pointers are positioned at the same position when a program starts. In order to save space occupied by the register, the register is set as a ring register, i.e. the beginning and the end of the register are connected.
In some embodiments, said setting a register in a processor for storing an exception signal comprises: setting a second data read pointer to indicate a start point or an end point of the register to avoid overwriting previously stored data when storing.
The registers physically exist in the form of stripes that exist "head-to-tail". In order to realize the ring structure of the using meaning of the register, the ring structure can be realized by setting a data writing pointer, namely when the pointer moves to the maximum capacity address of the register, the initial position of the register is returned again. And according to the form of circular movement of the pointer, realizing the function of annular storage of the register. Meanwhile, a data reading pointer needs to be additionally arranged to indicate the bottom of the ring register, so that the pointer is prevented from overwriting the previously stored data during ring storage.
Setting a timer in the processor, reading the count value of the timer in response to detecting the abnormal signal, and storing the count value into the register. And storing the state of the abnormal signal to a data writing address, and moving a data writing address pointer to a first direction.
When an abnormal signal is detected, the state of the monitoring signal is stored in the data writing address, and the data writing address pointer moves upwards at the same time. Indicating the storage location of the next exception signal.
In some embodiments, the method further comprises: and in response to the register not being empty, triggering the BMC to interrupt and informing the BMC to receive an abnormal signal state. And when the register for storing the abnormal signal is not empty, triggering the BMC to interrupt and informing the BMC to receive the abnormal signal state.
In some embodiments, said moving said data write address pointer to a first direction comprises: and in response to the data write address pointer moving to the maximum capacity address of the register, returning to the initial position of the register. When the pointer moves to the maximum capacity address of the register, the initial position of the register is returned.
In some embodiments, the method further comprises: and the BMC reads the current data according to the position of the data reading address pointer, clears the current data of the register in response to the completion of reading of the BMC, and moves the data reading address pointer to the first direction.
And reading the current data according to the position of the data reading pointer. And when the BMC reads successfully, the CPLD is informed to clear the data in the current register. After the data is successfully cleared, the data read pointer is moved upward. Indicating the next memory location to wait for data to be read.
And in response to the communication interval time between the processor and the BMC exceeding a threshold value, using the time triggering the interrupt as the time when the next received abnormal data occurs.
A timer is arranged in the CPLD, when the monitoring signal is abnormal, the counting value of the counter is read, and the counting value and the signal state of the abnormal signal are stored in an abnormal signal register. When the timer clock is set to 1MHz, the clock can be made accurate to us level. Meanwhile, in order to reduce the deviation of the timer caused by the precision problem of the CPLD internal clock, a data transmission timeout mechanism is arranged inside the BMC. When no communication occurs in a period of time, the BMC and the CPLD consider that the next received exception signal and the exception signal received this time are not continuously generated in a short time, so that the time of triggering the interrupt for the data received next time can be used as the time of the occurrence of the exception.
The embodiment of the invention adopts a CPLD and BMC bidirectional timing mechanism to record the time triggered by the abnormal signal, so that the subsequent maintenance personnel can locate the reason of the abnormality according to the time when the abnormality occurs, the problem of abnormal signal loss caused by communication delay of the CPLD and the BMC can be avoided, meanwhile, the space reuse rate of the register can be improved by using the annular register, compared with a rectangular space data storage form, data only has two states of reading and writing, and the consumption and risk caused by data movement are avoided.
It should be particularly noted that, the steps in the embodiments of the signal monitoring method described above can be mutually intersected, replaced, added, or deleted, and therefore, the method for signal monitoring based on these reasonable permutation and combination transformations shall also belong to the scope of the present invention, and shall not limit the scope of the present invention to the embodiments.
In view of the above object, according to a second aspect of the embodiments of the present invention, a system for signal monitoring is provided. As shown in fig. 2, the system 200 includes the following modules: the application module is configured to set a register in the processor for storing the abnormal signal and set a data reading address pointer and a data writing address pointer; the reading module is configured to set a timer in the processor, respond to the detection of the abnormal signal, read the count value of the timer and store the count value into the register; the storage module is configured to store the state of the abnormal signal to a data writing address and move a data writing address pointer to a first direction; and the time module is configured to respond to the condition that the communication interval time between the processor and the BMC exceeds a threshold value, and the time of triggering the interrupt is used as the time of occurrence of the next received abnormal data.
In some embodiments, the system further comprises an emptying module configured to: and reading the current data according to the position of the data reading address pointer, clearing the current data of the register in response to the completion of reading, and moving the data reading address pointer to a first direction.
In some embodiments, the application module is configured to: connecting the starting point and the end point of the register.
In some embodiments, the application module is configured to: setting a second data read pointer to indicate a start point or an end point of the register to avoid overwriting previously stored data when storing.
In some embodiments, the storage module is configured to: and in response to the data write address pointer moving to the maximum capacity address of the register, returning to the initial position of the register.
In some embodiments, the application module is configured to: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the system further comprises: and in response to the register not being empty, triggering the BMC to interrupt and informing the BMC to receive an abnormal signal state.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, setting an application register in the processor for storing an abnormal signal, and setting a data reading address pointer and a data writing address pointer; s2, setting a timer in the processor, reading the count value of the timer in response to the detection of the abnormal signal, and storing the count value in the register; s3, storing the state of the abnormal signal to a data writing address, and moving the data writing address pointer to a first direction; and S4, responding to the communication interval time between the processor and the BMC exceeding the threshold value, and using the time of triggering the interrupt as the time of the occurrence of the next received abnormal data.
In some embodiments, the steps further comprise: and reading the current data according to the position of the data reading address pointer, clearing the current data of the register in response to the completion of reading, and moving the data reading address pointer to a first direction.
In some embodiments, said setting a register in a processor for storing an exception signal comprises: connecting the start point and the end point of the register.
In some embodiments, said setting a register in a processor for storing an exception signal comprises: setting a second data read pointer to indicate a start point or an end point of the register to avoid overwriting previously stored data when storing.
In some embodiments, said moving said data write address pointer to a first direction comprises: and in response to the data write address pointer moving to the maximum capacity address of the register, returning to the initial position of the register.
In some embodiments, the setting the data read address pointer and the data write address pointer comprises: and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
In some embodiments, the steps further comprise: and in response to the register not being empty, triggering the BMC to interrupt and informing the BMC to receive an abnormal signal state.
Fig. 3 is a schematic hardware structure diagram of an embodiment of the computer device for signal monitoring provided by the present invention.
Taking the device shown in fig. 3 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection in fig. 3.
The memory 302 is a non-volatile computer-readable storage medium and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the signal monitoring method in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., implements a method of signal monitoring, by executing nonvolatile software programs, instructions, and modules stored in the memory 302.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of signal monitoring, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Any embodiment of a computer device for performing the method for signal monitoring may achieve the same or similar effects as any corresponding embodiment of the method.
The present invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs a method of signal monitoring.
Fig. 4 is a schematic diagram of an embodiment of a computer storage medium for signal monitoring according to the present invention. Taking the computer storage medium as shown in fig. 4 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method of signal monitoring can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM), or a Random Access Memory (RAM). The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of signal monitoring, comprising the steps of:
setting a register in a processor for storing an abnormal signal and setting a data reading address pointer and a data writing address pointer;
setting a timer in a processor, reading a count value of the timer in response to detecting an abnormal signal, and storing the count value into the register;
storing the state of the abnormal signal to a data writing address, and moving a data writing address pointer to a first direction; and
and in response to the communication interval time of the processor and the BMC exceeding a threshold value, using the time of triggering the interrupt as the time of occurrence of the next received abnormal data.
2. The method of claim 1, further comprising:
and the BMC reads the current data according to the position of the data reading address pointer, clears the current data of the register in response to the completion of reading of the BMC, and moves the data reading address pointer to the first direction.
3. The method of claim 1, wherein setting a register in a processor for storing an exception signal comprises:
connecting the starting point and the end point of the register.
4. The method of claim 3, wherein setting a register in the processor for storing an exception signal comprises:
setting a data read pointer to indicate a start point or an end point of the register to avoid overwriting previously stored data when storing.
5. The method of claim 3, wherein moving the data write address pointer in a first direction comprises:
and in response to the data write address pointer moving to the maximum capacity address of the register, returning to the initial position of the register.
6. The method of claim 1, wherein setting the data read address pointer and the data write address pointer comprises:
and keeping the initial positions of the data reading address pointer and the data writing address pointer consistent.
7. The method of claim 1, further comprising:
and in response to the register not being empty, triggering the BMC to interrupt and informing the BMC to receive an abnormal signal state.
8. A system for signal monitoring, comprising:
the application module is configured to set a register in the processor for storing the abnormal signal and set a data reading address pointer and a data writing address pointer;
the reading module is configured to set a timer in the processor, respond to the detection of the abnormal signal, read the count value of the timer and store the count value into the register;
the storage module is configured to store the state of the abnormal signal to a data writing address and move a data writing address pointer to a first direction; and
and the time module is configured to respond to the condition that the communication interval time between the processor and the BMC exceeds a threshold value, and use the time for triggering the interrupt as the time for the occurrence of the next received abnormal data.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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| CN202210580773.6A CN114860495A (en) | 2022-05-25 | 2022-05-25 | Signal monitoring method, system, equipment and storage medium |
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