CN112947841A - Method, device, equipment and storage medium for reading embedded flash memory data - Google Patents
Method, device, equipment and storage medium for reading embedded flash memory data Download PDFInfo
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Abstract
The invention discloses a method, a device, equipment and a storage medium for reading embedded flash memory data, which are used for effectively avoiding transient abnormality of an embedded flash memory. The method comprises the following steps: sending a reading instruction to the embedded flash memory; the reading instruction is used for requesting to read data or instructions stored in the embedded flash memory; determining whether the embedded flash memory has an abnormality; if the embedded flash memory is abnormal, the reading instruction is repeatedly sent to the embedded flash memory, and if the transient abnormal signals are not generated in a plurality of periods and the read data of the embedded flash memory are consistent, the sending of the reading instruction is stopped, and the normal state is recovered.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for reading embedded flash data.
Background
Currently, microcontroller products commonly use embedded flash memory as a built-in non-volatile memory. In the microcontroller, a flash memory stores codes of a program, the program directly runs in the flash memory, and when the power supply voltage is abnormal, the working voltage of the embedded flash memory also has abnormal conditions, so that the read instruction is incorrect, the program suddenly jumps to any position to run, the program logic is disordered, and the states of halt, abnormality and the like are generated.
In order to prevent an incorrect read instruction caused by an abnormal working Voltage of an embedded flash memory, a Power On Reset (POR)/Low Voltage Direct (LVD) circuit is usually designed in the prior art to detect an abnormal Voltage, but the POR/LVD circuit usually filters a glitch caused by an abnormal Voltage by using a filtering method, and the POR/LVD circuit has a long time for detecting the abnormal Voltage, so that the transient abnormality of the flash memory cannot be effectively avoided.
Disclosure of Invention
The embodiment of the application provides a method, a device, equipment and a storage medium for reading embedded flash memory data, which are used for effectively avoiding transient abnormality of an embedded flash memory.
In a first aspect, a method for reading embedded flash data is provided, the method comprising:
sending a reading instruction to the embedded flash memory;
determining whether the embedded flash memory has an abnormality;
and if the embedded flash memory is abnormal, repeatedly sending the reading instruction to the embedded flash memory.
Optionally, determining whether the embedded flash memory has an exception includes:
detecting whether the working voltage of the embedded flash memory is within a preset working voltage range or not according to a preset detection frequency, wherein the preset detection frequency is greater than the working frequency of the embedded flash memory;
and if the working voltage is not within the preset working voltage range, determining that the embedded flash memory is abnormal.
Optionally, determining whether the embedded flash memory has an exception includes:
obtaining first data sent by the embedded flash memory based on the reading instruction;
obtaining second data from a preset data storage area;
and if the second data is not preset data, determining that the embedded flash memory has abnormity, and discarding the first data.
Optionally, after the reading instruction is repeatedly sent to the embedded flash memory, the method includes:
determining whether a stop transmission triggering condition is satisfied;
and if the sending stopping triggering condition is met, stopping sending the reading instruction to the embedded flash memory.
Optionally, determining whether the stop sending trigger condition is satisfied includes:
determining whether the received data reading results of the preset quantity are the same or not, wherein one data reading result comprises data sent by the embedded flash memory according to the reading address of the received reading instruction for one time;
and if the preset number of data reading results are the same, determining that the sending stopping triggering condition is met, and determining one data reading result as the reading result corresponding to the reading instruction.
Optionally, after determining whether the received predetermined number of data reading results are the same, the method further includes:
if the data reading results of the preset number are different, the reading instruction is continuously sent to the embedded flash memory, and when the cumulative number of times of sending the reading instruction reaches the preset number, an abnormal interruption instruction is output.
Optionally, the method further includes:
outputting an abnormal alarm indication when the working voltage of the embedded flash memory in a preset time length is within a preset working voltage range and the variation amplitude of the working voltage in the preset time length is larger than a preset value;
suspending operation of the processor according to the abnormal alarm indication; alternatively, the first and second electrodes may be,
and controlling the embedded flash memory to stop executing the reading instruction according to the abnormal alarm indication.
In a second aspect, there is provided an apparatus for reading embedded flash data, the apparatus comprising:
the sending module is used for sending a reading instruction to the embedded flash memory;
the determining module is used for determining whether the embedded flash memory has abnormity;
the sending module is further configured to repeatedly send the reading instruction to the embedded flash memory if the embedded flash memory is abnormal.
Optionally, the determining module is configured to:
detecting whether the working voltage of the embedded flash memory is within a preset working voltage range or not according to a preset detection frequency, wherein the preset detection frequency is greater than the working frequency of the embedded flash memory;
and if the working voltage is not within the preset working voltage range, determining that the embedded flash memory is abnormal.
Optionally, the determining module is configured to:
obtaining first data sent by the embedded flash memory based on the reading instruction;
obtaining second data from a preset data storage area;
and if the second data is not preset data, determining that the embedded flash memory has abnormity, and discarding the first data.
Optionally, the apparatus further includes a second determining module, configured to:
determining whether a stop transmission triggering condition is satisfied;
and if the sending stopping triggering condition is met, stopping sending the reading instruction to the embedded flash memory.
Optionally, the second determining module is configured to:
determining whether the received data reading results of the preset quantity are the same or not, wherein one data reading result comprises data sent by the embedded flash memory according to the reading address of the received reading instruction for one time;
and if the preset number of data reading results are the same, determining that the sending stopping triggering condition is met, and determining one data reading result as the reading result corresponding to the reading instruction.
Optionally, the second determining module is further configured to:
if the data reading results of the preset number are different, the reading instruction is continuously sent to the embedded flash memory, and when the cumulative number of times of sending the reading instruction reaches the preset number, an abnormal interruption instruction is output.
Optionally, the apparatus further includes an alarm module, configured to:
outputting an abnormal alarm indication when the working voltage of the embedded flash memory in a preset time length is within a preset working voltage range and the variation amplitude of the working voltage in the preset time length is larger than a preset value;
suspending operation of the processor according to the abnormal alarm indication; alternatively, the first and second electrodes may be,
and controlling the embedded flash memory to stop executing the reading instruction according to the abnormal alarm indication.
In a third aspect, an apparatus for reading embedded flash data is provided, the apparatus for reading embedded flash data comprising:
a memory for storing program instructions;
a processor for calling the program instructions stored in the memory and executing the steps comprised in any of the methods of the first aspect according to the obtained program instructions.
In a fourth aspect, there is provided a storage medium having stored thereon computer-executable instructions for causing a computer to perform the steps included in the method of any one of the first aspect.
In a fifth aspect, a computer program product containing instructions is provided, which when run on a computer causes the computer to perform the method of reading embedded flash data described in the various possible implementations above.
In the embodiment of the application, when a command (for example, called a read command) for reading data stored in the flash memory is sent to the embedded flash memory, whether the embedded flash memory is abnormal or not can be judged, when the embedded flash memory is determined to be abnormal, the read command is repeatedly sent to the embedded flash memory, and data corresponding to the command is repeatedly read. That is to say, the embodiment of the application provides a technical scheme for effectively avoiding transient abnormality of an embedded flash memory.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application.
Fig. 1 is a schematic structural diagram of an apparatus for reading embedded flash data according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for reading embedded flash data according to an embodiment of the present disclosure;
fig. 3a is a block diagram illustrating a structure of an apparatus for reading embedded flash data according to an embodiment of the present disclosure;
FIG. 3b is a block diagram of another structure of an apparatus for reading embedded flash data according to an embodiment of the present disclosure;
fig. 4 is another schematic structural diagram of an apparatus for reading embedded flash data according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. In the present application, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
The terms "first" and "second" in the description and claims of the present application and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the term "comprises" and any variations thereof, which are intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The "plurality" in the present application may mean at least two, for example, two, three or more, and the embodiments of the present application are not limited.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document generally indicates that the preceding and following related objects are in an "or" relationship unless otherwise specified.
For ease of understanding, the technical background of the embodiments of the present invention will be described below.
As described above, currently, when a general chip performs an electrical fast transient test, a transient change of a power supply may cause a transient fluctuation of a power supply voltage of an embedded flash memory, and the transient fluctuation may cause a transient abnormality of the embedded flash memory when reading an instruction, so that a processor obtains an erroneous data reading instruction, a program suddenly jumps to an arbitrary position to run, and a program logic is in a mess, thereby generating states such as a dead halt and an abnormality, and at this time, except for a watchdog reset (i.e., a timeout restart), the program cannot automatically recover to a normal working state, so that the electrical fast transient test fails.
In order to improve the accuracy of reading instructions and the reliability of operation of an embedded flash in a severe environment, for example, in an electric fast transient test, in order to enable the electric fast transient test to be successfully passed, a program can always normally work, cannot be reset and cannot be halted when a power supply has transient interference, the embodiment of the application provides a scheme for reading embedded flash data.
After introducing the design concept of the embodiment of the present application, some brief descriptions are made below on the structure of the device for reading embedded flash data in the embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an apparatus for reading embedded flash data according to an embodiment of the present disclosure, in the schematic structural diagram, the apparatus for reading embedded flash data mainly includes a processor 101 and an embedded flash memory 102, the processor 101 and the embedded flash memory 102 complete communication with each other through a communication bus, and the processor 101 may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement an embodiment of the present disclosure. A software program is installed in the processor 101, and different software programs can be regarded as one processing module having different functions. In the embodiment of the present application, the processor is configured to execute a program for instructions read from the embedded flash memory, and the embedded flash memory 102 is configured to store data.
In a specific implementation process, before the processor runs a program, the processor needs to read a program instruction, send a command to the device for reading the embedded flash memory data, then the device for reading the embedded flash memory data triggers the embedded flash memory to read the instruction needed by the processor, then the device for reading the embedded flash memory data sends the read instruction to the processor, and the processor runs the program corresponding to the instruction.
The technical scheme provided by the embodiment of the application is described in the following with the accompanying drawings of the specification.
Referring to fig. 2, fig. 2 is a diagram illustrating a method for reading data of an embedded flash memory according to an embodiment of the present disclosure. The flow chart of the method depicted in FIG. 2 is described as follows:
step 201: and sending a reading instruction to the embedded flash memory.
In the embodiment of the present application, the flash memory controller sends a command for reading the storage in the embedded flash memory to the embedded flash memory, where the command may be, for example, data or a program stored in the embedded flash memory.
Step 202: it is determined whether an exception exists with the embedded flash memory.
In the embodiment of the application, after the flash memory controller sends the reading instruction to the embedded flash memory, whether an abnormal condition exists in the embedded flash memory is judged.
In a possible implementation manner, whether the working voltage of the embedded flash memory is within a preset working voltage range is detected according to a preset detection frequency, in order to improve the detection reliability, the preset detection frequency for detecting the working voltage of the embedded flash memory is greater than the working frequency of the embedded flash memory, and if the detected working voltage of the embedded flash memory is not within the preset working voltage range, it is determined that the embedded flash memory is abnormal.
In a specific implementation process, a preset working voltage range is a voltage range in which the embedded flash memory can normally work, the embedded flash memory can read a correct command in the range, when a detection voltage higher than the normal working voltage range of the embedded flash memory or a detection voltage lower than the working voltage range of the embedded flash memory appears in a result detected by a preset detection frequency, the situation that the voltage of the embedded flash memory is in a transient abnormal state when the read command is executed is determined, and when the working voltage of the embedded flash memory in the result detected by the preset detection frequency is in the normal working voltage range, the situation that the voltage of the embedded flash memory is not in the transient abnormal state when the read command is executed is determined. When the embedded flash memory working voltage is detected, if the detection frequency is the same as the working frequency of the embedded flash memory, when the abnormity occurs in the interruption of the clock period for reading the data of the embedded flash memory, the abnormity cannot be captured, so that the transient abnormity cannot be effectively avoided.
In another possible implementation manner, first data sent by the embedded flash memory based on the reading instruction is obtained, second data is obtained from the preset data storage area, if the second data is not the preset data, it is determined that the embedded flash memory is abnormal, and the read first data is discarded.
In a specific implementation process, a clock cycle of the embedded flash memory is increased, the speed of reading an instruction in the embedded flash memory is reduced, a double-clock cycle reading mode is adopted, the former clock cycle is used for reading data in the embedded flash memory, the latter clock cycle is used for reading fixed data of a fixed address, if the data read in the latter cycle is the same as preset data, the working voltage of the embedded flash memory is in an abnormal condition, and if the data read in the latter cycle is different from the preset data, the working voltage of the embedded flash memory is in a transient abnormal condition.
In a possible implementation manner, when the working voltage of the embedded flash memory with the preset duration is within the preset working voltage range and the variation amplitude of the working voltage within the preset duration is greater than the preset value, an abnormal alarm indication is output, and the operation of the processor is suspended according to the abnormal alarm indication, or the embedded flash memory is controlled to stop executing the read instruction according to the abnormal alarm indication.
In the specific implementation process, the working voltage of the embedded flash memory is in the normal working voltage range, at this time, if the working voltage of the embedded flash memory changes in a range exceeding a preset value within a certain time period, i.e. the working voltage of the embedded flash memory increases or decreases suddenly and has a continuous change trend, an abnormal alarm indication is sent to the device for reading the data of the embedded flash memory, the embedded flash memory can control the processor to suspend running programs or control the embedded flash memory to stop executing reading instructions according to the alarm indication, so that when the embedded flash memory is still in the normal working voltage range, the processor running programs or the reading instructions of the embedded flash memory are stopped before transient abnormality of the voltage possibly occurs according to the change trend of the voltage, and the reading of wrong instructions when the working voltage of the embedded flash memory is abnormal is avoided, the condition of crash or overtime restart is caused, so that the running reliability of the equipment for reading the embedded flash memory data in a severe environment is improved.
In another possible embodiment, a threshold range is set according to the normal operating voltage range of the embedded flash memory, and when the detected voltage exceeds the threshold range within a certain period of time and has a trend of continuous change, an abnormal warning indication is sent to the device reading the embedded flash memory data, and when the device receives the abnormal warning indication, the same processing manner as the foregoing embodiment is adopted, and details are not repeated again.
Step 203: and if the embedded flash memory is abnormal, repeatedly sending a reading instruction to the embedded flash memory.
In the embodiment of the present application, as described above, whether the working voltage of the embedded flash memory is within the preset working voltage range is determined according to the result of the voltage anomaly detection, when the working voltage of the embedded flash memory is within the preset working voltage range, it is determined that the embedded flash memory is not abnormal, and when the working voltage of the embedded flash memory is not within the preset working voltage range, it is determined that the embedded flash memory is abnormal; or comparing the read data with the standard data, if the data obtained by comparison is the same, determining that the embedded flash memory is abnormal, and if the data obtained by comparison is different, determining that the embedded flash memory is abnormal.
When the embedded flash memory is determined to be abnormal, the flash memory controller repeatedly sends a reading instruction to the embedded flash memory, and the situation that the processor is halted or needs to be restarted overtime due to the fact that the processor executes the wrong instruction is avoided.
In a possible implementation manner, the read instruction is repeatedly sent to the embedded flash memory, and the read instructions may be sent to the embedded flash memory sequentially for a predetermined number of times according to a predetermined interval duration.
In a specific implementation process, the predetermined number of times may be selected to be sequentially sent every certain time length, for example, the predetermined number of times may be sent every other clock cycle, so that the number of times of instruction reading may be reduced on the premise of ensuring the accuracy of instruction reading.
In another possible implementation manner, after the read instruction is repeatedly sent to the embedded flash memory, whether a sending stopping triggering condition is met is determined, and if the sending stopping triggering condition is met, the sending of the read instruction to the embedded flash memory is stopped.
In a specific implementation process, after the instruction is repeatedly sent to the embedded flash memory, it is required to judge when the transient abnormality is ended, the embedded flash memory can read a correct instruction, and when the correct instruction can be read, the embedded flash memory stops continuously sending the instruction when the abnormality occurs to the embedded flash memory, that is, the trigger condition for stopping sending the instruction when the abnormality occurs is met, so that the end time of the transient abnormality can be grasped in real time, and the instruction reading efficiency is improved.
In a possible implementation manner, whether the trigger condition for stopping sending is met may be determined by determining whether a predetermined number of received data reading results are the same, where one data reading result includes data sent by the embedded flash memory according to a reading address of a received one-time reading instruction, and if the predetermined number of data reading results are all the same, it is determined that the trigger condition for stopping sending is met, and one data reading result is determined as the reading result corresponding to the reading instruction. That is to say, whether the data reading results in the predetermined clock cycle are the same or not may be determined, for example, whether the data reading results in the three consecutive cycles are the same or not may be determined, and if the data read in the three consecutive cycles are the same, it is indicated that the embedded flash memory recovers to the normal operating voltage, the continuous sending of the read instruction may be stopped, and the result of the data reading in one of the cycles may be used as the final data reading result of the instruction, so that the accuracy of the determination may be improved by determining whether the data in the consecutive cycles are the same or not.
In a possible implementation manner, when the preset number of data reading results are different, the reading instruction is continuously sent to the embedded flash memory, and when the accumulated number of sending the reading instruction reaches the preset number, an abnormal interruption indication is output. For example, if the data reading results in three consecutive cycles are different (two of the data may be the same, or all three data may be different), the data reading instruction when the abnormality occurs is continuously sent to the embedded flash memory, if the number of times of continuous sending lasts for tens of times, which indicates that the abnormality may last for a long time, an abnormal interrupt instruction is output, the device reading the embedded flash memory data may control the processor to interrupt itself according to the abnormal interrupt instruction, and stop running the program, or may control the embedded flash memory to interrupt reading the embedded flash memory data according to the abnormal interrupt instruction, so that the timely interrupt may save resources, and may avoid reading the error instruction all the time when the abnormality lasts for a long time.
In the embodiment of the application, when transient abnormality occurs in the embedded flash memory, the device for reading data of the embedded flash memory can dynamically control the instruction sent to the embedded flash memory, when a new instruction for sending an abnormal signal is not collected, the instruction sent when the abnormality occurs is resent when the abnormal signal is collected, or the instruction is stopped being sent when the abnormality lasts for a long time, and the program operation is interrupted.
Based on the same inventive concept, the embodiment of the application provides a device for reading embedded flash memory data, and the device for reading embedded flash memory data can realize the corresponding function of the method for reading embedded flash memory data. The device for reading the embedded flash memory data can be realized by a chip system, and the chip system can be formed by a chip and can also comprise the chip and other discrete devices. Referring to fig. 3a, the apparatus for reading embedded flash data includes a sending module 301 and a determining module 302. Wherein:
a sending module 301, configured to send a read instruction to the embedded flash memory;
a determining module 302, configured to determine whether an embedded flash memory is abnormal;
the sending module 301 is further configured to repeatedly send a reading instruction to the embedded flash memory if the embedded flash memory is abnormal.
In one possible implementation, the determining module 302 is configured to:
detecting whether the working voltage of the embedded flash memory is within a preset working voltage range or not according to a preset detection frequency, wherein the preset detection frequency is greater than the working frequency of the embedded flash memory;
and if the working voltage is not within the preset working voltage range, determining that the embedded flash memory is abnormal.
In one possible implementation, the determining module 302 is configured to:
obtaining first data sent by the embedded flash memory based on the reading instruction;
obtaining second data from a preset data storage area;
and if the second data is not preset data, determining that the embedded flash memory has abnormity, and discarding the first data.
In a possible implementation manner, please refer to fig. 3b, the apparatus for reading embedded flash data in the embodiment of the present application further includes a second determining module 303, configured to:
after the sending module 301 repeatedly sends the reading instruction, it is determined whether a stop sending trigger condition is satisfied;
and if the sending stopping triggering condition is met, stopping sending the reading instruction to the embedded flash memory.
In a possible implementation, the second determining module 303 is configured to:
determining whether the received data reading results of the preset quantity are the same or not, wherein one data reading result comprises data sent by the embedded flash memory according to the reading address of the received one-time reading instruction;
and if the preset number of data reading results are the same, determining that the sending stopping triggering condition is met, and determining one data reading result as a reading result corresponding to the reading instruction.
In a possible implementation, the second determining module 303 is further configured to:
if the data reading results of the preset number are different, the reading instruction is continuously sent to the embedded flash memory, and when the cumulative number of times of sending the reading instruction reaches the preset number, an abnormal interruption indication is output.
In a possible implementation manner, please refer to fig. 3b, the apparatus for reading embedded flash data in the embodiment of the present application further includes an alarm module 304, configured to:
outputting an abnormal alarm indication when the working voltage of the embedded flash memory within a preset working voltage range within a preset time length and the variation amplitude of the working voltage within the preset time length is larger than a preset value;
suspending the operation of the processor according to the abnormal alarm indication; alternatively, the first and second electrodes may be,
and controlling the embedded flash memory to stop executing the reading instruction according to the abnormal alarm indication.
All relevant contents of the steps involved in the foregoing embodiments of the method for reading embedded flash data may be cited in the description of the functions of the functional modules corresponding to the device for reading embedded flash data in the embodiments of the present application, which are not described herein again.
The division of the modules in the embodiments of the present application is schematic, and only one logical function division is provided, and in actual implementation, there may be another division manner, and in addition, each functional module in each embodiment of the present application may be integrated in one processor, may also exist alone physically, or may also be integrated in one module by two or more modules. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
Based on the same inventive concept, the embodiment of the application provides a device for reading embedded flash memory data. Referring to fig. 4, the apparatus for reading embedded flash data includes at least one processor 401 and a memory 402 connected to the at least one processor, in this embodiment, a specific connection medium between the processor 401 and the memory 402 is not limited, in fig. 4, the processor 401 and the memory 402 are connected through a bus 400 as an example, the bus 400 is represented by a thick line in fig. 4, and a connection manner between other components is only schematically illustrated and is not limited. The bus 400 may be divided into an address bus, a data bus, a control bus, etc., and is shown with only one thick line in fig. 4 for ease of illustration, but does not represent only one bus or type of bus.
In the embodiment of the present application, the memory 402 stores instructions executable by the at least one processor 401, and the at least one processor 401 may execute the steps included in the foregoing method for reading embedded flash data by executing the instructions stored in the memory 402.
The processor 401 is a control center of the device for reading the embedded flash data, and may connect various portions of the entire device for reading the embedded flash data by using various interfaces and lines, and perform or execute the instructions stored in the memory 402 and call the data stored in the memory 402, thereby performing overall monitoring on the device for reading the embedded flash data. Optionally, the processor 401 may include one or more processing units, and the processor 401 may integrate an application processor and a modem processor, wherein the application processor mainly handles operating systems, application programs, and the like, and the modem processor mainly handles wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 401. In some embodiments, processor 401 and memory 402 may be implemented on the same chip, or in some embodiments, they may be implemented separately on separate chips.
The processor 401 may be a general-purpose processor, such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like, that may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method for detecting the amount of laundry disclosed in the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.
By programming the processor 401, the code corresponding to the method for reading embedded flash data described in the foregoing embodiment may be solidified in the chip, so that the chip can execute the steps of the method for reading embedded flash data when running.
Based on the same inventive concept, embodiments of the present application further provide a storage medium storing computer instructions, which, when executed on a computer, cause the computer to perform the steps of the method for reading embedded flash data as described above.
In some possible embodiments, the aspects of the method for reading embedded flash data provided by the present application may also be implemented in the form of a program product, which includes program code for causing a detection device to perform the steps in the method for reading embedded flash data according to various exemplary embodiments of the present application described above in this specification, when the program product is run on a device for reading embedded flash data.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method of reading embedded flash data, the method comprising:
sending a reading instruction to the embedded flash memory;
determining whether the embedded flash memory has an abnormality;
and if the embedded flash memory is abnormal, repeatedly sending the reading instruction to the embedded flash memory.
2. The method of claim 1, wherein determining whether the embedded flash memory is anomalous comprises:
detecting whether the working voltage of the embedded flash memory is within a preset working voltage range or not according to a preset detection frequency, wherein the preset detection frequency is greater than the working frequency of the embedded flash memory;
and if the working voltage is not within the preset working voltage range, determining that the embedded flash memory is abnormal.
3. The method of claim 1, wherein determining whether the embedded flash memory is anomalous comprises:
obtaining first data sent by the embedded flash memory based on the reading instruction;
obtaining second data from a preset data storage area;
and if the second data is not preset data, determining that the embedded flash memory has abnormity, and discarding the first data.
4. The method of claim 1, after repeatedly sending the read instruction to the embedded flash memory, comprising:
determining whether a stop transmission triggering condition is satisfied;
and if the sending stopping triggering condition is met, stopping sending the reading instruction to the embedded flash memory.
5. The method of claim 4, wherein determining whether a stop sending trigger condition is satisfied comprises:
determining whether the received data reading results of the preset quantity are the same or not, wherein one data reading result comprises data sent by the embedded flash memory according to the reading address of the received reading instruction for one time;
and if the preset number of data reading results are the same, determining that the sending stopping triggering condition is met, and determining one data reading result as the reading result corresponding to the reading instruction.
6. The method of claim 5, wherein determining whether the predetermined number of data reads received are the same further comprises:
if the data reading results of the preset number are different, the reading instruction is continuously sent to the embedded flash memory, and when the cumulative number of times of sending the reading instruction reaches the preset number, an abnormal interruption instruction is output.
7. The method of any of claims 1-3, wherein the method further comprises:
outputting an abnormal alarm indication when the working voltage of the embedded flash memory in a preset time length is within a preset working voltage range and the variation amplitude of the working voltage in the preset time length is larger than a preset value;
suspending operation of the processor according to the abnormal alarm indication; alternatively, the first and second electrodes may be,
and controlling the embedded flash memory to stop executing the reading instruction according to the abnormal alarm indication.
8. An apparatus for reading embedded flash data, the apparatus comprising:
the sending module is used for sending a reading instruction to the embedded flash memory;
the determining module is used for determining whether the embedded flash memory has abnormity;
the sending module is further configured to repeatedly send the reading instruction to the embedded flash memory if the embedded flash memory is abnormal.
9. An apparatus for reading embedded flash data, the apparatus comprising:
a memory for storing program instructions;
a processor for calling program instructions stored in said memory and for executing the steps comprised in the method of any one of claims 1 to 7 in accordance with the obtained program instructions.
10. A storage medium storing computer-executable instructions for causing a computer to perform the steps comprising the method of any one of claims 1-7.
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Cited By (1)
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