CN116431377B - Watchdog circuit - Google Patents
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- CN116431377B CN116431377B CN202310693277.6A CN202310693277A CN116431377B CN 116431377 B CN116431377 B CN 116431377B CN 202310693277 A CN202310693277 A CN 202310693277A CN 116431377 B CN116431377 B CN 116431377B
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- 230000002159 abnormal effect Effects 0.000 claims abstract description 17
- 241000282472 Canis lupus familiaris Species 0.000 claims description 217
- 238000012840 feeding operation Methods 0.000 claims description 94
- 238000001514 detection method Methods 0.000 abstract description 3
- 230000001960 triggered effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to a watchdog circuit in the technical field of power electronics, which comprises: the device comprises a frequency division module, an up counter, a watchdog reset threshold register, a watchdog state register, a watchdog control register and a watchdog operation register, wherein the watchdog verification program is used for judging whether the conventional total time timeout of feeding is used for judging, and a feeding dog type flag bit, an ID of feeding and a standard interval time are added. The watchdog circuit detects that the program is abnormal in execution under more conditions, because the interval time of each watchdog and the sequential logic of the watchdog are required to be detected when the watchdog is operated, when the program is not run to the condition that the program cannot be run out, but is run to the wrong place to execute the program, the program is also greatly detected by the sequential detection of the reset of the watchdog, thereby triggering the reset of the system, ensuring the logic correctness of the system more comprehensively and avoiding the harm caused by the wrong program logic.
Description
Technical Field
The application relates to the technical field of power electronics, in particular to a watchdog circuit.
Background
In the operation of the single chip microcomputer, severe environment interference such as electromagnetic field and the like can be encountered to be out of control, so that unexpected faults such as program entering dead circulation, program running and flying (dead halt) and the like are caused, the normal operation of the program is interrupted, the system can not continue to operate, and the system falls into a stagnation state, and unexpected results occur. At this time, the system can be forced to reset by pressing a reset button. But more ideal implementation is to monitor the running state of the MCU in real time through a set of monitoring system, and make the system get rid of the fault state when the running is abnormal. Watchdog (watch) technology can solve this problem.
The watchdog Timer (WDT) is a component of the MCU and is a counter, the basic principle is that a numerical value (overflow value) is set for the counter first, after the program starts running, the watchdog Timer starts counting, when the program normally runs, a command is periodically sent to set the counter to zero (feed Dog) to restart counting, and if the counter is not cleared for a long time, the counter is increased to a set value (Timer overflow), the counter considers that the program is abnormal, and the system is forced to reset.
The watchdog module in the MCU does not trigger the system reset as long as the instruction is provided for setting the counter to zero (feeding the dog), so that if the program is disturbed to jump from one place to a program segment containing the feeding instruction by mistake, the program will not detect the error and trigger the watchdog reset, but the program logic is wrong, and the continuous running in a medical system can have serious consequences under certain conditions.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a watchdog circuit.
A watchdog circuit, the watchdog circuit comprising:
the frequency dividing module is used for dividing the frequency of the system clock signal according to a preset frequency dividing value and outputting the clock signal after frequency division to the up counter.
An up counter for counting the divided clock signal.
And the watchdog reset threshold register is used for storing a reset count threshold of the watchdog.
A watchdog status register for recording whether each round of different dog feeding IDs feed dogs in the round; the dog feeding ID is set according to a preset ID setting rule.
And the watchdog control register is used for storing the setting value of the control watchdog module.
And the dog feeding operation register is used for storing the dog feeding type flag bit, the dog feeding ID and the dog feeding operation time interval of the current dog feeding operation.
Writing a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval into the dog feeding operation register by a dog feeding program during dog feeding operation, setting the value of a corresponding ID state bit of the watchdog state register according to the value of the dog feeding operation register, and updating the watchdog control register; judging whether program execution is abnormal or not according to the values of the watchdog state register and the watchdog control register, the reset counting threshold and the count value of the up counter, and triggering a watchdog system reset signal if the program execution is abnormal.
In one embodiment, the frequency division module includes a prescaler counter and a prescaler register;
the prescaler register is used for storing a preset frequency division value.
The prescaler is used for counting down the system clock signal, introducing the value of the prescaler into the prescaler when the count reaches zero, and simultaneously reversing the level of the clock signal output to the up counter.
In one embodiment, the watchdog status register is a 32-bit register, configured to store whether each watchdog ID has performed a watchdog feeding operation in the present watchdog feeding period, where a bit with a value of 0 indicates that the watchdog feeding ID corresponding to the bit has not performed a watchdog feeding operation, and a bit with a value of 1 indicates that the watchdog feeding ID corresponding to the bit has performed at least one watchdog feeding operation.
In one embodiment, the watchdog control register is a 32-bit register, 0 to 4 bits of the register store the most recent predetermined order of the watchdog IDs, 5 to 9 bits of the register store the most recent arbitrary order of the watchdog IDs, 10 to 14 bits of the register store the maximum watchdog ID, and 15 to 31 bits of the register remain.
In one embodiment, the feeding program writes a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval into the dog feeding operation register during a dog feeding operation, sets a value of a corresponding ID status bit of the watchdog status register according to a value of the dog feeding operation register, and updates the watchdog control register, including:
and writing the dog feeding type flag bit, the dog feeding ID and the dog feeding operation time interval into the dog feeding operation register by the dog feeding program section during the dog feeding operation.
And if the bit corresponding to the dog feeding ID in the watchdog status register and the dog feeding operation register is 0, the corresponding position of the watchdog status register is 1, otherwise, the value of the bit is unchanged.
If the dog feeding type flag bit in the dog feeding operation register is any sequence dog feeding operation, storing a dog feeding ID in the dog feeding operation register in 5 to 9 bits of the watchdog control register; and if the dog feeding type flag bit in the dog feeding operation register is a preset sequence dog feeding operation, storing the dog feeding ID in the dog feeding operation register in 0 to 4 bits of the watchdog control register.
And if the feeding ID in the feeding dog operation register is larger than the maximum feeding dog ID number stored in the feeding dog control register, setting the maximum feeding dog ID number stored in the feeding dog control register as the feeding dog ID in the feeding dog operation register.
In one embodiment, determining whether program execution is abnormal according to the values of the watchdog status register and the watchdog control register, the reset count threshold and the count value of the up counter, and triggering a watchdog system reset signal if abnormal, including:
and if the state bit corresponding to the feeding dog ID in the feeding dog operation register in the watchdog state register is 1 and the bit of the ID number smaller than the feeding dog ID in the feeding dog operation register is unset, triggering a watchdog system reset signal.
And triggering a watchdog system reset signal if the dog feeding ID in the dog feeding operation register is a predetermined sequence of dog feeding operation, and when the predetermined sequence of dog feeding ID stored in the watchdog control register is not a dog feeding ID smaller than the dog feeding ID in the dog feeding operation register by 1.
And if the dog feeding ID in the dog feeding operation register is the first dog feeding operation, triggering a watchdog system reset signal when the error between the accumulated time of the up counter and the dog feeding operation time interval stored in the dog feeding operation register is larger than a preset value.
In one embodiment, the preset ID setting rule is: the dog feeding IDs are increased one by one from 0 to the set maximum ID, are arranged from small to large according to the interval time of feeding dogs, and are arranged according to the sequence when the program is executed when the interval time is the same.
The above-mentioned watchdog circuit, the watchdog circuit includes: the device comprises a frequency division module, an up counter, a watchdog reset threshold register, a watchdog state register, a watchdog control register and a watchdog operation register, wherein the watchdog verification program is used for judging whether the conventional total time timeout of feeding is used for judging, and a feeding dog type flag bit, an ID of feeding and a standard interval time are added. The watchdog circuit detects more types of program execution anomalies, because the interval time of each watchdog and sequential logic of the watchdog are required to be detected when the watchdog is operated, when the program is not flown to the place where the program is wrong, the program is executed only when the program is flown to the place where the program is wrong, the system reset is triggered by detecting the anomalies through the sequential detection of the watchdog reset, the logic correctness of the system is more comprehensively ensured, and the harm caused by the wrong program logic is avoided.
Drawings
FIG. 1 is a block diagram of a watchdog circuit architecture in one embodiment;
FIG. 2 is a watchdog status register in another embodiment;
FIG. 3 is a watchdog control register in another embodiment;
FIG. 4 is a diagram of a dog-feeding operation register in another embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In one embodiment, as shown in fig. 1, a watchdog circuit is provided, the watchdog circuit comprising: frequency division module 10, up counter 20, watchdog reset threshold register 30, watchdog status register 40, watchdog control register 50, and watchdog operation register 60.
The frequency dividing module 10 is configured to divide the system clock signal according to a preset frequency dividing value, and output the divided clock signal to the up counter.
Specifically, the frequency dividing module 10 divides the system clock signal to a required frequency, the maximum value of the reset threshold register is fixed according to the required reset interval time, when the longer reset interval time is required, the frequency dividing register is set to reduce the watchdog count clock frequency, and then the same reset threshold corresponds to the longer reset interval time.
An up counter 20 for counting the divided clock signal.
A watchdog reset threshold register 30 for storing a watchdog reset count threshold.
A watchdog status register 40 for recording whether each round of different dog feeding IDs fed dogs in the round; the dog feeding ID is set according to a preset ID setting rule.
A watchdog control register 50 for storing a setting value for controlling the watchdog module. Specifically, the watchdog control register stores some function settings of the watchdog circuit, including the largest feeding ID number, the latest arbitrary order ID, and the latest predetermined order ID number.
And the dog feeding operation register is used for storing the dog feeding type flag bit, the dog feeding ID and the dog feeding operation time interval of the current dog feeding operation. Specifically, feeding dogs is classified into two categories: one is a dog feeding operation in any order; the other is a predetermined order of feeding operations, and the current feeding ID must be less than 1 or after any order of feeding ID number of the predetermined order.
The predetermined sequence of feeding dog operation means that the ID number of the current feeding dog operation must be behind the feeding dog ID with ID number less than one, otherwise logic error is considered, the system reset is triggered, for example, the feeding dog operation with ID 3 is executed now, if it is in any sequence, the dog identification before it is not judged, if it is the feeding dog operation in the predetermined sequence, whether the feeding dog operation with ID 2 is actually behind the feeding dog operation with ID 2 is judged, if not, illegal is judged, and a system reset request is immediately sent.
Dividing the frequency of the clock signal by using the frequency dividing value set by the frequency dividing module; starting an up counter to count the frequency-divided clock signal; during feeding dog operation, the feeding dog program writes the feeding dog type flag bit, the feeding dog ID and the feeding dog operation time interval into a feeding dog operation register, sets the value of the corresponding ID state bit of the watchdog state register according to the value of the feeding dog operation register, updates the watchdog control register, automatically judges whether program execution is abnormal according to the value of the watchdog state register, the value of the watchdog control register, a reset count threshold and the count value of an up counter, triggers a watchdog system reset signal if the program execution is abnormal, and updates the value of the corresponding ID state bit of the watchdog state register and the value of the watchdog control register according to the value written into the feeding dog operation register if the program execution is not abnormal.
Specifically, the watchdog verification program adds a dog feeding type flag bit, a dog feeding ID and a standard interval time (writing into a dog feeding operation register) besides the conventional total time timeout judgment of the dog feeding.
When the dog feeding operation is needed to provide dog feeding ID and interval time, writing the dog feeding operation register (dog feeding operation), if the corresponding ID state bit of the watchdog state register is 0 at the moment, the corresponding state position 1 is set for the first dog feeding operation of the ID in the cycle of the watchdog, and in addition, every dog feeding operation, the latest arbitrary sequence dog feeding ID number and the preset sequence dog feeding ID number are recorded in the watchdog control register. The reset of the watchdog will be triggered when feeding the dog if the following happens: the corresponding status bit is 1 when feeding the dog, and the bit corresponding to the feeding dog ID smaller than the current feeding dog ID is unset, or the feeding dog operation with the ID in the order of attention is performed currently, but the feeding dog ID in the previous order of attention operation is not an ID smaller than the current ID by 1, or the accumulated time of the watchdog timer and the interval time error set by the feeding dog when the feeding dog operation of the ID is operated for the first time are larger than the set range, and the three conditions indicate that the program execution is abnormal and the reset of the watchdog is triggered.
In the above-mentioned watchdog circuit, the watchdog circuit includes: the device comprises a frequency division module, an up counter, a watchdog reset threshold register, a watchdog state register, a watchdog control register and a watchdog operation register, wherein the watchdog verification program is used for judging whether the conventional total time timeout of feeding is used for judging, and a feeding dog type flag bit, an ID of feeding and a standard interval time are added. The watchdog circuit detects that the program is abnormal in execution under more conditions, because the interval time of each watchdog and the sequential logic of the watchdog are required to be detected when the watchdog is operated, when the program is not run to the condition that the program cannot be run out, but is run to the wrong place to execute the program, the program is also greatly detected by the sequential detection of the reset of the watchdog, thereby triggering the reset of the system, ensuring the logic correctness of the system more comprehensively and avoiding the harm caused by the wrong program logic.
In one embodiment, the frequency division module includes a prescaler counter and a prescaler register; the pre-frequency dividing register is used for storing a preset frequency dividing value; and the prescaler is used for carrying out one-step down counting on the system clock signal, leading the value of the prescaler into the prescaler when the count reaches zero, and simultaneously reversing the level of the clock signal output to the up counter.
In one embodiment, as shown in fig. 2, the watchdog status register is a 32-bit register, which is used to store whether each watchdog feeding ID has performed a watchdog feeding operation in the present watchdog feeding period, a bit with a value of 0 indicates that the watchdog feeding ID corresponding to the bit has not performed a watchdog feeding operation, and a bit with a value of 1 indicates that the watchdog feeding ID corresponding to the bit has performed at least one watchdog feeding operation.
In one embodiment, as shown in FIG. 3, the watchdog control register is a 32-bit register, with 0 to 4 bits of the register storing the most recent predetermined order of the dog feed IDs, 5 to 9 bits of the register storing the most recent arbitrary order of the dog feed IDs, 10 to 14 bits of the register storing the maximum dog feed ID, and 15 to 31 bits of the register reserved.
In one embodiment, the feeding program section writes the feeding dog type flag bit, the feeding dog ID and the time interval into the feeding dog operation register during the feeding dog operation, sets the value of the corresponding ID status bit of the watchdog status register according to the value of the feeding dog operation register, and updates the value of the watchdog control register, including: writing a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval into a dog feeding operation register by a dog feeding program section during dog feeding operation; if the bit corresponding to the dog feeding ID in the watchdog status register and the dog feeding operation register is 0, the corresponding position of the watchdog status register is 1, otherwise, the value of the bit is unchanged; if the dog feeding type flag bit in the dog feeding operation register is fed dog operation in any sequence, storing the ID of the dog feeding operation register in 5 to 9 bits of a watchdog control register; if the dog feeding type flag bit in the dog feeding operation register is a preset sequence dog feeding operation, storing the ID of the dog feeding operation register in 0 to 4 bits of a watchdog control register; if the dog feeding ID in the dog feeding operation register is larger than the maximum dog feeding ID number stored in the dog feeding control register, updating the maximum dog feeding ID number stored in the dog feeding control register into the dog feeding ID in the dog feeding operation register.
The structure of the dog-feeding operation register is shown in fig. 4.
In one embodiment, determining whether program execution is abnormal based on the value of the watchdog status register, the value of the watchdog control register, the reset count threshold and the count value of the up counter, and triggering a watchdog system reset signal if so, includes: if the state bit corresponding to the feeding dog ID in the feeding dog operation register in the watchdog state register is 1 and the bit of the ID number smaller than the feeding dog ID in the feeding dog operation register is unset, triggering a watchdog system reset signal; triggering a watchdog system reset signal if the watchdog ID in the watchdog operation register is a predetermined order of watchdog operation, the predetermined order of watchdog ID stored in the watchdog control register not being a watchdog ID 1 less than the watchdog ID in the watchdog operation register; if the dog feeding ID in the dog feeding operation register is the first dog feeding operation, when the error between the accumulated time of the up counter and the time interval of the dog feeding operation stored in the dog feeding operation register is larger than a preset value, triggering a watchdog system reset signal.
Specifically, when the feeding dog is operated, the order and logic of the feeding dog ID need to be verified are judged, and two logics need to be satisfied: first, if a dog feeding ID is not the first time, then a sequential dog feeding with an ID smaller than that of the dog feeding ID is required to have at least one dog feeding operation, and second, if a dog feeding operation with an ID in a preset sequence is performed currently, then the previous dog feeding ID must be an ID in the preset sequence smaller than the current ID by 1 or an ID dog feeding operation in any sequence.
The feeding operation needs to check that the time interval of the first feeding of the feeding ID meets the set requirement.
These two logic checks will more reliably ensure that the program is running without running.
In one embodiment, the preset ID setting rule is: the dog feeding IDs are increased one by one from 0 to the set maximum ID, are arranged from small to large according to the interval time of feeding dogs, and are arranged according to the sequence when the program is executed when the interval time is the same.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (7)
1. A watchdog circuit, the watchdog circuit comprising:
the frequency dividing module is used for dividing the frequency of the system clock signal according to a preset frequency dividing value and outputting the clock signal after frequency division to the up counter;
an up counter for counting the divided clock signal;
a watchdog reset threshold register for storing a reset count threshold of the watchdog;
a watchdog status register for recording whether each round of different dog feeding IDs feed dogs in the round; the dog feeding ID is set according to a preset ID setting rule;
the watchdog control register is used for storing and controlling the setting value of the watchdog module;
the dog feeding operation register is used for storing a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval of the current dog feeding operation;
when the dog feeding operation is performed, the dog feeding program writes a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval into the dog feeding operation register, sets the value of a corresponding ID state bit of the watchdog state register according to the value of the dog feeding operation register, and updates the watchdog control register; judging whether program execution is abnormal or not according to the values of the watchdog state register and the watchdog control register, the reset counting threshold and the count value of the up counter, and triggering a watchdog system reset signal if the program execution is abnormal.
2. The watchdog circuit of claim 1, wherein the frequency division module comprises a prescaler counter and a prescaler register;
the prescaler register is used for storing a preset frequency division value;
the prescaler is used for counting down the system clock signal, introducing the value of the prescaler into the prescaler when the count reaches zero, and simultaneously reversing the level of the clock signal output to the up counter.
3. The watchdog circuit of claim 1, wherein the watchdog status register is a 32-bit register for storing whether each of the watchdog IDs has been fed with a watchdog operation in the present watchdog feeding period, a bit of 0 indicating that the watchdog ID corresponding to the bit has not performed the watchdog operation, and a bit of 1 indicating that the watchdog ID corresponding to the bit has performed the watchdog operation at least once.
4. The watchdog circuit of claim 1, wherein the watchdog control register is a 32-bit register, 0 to 4 bits of the register store the most recent predetermined order of the feeding IDs, 5 to 9 bits of the register store the most recent arbitrary order of the feeding IDs, 10 to 14 bits of the register store the maximum feeding ID, and 15 to 31 bits of the register remain.
5. A watchdog circuit according to claim 3, wherein, in a watchdog feeding operation, a watchdog feeding program writes a watchdog type flag bit, a watchdog feeding ID and a watchdog feeding operation time interval into the watchdog feeding operation register, sets a value of a corresponding ID status bit of the watchdog status register according to a value of the watchdog feeding operation register, and updates the watchdog control register, comprising:
during dog feeding operation, the dog feeding program section writes a dog feeding type flag bit, a dog feeding ID and a dog feeding operation time interval into the dog feeding operation register;
if the bit corresponding to the dog feeding ID in the watchdog status register and the dog feeding operation register is 0, the corresponding position of the watchdog status register is 1, otherwise, the value of the bit is unchanged;
if the dog feeding type flag bit in the dog feeding operation register is any sequence dog feeding operation, storing a dog feeding ID in the dog feeding operation register in 5 to 9 bits of the watchdog control register; if the dog feeding type flag bit in the dog feeding operation register is a preset sequence dog feeding operation, storing a dog feeding ID in the dog feeding operation register in 0 to 4 bits of the watchdog control register;
and if the feeding ID in the feeding dog operation register is larger than the maximum feeding dog ID number stored in the feeding dog control register, updating the maximum feeding dog ID number stored in the feeding dog control register into the feeding dog ID in the feeding dog operation register.
6. The watchdog circuit of claim 1, wherein determining whether program execution is abnormal based on values of the watchdog status register and the watchdog control register, the reset count threshold and a count value of the up counter, and triggering a watchdog system reset signal if abnormal, comprises:
if the state bit corresponding to the dog feeding ID in the dog feeding operation register in the watchdog state register is 1 and the ID number is smaller than the bit of the dog feeding ID in the dog feeding operation register is unset, triggering a watchdog system reset signal;
triggering a watchdog system reset signal if the watchdog ID in the watchdog operation register is a predetermined order of watchdog operation, and if the predetermined order of watchdog ID stored in the watchdog control register is not a watchdog ID that is 1 less than the watchdog ID in the watchdog operation register;
and if the dog feeding ID in the dog feeding operation register is the first dog feeding operation, triggering a watchdog system reset signal when the error between the accumulated time of the up counter and the dog feeding operation time interval stored in the dog feeding operation register is larger than a preset value.
7. The watchdog circuit of claim 1, wherein the preset ID setting rule is: the dog feeding IDs are increased one by one from 0 to the set maximum ID, are arranged from small to large according to the dog feeding operation time interval, and are arranged according to the sequence when the program is executed when the interval time is the same.
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| CN202310693277.6A CN116431377B (en) | 2023-06-13 | 2023-06-13 | Watchdog circuit |
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|---|---|---|---|---|
| US6230094B1 (en) * | 1998-04-13 | 2001-05-08 | Denso Corporation | Electronic control system and method having monitor program |
| CN102622278A (en) * | 2012-03-07 | 2012-08-01 | 北京经纬恒润科技有限公司 | Watchdog monitoring circuit and monitoring method |
| CN105677497A (en) * | 2015-12-10 | 2016-06-15 | 中国航空工业集团公司西安航空计算技术研究所 | High availability watchdog circuit |
| US20200264933A1 (en) * | 2017-09-30 | 2020-08-20 | Huawei Technologies Co., Ltd. | System Service Timeout Processing Method, and Apparatus |
-
2023
- 2023-06-13 CN CN202310693277.6A patent/CN116431377B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230094B1 (en) * | 1998-04-13 | 2001-05-08 | Denso Corporation | Electronic control system and method having monitor program |
| CN102622278A (en) * | 2012-03-07 | 2012-08-01 | 北京经纬恒润科技有限公司 | Watchdog monitoring circuit and monitoring method |
| CN105677497A (en) * | 2015-12-10 | 2016-06-15 | 中国航空工业集团公司西安航空计算技术研究所 | High availability watchdog circuit |
| US20200264933A1 (en) * | 2017-09-30 | 2020-08-20 | Huawei Technologies Co., Ltd. | System Service Timeout Processing Method, and Apparatus |
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