CN105448333A - Flash memory and processing method thereof - Google Patents
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Abstract
The invention provides a flash memory and a processing method thereof. The flash memory concretely comprises a power supply detection module, an abnormality processing module and a first power supply flag operating module, wherein the power supply detection module is used for detecting the power supply voltage of a flash memory chip to obtain a corresponding detection result, and the detection result comprises abnormality and normality; the abnormality processing module is used for terminating the ongoing operation of the flash memory chip when the detection result is abnormal; and the first power supply flag operating module is used for setting a power supply monitoring flag bit after the abnormality processing module terminates the ongoing operation of the flash memory chip, and the power supply monitoring flag bit is used to represent whether the ongoing operation of the flash memory chip is terminated due to abnormality of the power supply voltage or not in the precious operating process. The reliability of the flash memory is improved in the invention.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a flash memory and a processing method thereof.
Background
Flash memory (flash memory), or flash memory for short, is a form of electrically erasable programmable read-only memory that allows for multiple erases or writes during operation. The flash memory has the advantages of erasable, writable and programmable memory, no loss of power-off data and the like, so the flash memory is widely applied to embedded equipment such as digital cameras, MP3, mobile phones and the like.
Flash memory stores information by varying the number of electrons in the floating gate. Specifically, when electrons are injected into the floating gate of the memory cell, the threshold voltage of the memory cell increases, and the memory cell is in a programmed state. When the electrons trapped in the floating gate are removed, the threshold voltage of the memory cell is lowered, and the memory cell is in an erased state.
Both the program and erase operations of a flash memory require relatively high voltages, wherein the erase operation also requires negative voltages, which can be provided by a charge pump (charge pump) inside the chip according to the requirements. However, when the power supply voltage is too low or too high beyond the operating range of the charge pump, the charge pump cannot deliver the required voltage. In this case, normal execution of the programming and erasing operations of the flash memory cannot be guaranteed, and thus reliability of the flash memory cannot be guaranteed.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a flash memory and a processing method thereof, which can improve the reliability of the flash memory.
In order to solve the above problems, the present invention discloses a flash memory, comprising: the power supply detection module, the exception handling module and the first power supply sign operation module; wherein,
the power supply detection module is used for detecting the power supply voltage of the flash memory chip to obtain a corresponding detection result; wherein the detection result comprises an abnormal state and a normal state;
the exception handling module is used for terminating the ongoing operation of the flash memory chip when the detection result is abnormal; and
the first power supply mark operation module is used for setting a power supply monitoring mark position after the abnormality processing module terminates the ongoing operation of the flash memory chip; wherein the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation.
Preferably, the flash memory further includes:
the second power supply mark operation module is used for resetting the power supply monitoring mark bit before the write operation is executed for the flash memory chip; the power monitoring flag is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power voltage during the execution of the write operation.
Preferably, the flash memory further includes:
the third power supply mark operation module is used for resetting the power supply monitoring mark bit when the flash memory chip is electrified; the power monitor flag bit is used to indicate whether the flash memory chip has terminated an ongoing operation due to an abnormal power supply voltage during the execution of all write operations after power-up.
Preferably, the flash memory further includes:
and the query module is used for responding to a query request of a user for the power supply monitoring zone bit and returning a corresponding query result.
On the other hand, the invention also discloses a processing method of the flash memory, which comprises the following steps:
detecting the power supply voltage of the flash memory chip to obtain a corresponding detection result; wherein the detection result comprises an abnormal state and a normal state;
when the detection result is abnormal, stopping the ongoing operation of the flash memory chip;
after terminating the ongoing operation of the flash memory chip, setting a power monitoring flag bit; wherein the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation.
Preferably, the method further comprises: resetting the power monitoring flag bit before performing the write operation for the flash memory chip; the power monitoring flag is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power voltage during the execution of the write operation.
Preferably, the method further comprises: resetting the power monitoring flag bit when the flash memory chip is powered on; the power monitor flag bit is used to indicate whether the flash memory chip has terminated an ongoing operation due to an abnormal power supply voltage during the execution of all write operations after power-up.
Preferably, the method further comprises: and responding to a query request of a user for the power supply monitoring zone bit, and returning a corresponding query result.
Compared with the prior art, the embodiment of the invention has the following advantages:
in the embodiment of the invention, the power supply voltage of the flash memory chip is detected in the process of programming or erasing operation of the flash memory, and when the power supply voltage is abnormal due to over-low or over-high voltage, the ongoing programming or erasing operation is automatically terminated, so that the reliability of the flash memory can be improved.
In addition, the embodiment of the invention can also set the power supply monitoring flag bit after terminating the ongoing operation of the flash memory chip; wherein, the power monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation because of the abnormal power supply voltage in the previous operation process; therefore, a user can judge whether the flash memory chip has the over-operation termination condition in the write operation process by inquiring the power supply monitoring flag bit, for example, when the power supply monitoring flag bit is set, the over-operation termination condition of the flash memory chip in the write operation process can be judged, and the reliability of the write operation can be ensured by re-triggering the write operation.
Drawings
FIG. 1 is a diagram of a first embodiment of a flash memory according to the present invention;
FIG. 2 is a diagram of a second embodiment of a flash memory according to the present invention;
FIG. 3 is a block diagram of a third embodiment of a flash memory according to the present invention;
FIG. 4 is a diagram of a fourth embodiment of a flash memory according to the present invention;
FIG. 5 is a flow chart of a first embodiment of a processing method of a flash memory according to the present invention;
FIG. 6 is a flow chart of a second embodiment of a processing method of a flash memory according to the present invention;
FIG. 7 is a flow chart of a third embodiment of a processing method of a flash memory according to the present invention;
FIG. 8 is a flow chart of an example of a processing method of a flash memory according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Memory embodiment one
Referring to fig. 1, a block diagram of a first embodiment of a flash memory according to the present invention is shown, which may specifically include: a power detection module 101, an exception handling module 102 and a first power flag operation module 103; wherein,
the power supply detection module 101 can be used for detecting the power supply voltage of the flash memory chip to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
the exception handling module 102 is configured to terminate an ongoing operation of the flash memory chip when the detection result is an exception; and
the first power flag operating module 103 is configured to set a power monitoring flag after the exception handling module terminates the ongoing operation of the flash memory chip; wherein the power monitoring flag bit can be used to indicate whether the flash memory chip has terminated the ongoing operation due to the power supply voltage abnormality during the previous operation.
The embodiment of the invention can be applied to embedded devices such as digital cameras, MP3, mobile phones and the like, is used for improving the reliability of the flash memory, and particularly can be used for improving the reliability of the write operation of the flash memory.
Power supply detection module 101
In practical applications, the power detection module 101 may be configured to detect a power voltage of the flash memory chip and send a corresponding detection result to the exception handling module 102. The specific process of detecting the power supply voltage of the flash memory chip by the power supply detection module 101 may be to determine whether the power supply voltage is within a preset voltage range, if so, obtain a normal detection result, otherwise, obtain an abnormal detection result; wherein the voltage ranges mentioned above may be used to indicate voltage ranges that are not too high or not too low, which are related to the design as well as the manufacturing process. The products of different applications are different, and the specific voltage range is not limited by the embodiment of the invention.
First power source identifier operating module 103
In the embodiment of the invention, the power monitoring flag bit can be used for indicating whether the flash memory chip terminates the ongoing operation due to the abnormal power supply voltage in the previous operation process, which can provide an effective basis for a user to evaluate whether data is correctly and reliably written into the flash memory chip.
The power monitoring flag may include a unit, for example, the power monitoring flag of a unit may indicate the current state of the flash memory chip; the flash memory chip can also comprise a plurality of bits, and the power supply monitoring flag bits of the plurality of bits can respectively represent the writing operation conditions at different occasions (such as after power-on and each writing operation), so that effective data can be provided for a user to analyze the size of the flash memory chip while the reliability of data written by the user is ensured.
Taking a unit power supply monitoring flag bit as an example, in practical application, the power supply monitoring flag bit may be stored in a register, so that it may use binary "0" or "1" to store corresponding states, for example, "0" and "1" may respectively represent an un-terminated state and a terminated state, and a user may obtain the corresponding states by querying the obtained "0" or "1" and further determine whether the operation termination of the flash memory chip occurs during the write operation.
And the value of the power supply monitoring flag bit in the register can be changed through operation, wherein the setting operation can be used for setting the power supply monitoring flag bit to a terminated state, and the resetting operation can be used for setting the power supply monitoring flag bit to an unterminated state. For example, after the power supply monitoring flag bit is set, its value in the register is 1, and after the power supply monitoring flag bit is reset, its value in the register is 0.
In summary, in the embodiment of the present invention, in the process of performing the programming or erasing operation of the flash memory, the power supply voltage of the flash memory chip is detected, and when the power supply voltage is abnormal due to being too low or too high, the ongoing programming or erasing operation is automatically terminated, so that the reliability of the flash memory can be improved.
In addition, the embodiment of the invention also sets the power supply monitoring flag bit after the ongoing operation of the flash memory chip is terminated; wherein, the power monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation because of the abnormal power supply voltage in the previous operation process; therefore, a user can judge whether the flash memory chip has the over-operation termination condition in the write operation process by inquiring the power supply monitoring flag bit, for example, when the power supply monitoring flag bit is set, the over-operation termination condition of the flash memory chip in the write operation process can be judged, and the reliability of the write operation can be ensured by re-triggering the write operation.
Memory embodiment two
Referring to fig. 2, a structural diagram of a second embodiment of a flash memory of the present invention is shown, which may specifically include: a second power supply sign operation module 201, a power supply detection module 202, an exception handling module 203, and a first power supply sign operation module 204; wherein,
the second power flag operating module 201 is configured to reset the power monitoring flag bit before performing the write operation on the flash memory chip; the power supply monitoring zone bit is used for indicating whether the flash memory chip stops the ongoing operation because of the abnormal power supply voltage in the execution process of the current writing operation;
the power detection module 202 may be configured to detect a power voltage of the flash memory chip during the write operation, so as to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
the exception handling module 203 is configured to terminate the ongoing operation of the flash memory chip when the detection result is an exception; and
the first power flag operating module 204 is configured to set a power monitoring flag after the exception handling module terminates the ongoing operation of the flash memory chip.
Compared with the first embodiment, in the present embodiment, a second power flag operating module 201 is added, and the second power flag operating module 201 may reset the power monitoring flag bit before each write operation is executed, so that the power monitoring flag bit is used to indicate whether the flash memory chip terminates the ongoing operation due to the abnormal power voltage in the execution process of the current write operation.
Memory embodiment three
Referring to fig. 3, a structural diagram of a third embodiment of a flash memory of the present invention is shown, which may specifically include: a third power flag operating module 301, a power detection module 302, an exception handling module 303, and a first power flag operating module 304; wherein,
the third power flag operating module 301 may be configured to reset the power monitoring flag bit when the flash memory chip is powered on; the power supply monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation due to the abnormal power supply voltage in the execution process of all write operations after power-on;
the power detection module 302 may be configured to detect a power voltage of the flash memory chip in the process of performing all write operations after power-on, so as to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
the exception handling module 303 is configured to terminate an ongoing operation of the flash memory chip when the detection result is an exception; and
the first power flag operating module 304 is configured to set a power monitoring flag after the exception handling module terminates the ongoing operation of the flash memory chip.
Compared with the first embodiment, in the present embodiment, a third power flag operating module 301 is added, and the third power flag operating module 301 may reset the power monitoring flag bit after each power-on execution, so that the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the power voltage abnormality in the execution process of all the write operations after the power-on.
Memory embodiment four
Referring to fig. 4, a block diagram of a fourth embodiment of a flash memory according to the present invention is shown, which may specifically include: a power detection module 401, an exception handling module 402, a first power flag operation module 403 and an inquiry module 404; wherein,
the power detection module 401 may be configured to detect a power voltage of the flash memory chip to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
the exception handling module 402 is configured to terminate the ongoing operation of the flash memory chip when the detection result is an exception;
the first power flag operating module 403 is configured to set a power monitoring flag after the exception handling module terminates the ongoing operation of the flash memory chip; wherein the power monitoring flag bit can be used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation; and
the query module 404 is configured to return a corresponding query result in response to a query request from a user for the power monitoring flag.
Compared with the first embodiment, in the present embodiment, a query module 404 is added, and the query module 404 may return a corresponding query result in response to a query request of a user for the power monitoring flag.
In practical application, a user can trigger a query request by sending a query instruction; and the power monitoring flag may correspond to a pin of the flash memory chip, so that the query module 404 may read a value of the power monitoring flag through the pin address.
Of course, in addition to the way of returning the corresponding query result in response to the query request of the user for the power monitoring flag bit, the embodiment of the present invention may also actively present the value of the power monitoring flag bit to the user, and the active presentation way may save the query operation of the user and provide an effective basis for the user to evaluate whether the data is correctly and reliably written into the flash memory chip.
Method embodiment one
Referring to fig. 5, a flowchart of a first embodiment of a processing method of a flash memory according to the present invention is shown, which may specifically include:
step 501, detecting the power supply voltage of a flash memory chip to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
step 502, when the detection result is abnormal, terminating the ongoing operation of the flash memory chip;
step 503, after terminating the ongoing operation of the flash memory chip, setting a power monitoring flag bit; wherein the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation.
In a preferred embodiment of the present invention, the method may further include: and responding to a query request of a user for the power supply monitoring zone bit, and returning a corresponding query result.
Method embodiment two
Referring to fig. 6, a flowchart of a second embodiment of a processing method of a flash memory according to the present invention is shown, which may specifically include:
step 601, resetting the power supply monitoring zone bit before the write operation is executed for the flash memory chip; the power supply monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation due to the abnormal power supply voltage in the execution process of the current writing operation;
step 602, detecting a power supply voltage of the flash memory chip during the process of executing the write operation to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
step 603, when the detection result is abnormal, terminating the ongoing operation of the flash memory chip;
step 604, after terminating the ongoing operation of the flash memory chip, setting a power monitoring flag bit.
Method embodiment three
Referring to fig. 7, a flowchart of a third embodiment of a processing method of a flash memory according to the present invention is shown, which may specifically include:
step 701, resetting the power monitoring flag bit when the flash memory chip is powered on; the power supply monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation due to the abnormal power supply voltage in the execution process of all write operations after power-on;
step 702, detecting the power supply voltage of the flash memory chip in the process of executing all write operations after power-on to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
step 703, when the detection result is abnormal, terminating the ongoing operation of the flash memory chip;
step 704, after terminating the ongoing operation of the flash memory chip, setting the power monitoring flag bit.
For a person skilled in the art to better understand the embodiment of the present invention, referring to fig. 8, a flowchart of an example of a processing method of a flash memory according to the present invention is shown, which specifically may include:
step 801, receiving a write operation instruction from a user;
step 802, resetting a power monitoring flag bit; the power supply monitoring flag bit is used for indicating whether the flash memory chip terminates the ongoing operation due to the abnormal power supply voltage in the execution process of the current writing operation;
step 803, executing the write operation;
step 804, detecting the power supply voltage of the flash memory chip in the process of executing the write operation to obtain a corresponding detection result; the detection result specifically includes an abnormal state and a normal state;
step 805, when the detection result is abnormal, terminating the current write operation of the flash memory chip;
step 806, after terminating the ongoing operation of the flash memory chip, setting a power monitoring flag bit;
and 807, when the detection result is normal, continuing to execute the writing operation until the writing operation is finished.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
For the method embodiment, since it is basically similar to the memory embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above detailed description is provided for a flash memory and a processing method of a flash memory provided by the present invention, and the principle and the implementation of the present invention are explained by applying specific examples herein, and the description of the above examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. A flash memory, comprising: the power supply detection module, the exception handling module and the first power supply sign operation module; wherein,
the power supply detection module is used for detecting the power supply voltage of the flash memory chip to obtain a corresponding detection result; wherein the detection result comprises an abnormal state and a normal state;
the exception handling module is used for terminating the ongoing operation of the flash memory chip when the detection result is abnormal; and
the first power supply mark operation module is used for setting a power supply monitoring mark position after the abnormality processing module terminates the ongoing operation of the flash memory chip; wherein the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation.
2. The flash memory of claim 1, further comprising:
the second power supply mark operation module is used for resetting the power supply monitoring mark bit before the write operation is executed for the flash memory chip; the power monitoring flag is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power voltage during the execution of the write operation.
3. The flash memory of claim 1, further comprising:
the third power supply mark operation module is used for resetting the power supply monitoring mark bit when the flash memory chip is electrified; the power monitor flag bit is used to indicate whether the flash memory chip has terminated an ongoing operation due to an abnormal power supply voltage during the execution of all write operations after power-up.
4. The flash memory of claim 1, further comprising:
and the query module is used for responding to a query request of a user for the power supply monitoring zone bit and returning a corresponding query result.
5. A method for processing a flash memory, comprising:
detecting the power supply voltage of the flash memory chip to obtain a corresponding detection result; wherein the detection result comprises an abnormal state and a normal state;
when the detection result is abnormal, stopping the ongoing operation of the flash memory chip;
after terminating the ongoing operation of the flash memory chip, setting a power monitoring flag bit; wherein the power monitoring flag bit is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power supply voltage during the previous operation.
6. The method of claim 5, further comprising: resetting the power monitoring flag bit before performing the write operation for the flash memory chip; the power monitoring flag is used to indicate whether the flash memory chip has terminated the ongoing operation due to the abnormal power voltage during the execution of the write operation.
7. The method of claim 5, further comprising:
resetting the power monitoring flag bit when the flash memory chip is powered on; the power monitor flag bit is used to indicate whether the flash memory chip has terminated an ongoing operation due to an abnormal power supply voltage during the execution of all write operations after power-up.
8. The method of claim 5, further comprising:
and responding to a query request of a user for the power supply monitoring zone bit, and returning a corresponding query result.
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| CN110059005A (en) * | 2019-01-30 | 2019-07-26 | 北京品驰医疗设备有限公司 | The program detecting method and implantable medical device of flash memory |
| CN112947841A (en) * | 2019-11-26 | 2021-06-11 | 珠海零边界集成电路有限公司 | Method, device, equipment and storage medium for reading embedded flash memory data |
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| CN112947841A (en) * | 2019-11-26 | 2021-06-11 | 珠海零边界集成电路有限公司 | Method, device, equipment and storage medium for reading embedded flash memory data |
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