SU1430958A1 - Device for testing digital units - Google Patents

Abstract

The invention relates to a device for automation and computer technology and can be used as an embedded control system for digital blocks during operation. The aim of the invention is to increase the productivity of the control, as well as to expand the field of application to enable the control of digital blocks operating in real time. The device contains a control unit 1, a generator of 2 tests, a switch 9, an encoder, a counter 3, a decoder 7, a node 8 of the control. In the case of the release of the system, which includes a digital unit, the device automatically switches to the control mode of the tested unit. During monitoring, if the digital system needs to be put into operation in the proposed device (usually in the event of an urgent need to put the system into operation, the monitoring mode cannot be interrupted) the monitoring mode is automatically terminated and the system can perform its operational functions. The device uses each time free from system operation time for organization of control. The system is monitored more frequently, which allows timely detection and elimination of malfunctions and increases reliability of operation. Such a control mode does not prevent the system from performing its operational functions, since if necessary, the control is automatically terminated, 1 hp f-ly, 4 ill. with: (With SP 4ib SS

Description

SP

00

&. f

The invention relates to automation and computing and can be used as an embedded system for controlling digital blocks during operation.

The purpose of the invention is to increase the performance of the control, as well as expand the field of application of the device by enabling the control of digital blocks operating in real time.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - control unit; Fig, 3 switch; in fig. 4 - control unit

The device contains a control block 1, a generator of 2 tests, a counter 3, an encoder containing an OR 4 element and a pre-processing block 5, a monitored block 6, an error decoder 7, a control unit 8, a switch 9 an input 10 of a sign of the start of the actual effect of the device, an input 11 of the actual device impact, the output 12 of the test change of the control unit, the output 13 of the control mode of the control unit, the output 14 of the test generator,. switch outputs 15 and 16, decoder output 17, output 18 Defective and output 19 OK,

Control unit 1 contains D-flip-flop 20, synchronous input 21, element AND 22, counter 23 of the response time of the monitored block, element OR 24, element AND 25, counter 26, element ZI-OR 27 and counter 28 of the control cycle time, in the control unit, elements 22, 24, 25, and 27 form an encoder.

Switch 9 contains element., 2I-OR 29 and D-flip-flop 30.

The control node 8 contains a D-flip-flop 31 and an AND 32 element.

The device works as follows

The device can operate in the mode of checking digital blocks both in the process of their production, and in the process of operation according to the same algorithm.

When the device is turned on, all elements are reset (the setting circuits are not shown). At the end of the installation signal, the device is in the control mode, while the switch 9 issues a signal 15, which

g

Q

five

five

It allows for the operation of the node 8 control. Control unit 1 generates a potential signal 12 (which is the test test generator for generating control information) according to which test generator 2 generates control information received through switch 9 into block 6. At the end of the signal 12, control block 1 generates a potential signal 13 during which, at the output of block 6, the output control information is formed, the Output control information through the block 5 of preliminary processing of information, leading the information to a form convenient for control, and ent or 4 is supplied to the count input of the counter 3, for the controlled unit 6, the number of pulses appearing on the output of the OR gate 4 for proper operation unit 6 in the process control, it is known beforehand. Therefore, after the monitoring time expires, the counter 3 is set to a predetermined state, which is decoded by the decoder 7, the monitoring time ends at the end of the signal 13, the falling edge of which at the monitoring node 8 records the state of the decoder 7.

When the condition of the monitored block 6 is faulty or its operation fails, a single signal is present at the output of the decoder 7, which is registered by the control node 8 as a fault. In the absence of a pulse 10, the device automatically repeats the monitoring cycle described by Bbmie. Confirmation by node 8 of the control signal; A malfunction indicates a malfunction in the monitored unit 6, otherwise the device would malfunction.

The device is in monitoring mode continuously, i.e. the control cycles are repeated until the arrival of the pulse 10. According to this pulse, the switch 9 removes the signal 15 and passes the operating information to the control unit 6. The pulse control unit 1 IO terminates the control cycle and generates signals I2 and 13 for the duty cycle from the beginning and similar to the control loop. In node 8 of the control fiz-due to interruption of the control loop), pulse 10 prohibits the possible generation of a fault signal, i.e. is installation.

At the end of the work cycle, i.e. at the end of the signal 13, the switch 9 generates a signal 15 and in the absence of a pulse 10 (no new operating information required for processing by the monitored unit 6) the control unit 1 automatically begins to form control loops. The control unit 6 continues until the next receipt of working information, etc.

Thus, the device fills the time interval between the processing by the monitored block 6 of the working information control cycles.

The control unit 1, the switch 9 and the control unit 8 operate as follows. When the device is turned on, all elements are reset (as mentioned above). All triggers are set on the R input. The clock frequency from the synchronous input 21 of the control unit 1 goes through the AND 22 elements to OR 24 to the input of the ZI-OR 27 element, to another input of which the resolution is fed to the initial setting from the output of the counter 26. The first clock pulse, the frequency of the falling edge along the counting the input switches the counter 26 and at its second output a signal is generated, which is fed to the output 12 and is resolution with the second input of the ZI-OR element 27. In addition, the second inverse output of the counter 26 receives the enable signal to the installation input of the counter 23, It counts the pulses coming from the synchronous input 21. When a certain number is reached, after the time required for the test to be generated by the generator of 2 tests in the monitored block 6, the signal from the output of the counter 23 arrives at the input of the ZI-OR element 27 and switches the counter 26 At the third exit. the counter 26, a Processing signal is generated, which is fed to the output 13 and the input of the ZI-OR element 27. The inverse third output of the counter 26 is enabling by the installation input of the counter 28. The counter input of the counter 28 receives pulses from the synchronous input 21. When a certain time is reached required for processing the test by the monitored unit 6, the signal from the output of the counter 28 is fed to the input of the ZI-OR element 27 and returns the counter 26 to the initial state

five

0

five

Q

0

five

five

0

five

The monitoring cycle is automatically repeated when there is no start-up signal at input 10.

When the device is turned on, the D-flip-flop 30 is set to a state in which a potential signal is generated at its inverse output that permits the control unit 8, which enters output 15 and allows the test to pass from the generator output 2 to test 16 and then to controlled block 6 through the element 2I-OR 29.

Upon completion of the test processing in the controlled block 6, the falling edge of the signal arriving at output 13 via the C input of the D flip-flop is confirmed by the monitoring status of the D flip-flop 30.

In node 8 of the control, the signal from input 17 (the output of the decoder) is fed to the D input of the D flip-flop 31, If there is a resolution (signal at input 15) at the input of the AND 32 element (at the end of the signal 13), it is polled via the C input D -trigger 31. If there is a single signal at that moment, D-trigger 31 is energized at the input, indicating a malfunction or failure of the monitored unit 6. If this fails, then at the end of the next control test D-trigger 31 is reset,

The pulse 10 (duration of two or more periods of the clock frequency of the synchronous input 21), arriving at. the input 10 of the control unit 1, the D input of the D-flip-flop 20, the first and second inputs of the OR 24 and AND 25 elements, the counter 26 is set by the signal from the output of the AND 25 element to the initial state, the Pulse 10 sets the D-flip-flop 30 to the reset input as a result, the signal is removed from the output 15, C and 1 of the D-flip-flop 30 to the input of the element 2I-OR 29, permission is received to pass the working information from the input 1 I to the second input of the element 2I-OR 29 to the 16 input and then to the controlled unit,

in node 8 of the control, the impulse from input 10 prohibits from the reset input D to flip-flop 31 a false alarm signal. A false signal could be formed when pulse 10 is not received at the end of the signal 13 (signal 13 by pulse .10 is set) and at input 17 a signal is not generated from the output of the decoder 7,

In block 1, the control signal set from the output of the element And 25 is present before the first trailing edge of the clock pulse, which, at the C input, coaxes the D-flip-flop 20, is a mouth

setting the counter 26 and the second input element And 22 prohibits the passage of bars.

Thus, the control unit 1 is in the initial state and is ready to form a working cycle. The duty cycle is formed on the falling edge of the pulse 10 in a manner similar to the control cycle. In addition, after the end of the pulse 10, the D-trigger 20 in the control unit 1 is set to the initial state and allows the clock to pass through the AND 22 element for the new monitoring cycle.

1 at the end of the work cycle, i.e. at the end of signal 13, the D-flip-flop is reset and the signal 15 is received from its inverse output. In the absence of the next pulse 10, the control unit 1 automatically and continuously starts to form control loops.

Claims (2)

1. A device for controlling digital blocks, containing a control unit, test generator, encoder, counter, error decoder, the output of the control mode of the control unit connected to the reset input of the counter, the counting input of which is connected to the output of the encoder, the inputs of which are the inputs to the device to the outputs of the monitored digital block, the bit outputs of the counter are connected to the information inputs of the decoder, the change output of the test of the control unit is connected to the synchronization input of the test generator, which is different The fact that, in order to improve the control performance, as well as expand the scope of application by enabling the control of digital blocks operating in real time, the device contains a switch and a control node containing an AND element and a D trigger, and the control mode control output is connected with the first input of the element And and with the gate input of the switch, the first information input of which is the input for connecting to the real action of the device, the logical zero bus of which is connected en the second information input of the switch, the first five 0 ZO five device for connecting to the input of the monitored digital block, the second output of the switch is connected to the second input of the element I, the output of which is connected to the C input of the D-flip-flop, the D input of which is connected to the output of the error decoder, the reset input of the D-flip-flop connected to the input of the beginning sign supplying the real action of the device, with the first control input of the switch, with the input of the logic condition of the control unit, the forward and inverse outputs of the D-flip-flop are the Errors and Device Health outputs, the synchronization input of which is connected to the synchronization input of the control unit; the second information input of the switch is connected to the output of the test generator. , 2. The device according to claim 1, characterized in that the control unit contains a D-flip-flop, an encoder, a counter, a control cycle time counter, a time counter operative of the monitored block, the input of the logical condition of the block connected to the D-input of the D-trigger and with the first information input of the encoder, the second information input of which is connected to the inverse output of the D-flip-flop, the C input of which is connected to the synchronous input of the block, with the third information input of the encoder, with the counting inputs of the time counter of the monitored block and the control cycle time counter, the outputs of the borrowings of the counters response time of the monitored block and the control cycle time are connected to the fourth and fifth encoder information inputs, the first direct discharge counter output is connected to the sixth encoder information input, the second counter output counter connected to the seventh information input of the encoder and to the output of the sign of the block test change, the inverse second bit output of the counter is connected to the reset input of the account 50 55 the control cycle time, the third third bit of the counter code is connected to the eighth information input of the thrasher and the output of the sign of the control mode of the block, the inverse third bit of the counter output is connected to T Infortsi uSpaOo / nifa WITH Hava / io paSomiti Since l thirty P Genera / por / dog / under the reset input of the time counter for controlling the block to be monitored; the first and second outputs of the encoder are connected to the counting and reset inputs of the counter, respectively. (picture 2 29 Nnformacil T6 on offpaffomf / fOHfryjffJtu F1 / g.Z.