SU1401587A1 - Device for checking pulse recurrence sequence - Google Patents

Abstract

The invention can be used in discrete-action automation devices for controlling the sequence of alternating pulsed signals in monitoring and control systems. The device contains n triggers 1, n elements AND 2, n elements OR 3, output element OR 4, n input bus 5, outputs 6, 9, 11 devices, n counters 7, element OR - NO 8, element AND NOT 10. The device has an increased reliability of control due to the formation of a failure pulse at the output when crushing or repetition of input pulses along one of the input buses and the start of control when the first controlled input pulse arrives. 2 Il. 5-1S-n § C / s

Description

The invention relates to a pulse technique, can be used in devices of automatic discrete action to control the sequence of alternating pulse signals in control and management systems and is an improvement of the device according to the author. St. No. 1192130.

The aim of the invention is to increase the reliability of the control by ensuring the formation of a failure pulse at the output when crushing or repetition of the input pulses through one of the input buses and the beginning of the control when the first controlled input pulse arrives.

FIG. 1 shows a functional diagram of the device; in fig. 2 is an example of the construction of a counter.

The device for controlling the sequence of alternating pulses contains n triggers 1, n elements AND 2, n elements OR 3, output element OR 4, n input buses 5, each i- input spike 5 is connected respectively to the (1 + 2) -x inputs and subsequent to the i-ro element OR 3 and S-inputs (i- | -l) -x flip-flops 1, the direct outputs of which are connected to the first inputs of the corresponding And 2 elements, and the inverse outputs to the second inputs ( i- | -2) -x elements AND 2, the third inputs of which are connected to the direct outputs (i-f3) -x of the flip-flops 1, and the outputs of the elements AND 2 are connected to the outputs of the output element 4, the output of which is the first output 6 of the device, the outputs of each element OR 3 are connected to the R inputs (i + l) -x flip-flops 1, n counters 7, the count resolution input of each i-ro counter 7 is connected to at the input of the corresponding element AND 2, the counting input - to (i-1) -and input bus 5, and the output - to the corresponding input of the element OR-NOT 8, the output of which is connected to the second output 9 of the device and the first input of the element AND-NOT 10, the second input of which is connected to the output of the output element OR 4, and the output of the element NAND 10 is the third output 1 1 device, the second S-inputs of the trigger 1 is connected to the bus 12 of the initial installation.

Counters 7 (FIG. 2) can be performed on two 1K triggers, the 1 input and the R input of the first trigger 13 are interconnected and are the count resolution enable of each of the counters and are connected to the output of the corresponding AND element 2 The K inputs of the first 13 and second 14 flip-flops are connected to the inverse outputs of the flip-flops respectively, the C inputs of the flip-flops 13 and 14. are connected to the counting input of counter 7 and (i-1) -th input bus 5. The output of the first the trigger 13 is connected to the 1- and R-inputs of the second trigger 14, the direct output of which is the output of the counter 7 and is connected to the co vetstvuyush.emu input OR- NO element 8.

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The device for controlling the sequence of alternating pulses operates in the following manner.

In the initial state, the high-level pulse signal on the initial installation bus 12 triggers 1 are set to the second S-inputs in the unit state, while the input buses 5 have a low potential, the second 9 and the third 11 outputs of the device have a high potential, and at the first exit 6 - low potential.

The device starts monitoring when a pulse arrives at any i-th input bus 5, but the next pulse, provided they are correctly interleaved, must flow to (i-1) -th input bus 5, for example, 5-2.5-1.5- n etc. When the first pulse arrives at the i-th input bus 5 (suppose 5-2, fig. 1) (1 + 1) -th trigger 1 (1-3) confirms its single state, and the remaining triggers 1 (1-2 , 1-п, 1 - 1) with the exception of (i + 2) -ro trigger 1 (1 -i) are set to the zero state through the OR 3 elements, while a high level potential appears on the first output 6 of the device, and at the third output 11, a low-level potential signaling the start of monitoring the alternation of input pulses. On the falling edge of the input pulse, the trigger 13 (i- | -l) -ro of the counter 7 (in our case 7-3) switches. When the next pulse arrives on the (i-1) -th input bus 5 (5-1), the i-th trigger 1 (1-2) is set to one, and the remaining triggers 1 (1-i, 1-п, 1 - 1), with the exception of (i4-l) -ro trigger 1 (1-3) - to the zero state. On the leading edge of the input pulse, the trigger 13 (i + n-th counter 7 (7-3) is set by the R input to the zero state, and on the falling front the trigger 13 by the i-th counter 7 (7-2) - to one state At the first 6 and second 9 outputs of the device, a high level potential is maintained, and at the third 11 - a low level potential, which are held further as long as the order of arrival of the input pulses is maintained.

If the order of arrival of input pulses is not followed, for example, when a pulse arrives on the (1 + 2) -th input bus 5 (suppose 5-i), after the pulse arrives on the 1st input bus 5 (5-2) - (i + 3) the 1st trigger 1 (1-p) is set to one state, and the remaining triggers 1 (1-2, 1-3, 1-i), except for the (i-1) th trigger 1 (1-1), through the elements OR 3 are set to the zero state, but since (i-1) -th trigger 1 (1 - 1) on the previous pulse on the i-th input bus 5 (5-2) is set to the zero state, in unit the state is only (i- | -3) -th trigger 1 (1-p). Therefore on you

During all the elements of AND 2, a zero level is formed, which zeroes all the counters 7, a low level signal appears on the first output 6 of the device, a high level signal appears on the third output 1 1, which indicates a failure in the pulse interleaving sequence. When restoring the order of arrival of input pulses (in this case, when subsequent pulses arrive in turns, the tires 5-3, 5-2, 5-1, 5-p, etc., or 5-1, 5-p, 5-i 5-3, etc.) a single level is formed at the first output 6 of the device, and a low level is formed at the third output 11, and the information about the failure is removed.

If the sequence of receipt of pulses like splitting or repetition of input pulses is not followed, for example, when a second pulse is received on the (i-1) -th input bus 5 (5-1), after the pulse arrives on the i-th input bus 5 (5 -2) triggers 1 confirm their predecessor, its state, i- and (1- | -1) -th triggers 5 (1-2 and 1-3) are in one state, and the rest are in zero, at the first output of the device 6 is kept high, the trigger 14 of the i-ro counter 7 (7-2) is switched, since, according to the previous step, it has a pulse on the (i-1) -th input bus 5 (5-1 ) switched trigger er 13 i-ro counter 7 (7-2). At the output of the i-ro counter 7 (7-2), a high level signal appears, which changes the signal level at the second output 9 of the device to low, and at the third output 11 to high, forming a failure. Upon further repetition of pulses over the (i-1) -th input bus 5 (5-1), the i-th counter 7 (7-2) does not change its state, and the second signal and the 11th and 11th outputs of the device retain a fault signal. Only when a pulse arrives at the next input bus 5 (5-n) of the device, the i-th counter 7 (7-2) forms a low-level potential at its output, removing the fault signal. If a pulse arrives not on the next input bus 5 (5-p), but on any other, except (i-1) -th bus 5 (5-1), the output of the i-ro counter 7 (7-2) also forms a low level signal, a change in the state of the second output 9 of the device, but at the third output 11 of the device, the signal fails due to the low level potential generated in this case at the first output 6.

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At the first output 6 of the device, a fault signal is generated in case of interruption of alternation, loss of one or several input pulses. At the second output 9 of the device, a signal is generated about the failure in case of splitting or repetition of the input pulses through one of the input buses 5. At the third output 11 of the device, a common failure occurs for these two rays.

A simple comparison of the device outputs shows what kind of interleaving occurred. If necessary, you can monitor the direct outputs of the triggers 1 and the alarm signal on the third output 11 of the device, analyze the state of the first 6, second 9 outputs of the device and the state of the triggers 1, determine which type of fault occurred and on what input bus.

Using this device as compared to the known initial installation bus, n counters, OR-NOT and AND-NOT elements, the second and third outputs of the device clearly fix the control start point, determine the type of failure, and form a failure when crushing or repeating input signals. pulses, which provides a more reliable control of the sequence of alternation of pulses.

Claims (1)

Invention Formula Device for controlling the sequence of alternating pulses by aut. St. No. 1192130, characterized in that, in order to increase the reliability of control by ensuring the formation of a failure pulse at the output when crushing or repeating input pulses and beginning control when the first input pulse arrives, an AND-NOT element, an OR-NOT element are additionally introduced into it n counters, the counting input of each i-ro counter is connected to the output of the corresponding element AND, the counting input to the (i-1) th input bus, and the output to the corresponding input of the OR-NOT element whose output is connected to the second output of the device and first at entry AND-NO element, whose second input is connected to the output of the OR gate output, and an output of AND-NO element is a third output device, wherein the second S-inputs of flip-flops connected to the bus initial installation. FIG. 2