SU907887A1 - Device for testing redundancy generator - Google Patents

Description

A device for monitoring a redundant generator relates to a pulse technique and can be used in monitoring systems for pulse generators. o A generator control device is known that contains an AND element, the output of which is connected to the zero input input of a pulse counter connected to a 1 J pulse generator. The disadvantage of such a device is the lack of control accuracy due to the fact that no malfunction is detected and also malfunctions of the counter and the additional control pulse generator. It is known a device for monitoring a redundant generator, which has a higher reliability of monitoring and provides detection of faults that cause an increase in the frequencies of the operating generator. The device contains a pulse estimator, the summing input of which is connected to the pulse generator, the reset input - with the output of the first element And and one input of the second element. And, and the outputs of the first and penultimate bits of the counter are connected to the set inputs of the trigger, the output of which is connected to another input of the second element AND, the output of the second element AND and the last bit of the counter are connected to the inputs of the output element OR 2j. A disadvantage of the known device for monitoring a redundant generator is the lack of reliability of the monitoring result due to the lack of monitoring of the counter, auxiliary generator and the trigger, which leads to ambiguity of the result and the possibility of false switching.

The purpose of the invention is to increase the dignity of the control and expand the functionality.

The goal is achieved in a device for a redundant generator, containing a counter connected to the clock generator, the first And element, the trigger and the second And element, the first and second inputs of which are connected respectively to the output of the trigger and the first element And, and the output To the output element OR, the decoder, register, third AND element, encoder, error indicator, control unit and bit comparison element whose output is connected to the first inputs of the error indicator and the third AND element, are entered. to the outputs of the register, and other inputs to the outputs of the encoder, the inputs of which are connected to the outputs of the decoder and the output of the trigger connected by the installation inputs to the corresponding outputs of the decoder, the first m inputs of which are connected to the outputs m of the least significant bits of the counter, and the remaining (nm) inputs are from the outputs (nm) of the higher bits of the counter and with the inputs of the register, the installation input of which is connected to the reset input of the counter and to the first output of the control unit, the first, second and third inputs of which are connected respectively to the outputs of the gene clock pulse, the first element And to the corresponding output of the decoder, the second and third outputs of the control unit are connected to the synchronization inputs of the trigger and register, respectively, the fourth output to the second inputs of the error indicator and the third element And, and the fifth output to the third input of the error indicator , the output of which is connected to the third inputs of the second and third elements AND, while the fourth input of the third element AND is connected to the corresponding output of the decoder, and the output to another input of the output element IL .

In addition, the error indicator contains a trigger with an And element connected to the installation input, whose inputs are the inputs of the error indicator, and the inverse output of the trigger output of the error indicator.

Moreover, the control unit contains a Dzukhkanal delay element, a shaper of a predetermined interval and a synchronization block whose inputs are the inputs of the control unit, the first output is connected to the control input of the two-channel delay element and the first output of the control unit, the second and third outputs control unit, and the fourth output is connected to the information input of a two-channel delay element and one input of a generator of a given interval, the other input of which union of the two-channel output with delay element and to third output of the control unit, and the output is the fifth output of the control unit.

FIG. 1 shows a block diagram of the device; FIG. 2 - block diagram

control unit; in fig. 3 timing charts of the control unit.

The device for monitoring the redundant generator contains an element AND 1, a generator of 2 clock pulses, a counter 3) a decoder k, a trigger 5 an element AND 6, a second element AND 7 a third element OR 8, an encoder 9. a register 10, an element of bit comparison 11, an indicator 12 Errors, block 13 control.

The error indicator contains a trigger 1 and the element 15- The control unit 13 contains a synchronization unit 1b, a two-channel delay element 17,

shaper 18 of a predetermined interval, inputs, outputs 22-26 of control unit 13. The synchronization unit 16 comprises a trigger 27, element 28, element OR 29, a delay element 30. Two-channel delay element 17 contains a trigger 31, elements AND 32 and 33. elements 3 and 35 of the delay, element 2И-OR Зб. The shaper 18 of the specified interval contains the trigger 37, the element OR 38, the element zade. Rzhki 39.

The device works as follows.

In the initial state of the device

counter 3 is in the zero state, register 10 is in one for all bits, device triggers are in the zero state. The clock pulses from the generator 2 are calculated by the estimator 3, and are also fed to the first input .19 of the control unit 13.

The output pulses from element 1, the frequency of which is monitored, are fed to the second input 20 of control unit 13, which produces a response to zero the counter 3 and set register 10, and also to the first input of element 6, to the second input of which a signal comes from the trigger 5 specifies the allowable interval of the monitored pulse, and the third input is a single signal from indicator 2, which corresponds to the correct operation of the control equipment, and the zero signal is at its failure x. The trigger 5 is switched to the zero and one states by signals from the corresponding descramble outputs. i connected to the discharge bits of the counter 3- In this case, the switching times of the trigger 5 are determined from the condition of the temporal location of the pulse from element y in the interval when the trigger 5 is in the zero state and the zero signal from its output closes on the third input And 6. During normal operation of the monitored generator, the impulse from the AND element enters in the time interval when the second input of the AND 6 element receives the zero signal from the trigger 5, as a result of which the output signal of the AND 6 element is absent. In the event of faults leading to an increase in the frequency of the signal at the output of the And 1 element, the reset signal of the trigger 5 from the decoder C is absent, since the resetting of the counter 3 occurs earlier. Trigger 5 is not set to the zero state, i.e. the signal from its output enables the pulse through the AND 6 element to the output element OR 8. For faults that reduce the pulse frequency at the output of the AND 1 element, the signal with the corresponding output of the decoder C is fed to the fourth input of the element And 7 before the appearance of the zero pulse 3, as a result, the element And 7 is triggered, as its second and third inputs receive the enabling signals, while from its output the pulse goes to the output element OR 8 . AT During the counting process of the input pulses, the output signals (pt) of the higher bits of counter 3 are fed to register 10, to which the high bits of counter 3 are periodically rewritten before the next change, and the signals from the decoder and trigger 5 outputs are sent to the encoder 9 and are converted by encoder 9 into (nm) -digit binary code, the reading of which is one less than the current reading, the most significant (n-th) bits of counter 3. Codes from the outputs of the encoder 9 and register 10 are fed to the inputs of bit comparison element 11. With normal operation of generator 2, counter 3, decoder C, trigger 5 and other elements of the device, the output codes of register 10 and encoder 9 are the same, so the output of element 1 1 supports a single signal indicating the normal operation of the control equipment at the first inputs of the element And 7 and the indicator 12 and allows the operation of the element And 7, and also prohibits the operation of the indicator 12. If the codes received at the inputs of the bit comparison element 11 do not match, its output is set to Eve signal which is supplied to the inverted input AND gate 15 to the other inputs of which receives the enable signals to the control unit 13. Element I 15 operates and, from its output, the signal arrives at the setup input of trigger N. The trigger switches to one state, in which the zero signal from its inverse output enters the inputs of elements 6 and 7 and prohibits their triggering, thereby issuing a false command to switching back-up generator, which could have been issued in case of failure of the counter 3. decoder, trigger 5 of generator 2 and other elements of the control equipment, when the time interval at the output of trigger 5 is formed with an error and Is the possibility of issuing a false command to switch the backup generator. Thus, if control equipment malfunctions, a zero signal is set at the output of the trigger T, which is fed to the inputs of elements And 6 and 7, prohibits their triggering and, thereby, prohibits the detection of a false signal to the output element OR 8.

The current reading of the counter 3 converted by the decoder 4 and the encoder 9. is continuously monitored by bitwise comparison element 11 by comparing with the register reading 10, which periodically reads the high-order bits of the counter 3 by a signal at its synchronization input to all register bits are one. The unit state of the bits of register 10 at the inputs of element 11 corresponds to the zero reading of counter 3 converted by decoder k and encoder 9 Signals for controlling reset of counter 3i by resetting and register synchronization 10, trigger synchronization 5. by blocking the elements And 7 and 15 in during short intervals of the end of the transient switching of information codes arriving at the inputs of the element 11 at random comparison, are generated by the control unit 13. The input 19 of the control unit 13 receives the clock pulses from the generator 2, used to synchronize the output signals of the control unit 13, the input 20 - the pulses from the output of the first element I 1, used to generate the response pulses of the reset of the counter 3 and set the register 10 to the input 21 —a signal from the corresponding output of the decoder, which takes a single value at zero state m the least significant bits of counter 3 and is one if at least one of the m least significant bits is different from zero.

From the output 22 of the control unit 13, pulses synchronized with clock pulses arrive at the reset of counter 3 and resetting the register 10 to the initial state. By synchronizing the reset pulses of counter 3 and setting the register 10 with clock pulses, the stability of rewriting the switching times of information switching elements 11 since the prohibition of the operation of the elements And 7 and 15.

 From the output 23 of the control unit 13, pulses delayed relative to the clock pulses of the generator 2 for the duration of the transition are removed.

process in the counter 3. and also on the time of signal propagation through the decoder k. These pulses are fed to the synchronization input of trigger 5 and allow it to switch without dangerous contests during the switching time of the bits of counter 3, thereby achieving more reliable registration by trigger 5 of a predetermined interval.

From the output 24 of the control unit 1, the signal is fed to the synchronization input of the register 10. This signal is delayed relative to the signal of the zero state of the lower bits of the counter 3 to the control unit 13, which arrives at the input 21, for a fixed time f, which is selected slightly less than the change time of the reading (nm ) the older bits of the counter 3 so that the new code is overwritten to the register 10 immediately before the next change in the display of the higher bits of the counter 3C of the output 25 of the control unit 13 negative pulses are received to the second inputs of units 7 and 15, these signals are generated on the leading edge of the clock pulses from generator 2, and the duration of these signals is chosen slightly longer than the propagation time of signals through counter 3, the decoder trigger 5, and the encoder 9- negative pulses from the output 25 of the control unit 13 prohibits the triggering of the elements 7 and 15 for the time of switching information and thereby prevents the possibility of false alarms of the elements 7 and 15.

Claims (2)

At the output 26 of the control unit 13, a negative pulse is formed, the leading edge of which coincides with the synchronization pulse of register 10, and the duration of this pulse sets the length of the time interval in which an increase in the unit of indication (p-ha) of the high bits of the counter 3 should occur. The output 26 of the control unit 13 is fed to the third input of the element 15 And prohibits its triggering at a predetermined time interval. Upon termination of this pulse, the operation of element 15 on the third input is again enabled, and if by this time the indication of the higher bits of the count 3 does not increase by 9 units relative to the indication recorded on register 10, in this case the codes do not match the inputs of element II and a single signal from the output of element 11 will trigger the indicator 12, which detects a disturbance in the operation of generator 2, counter 3. decoder C and other elements of the control equipment, and a zero signal from the output ind locator 12 prohibit operation of AND 6 and 7 and issuing false switching command generator Rezer Nogo case 2 abnormality in the control equipment. Let us consider in more detail the operation of the control unit 13 (Fig. 2) The clock pulses through the input 19 are fed to the inverse input of the OR element 29 and to the input of the delay element 30 (Fig. 3a). On the leading edge of the clock pulse at the output of the element OR 23, a negative pulse is formed (Fig. 36), the duration of which is determined by the delay of the element 30. After some time determined by the delay before the element 30 is retracted, the clock pulse arrives at the output 23 of the control unit 13, and further to the trigger input of the trigger 5, allowing its operation after a certain time, during which the output signals of the decoder 4 are set. At the output of the element OR 2 negative pulses are formed (Fig. 3b), which are drop from output 25 to the inputs of elements And 7 and 15, as well as to the synchronization input of trigger 27 and to one input of element 28, to another input of which from input 21 receives a signal from the corresponding output of the decoder (Fig. 3 Sv), which takes a single value in the zero state m the lower bits of the counter 3- This state of the counter 3 is used to detect the moments of change in the indications of the higher bits of the counter 3 and generate control signals to write information to the register 10 immediately before the next change in the indications of the high bits s 3PO counter as clock pulse count m LSBs cchetchika 3 is periodically set to the null state, the inlet 21 of the control unit 13 is of unit ,. 7, the signal that arrives at the input of element And 28. After the negative pulse is output at the output of element OR 29 (Fig. 36), the input element And 28, And 28 also triggers a pulse from its output (Fig. Zg) the inputs of the elements 32 and 33 to the other inputs of which are received signals from opposite outputs of the trigger 31 (Fig. Hw, shows the signal of the inverse output of the trigger 31). which open element 32 and close element 33 and element 32, the iji triggers a pulse (fig. 3e) to the delay element 3, the delay time t of which is chosen slightly less than the period of change in the readings of the higher bits of the counter 3, the pulse from the output of element 3 (fig .3) is fed to one input of the element AND element 2И-OR Зб, opened on the other input by a single signal from the inverse output of the trigger 31- From the output of the element Zb, a pulse formed in duration (Fig. ЗЗ) is fed to the output 2k of the control unit 13 and further n synchronization input of register 10, allowing overwriting to register 10 of a new code immediately before changing the counter 3 indication. At the same time, the pulse from the signal element arrives at the setup input of the trigger 37, the inverse output of which sets the 1-th signal from the output 2b (Fig. Zi) of block 13 control to the input of the indicator 12 and prohibiting its operation at the time of switching the codes on the register 10 and the counter 3, the return of the trigger 37 to the initial state is performed through the element OR 38 by a pulse from the AND 28 element, which blunt after installation LSBs of the counter 3 to the zero state. If the generator 37 or counter 3 or other elements of the control equipment fails to return to its initial state, the 37 is returned to its initial state from delay element 39 (FIG. G3), the delay time of which specifies ;; the interval during which the information should change to the register 10 and the higher bits of the counter 3- Trigger 37 returns to its initial state and a single signal from the inverse output to the input of the indicator 12, enables it to be triggered if the codes at the input of the element 11 do not match. The failure of the elements of the control equipment. If the generator malfunctions (skip or absence of pulses), the reading of the counter 3 stops changing, and there will be no pulses at the output of the OR 29 and AND 28 elements. In this case, the pulse generated by the last output pulse of the delay element 3 (or 35), which appears at the output of element 2I-36, enters the synchronization input of register 10 and allows the code of the high bits of the counter / 3 to be overwritten on it. The register 10 is used to establish the indication of the higher bits of the counter 3, which from the outputs of the register goes to one input of element 11, to the other inputs to which from the encoder 9 the code is less than one value. In this case, the codes at the inputs of element 11 do not coincide, and a zero signal is set at its output, which indicates the failure of the control equipment. Well, the left signal from the output of element 11 decides at the input the operation of the element AND 7 and resolves the operation of the element 15 at the inverse input. At the second input of the element 15, the enable signal comes from the element OR 29 and the third input receives a single signal from the inverse output of the trigger 37 The initialized state of the 39 Element I 15 pulse from the output is triggered and the signal from its output goes to the set-up input of the trigger I, which switches to the single state and thereby fixes the occurrence of the control equipment (in this case, the failure of the generator 2). The zero signal from the inverse of the trigger output k prohibits the triggering of the elements 6 and 7 and thereby prevents the formation of a simple command to switch the backup generator. The impulse from the element AND 1 at the input 2 of the control unit (Fig. 3L) arrives at the I-input 1 of the K-flip-flop 27. On the control input which receives 8712 pulses from the OR-29 element. At the output of the flip-flop 27 a pulse is formed (Fig 3 m), synchronized by clock pulses, which is fed from the output 22 of the control unit 13 to the reset of the counter 3 and setting the register bits to one state. At the same time, the pulse from the flip-flop 27 is fed to the counting input of the flip-flop 31, while the flip-flop 31 switches to a single state and zero signal from the inverse output kryvaet AND gate 32 and a NAND element 2I-OR 36, in order. the pulse generated by the delay element 3 is neutralized by the previous pulse from the elements 28 and 32, which were filled before the reset of the counter 3. The single signal from the direct output of the trigger 31 opens the input element 33 and the other element 3 of the anti-virus element one input. When the counter 3 is reset to its initial state, a single signal appears at the output of the decoder A connected to the input 21 of the control unit 13, the unit signal (FIG. 10B), And 28 is working. A pulse from its output (Fig. 3g) through the element OR 28 switches the trigger 37 to the zero state, thereby removing the signal for the indication of the activation of the indicator 12 generated by the inverse output of the trigger 37. Thus, the resolution of the indicator of the indicator of the indicator 12 is synchronized with the moment of switching information at the higher bits of the counter 3, so that the device is not critical to change within certain limits the magnitudes of the delays of elements 3, 35 and 39 and does not complicate the implementation of these delays. At the same time, the impulse from the AND 28 element arrives at the AND 33 element, opened at a different input by a single signal from the trigger 31 - Element. And 33 is triggered 1 and. from its output a pulse (Fig. 3N) goes to delay e.piment 35, and through time C, a pulse from the output of delay element 35 (fig.Zo) passes through the SC element (Fig. W) to the synchronization input of register 10, allowing overwriting to the code before the next change in the high-order bits of the counter 3, also enters the installation input of the trigger 37 which switches and forms the beginning of the interval of the prohibition of the operation of the indicator 12, and also 13 enters the input of the element 39 and enters the trigger 37 the original The state and the end of the interval of the prohibition of the operation of the indicator 12 in case of failure of the control equipment. Thus, the operation of the generator 2, counter 3, decoder i, trigger 5 of the encoder 9 of register 10 and control unit 13 is continuously monitored by matching signals at the inputs of bit comparison 11, the outputs of which are converted by decoder C, trigger 5 and encoder 9 current readings of the counter 3. e to the other inputs are received recorded by the register 10 readings of the higher bits of the counters 3 are rewritable into the register 10 before each successive change of the readings of the higher bits of the counter 3 - Block 3 controls At the output 26, the time intervals form during which information on counter 3 and register 10 change before each change in the high order bits of the counter by delaying the low-order signals of the zero bits of the counter 3 selected by the decoder 4 and the synchronization unit 16. The signals from the outputs 25 and 2b of the control unit prohibit the activation of the indicator 12 for the duration of information transients. The signals from outputs 22 23 and 2 of the control unit are used respectively to return counter 3 and register 10. to their initial state, synchronization of trigger 5 and register 10. Disruption of generator 2 (changing the period of the clock pulses over the boundary values), counter 3 ( for example, malfunctions of the lower bits and other nodes of the control equipment cause a failure in changing the output codes of the encoder 9 and the register 10, which leads to the operation of the indicator 12. Violation of the operation of the bit comparison element 11 and indicator 12, causing their false positives, does not lead to the device issuing spurious commands for switching the backup generator and are also recorded by the output signals of the indicator 12. The design features of the proposed technical solution increase the reliability of control due to the 9 7I control of the auxiliary pulse generator, counter , decoder, tr igger and other elements of the control equipment by continuously comparing the code with the encoder at the input of the bit comparison element connected to the indicator m, with the indication of the register to which the indication of the higher bits of the counter is copied on the eve of their changes as commanded by the control unit. At the same time, the functionality of the device is expanded by making it possible to select a predetermined interval for monitoring the pulse pulse period by connecting the corresponding outputs of the decoder to the trigger inputs and an additional element I. Isolation formula A device for monitoring a redundant generator, containing a counter connected to the clock generator, the first element And, the trigger and the second element H, the first and second inputs of which are connected respectively to the trigger output and the first The element is And, and the output is to the output element OR, characterized in that, in order to increase the reliability of the control and expand the functionality. A descrambler, a register, a third element AND, an encoder, an error indicator, a control unit, and a bitwise comparison element are entered into it, the output of which is connected to the first inputs of the error indicator and the third AND element, some inputs to the outputs of the register, and others to the outputs of the encoder, the inputs of which are connected to the outputs of the decoder and the output of the trigger connected by the installation inputs to the corresponding outputs of the decoder, the first m inputs of which are connected to the outputs m of the least significant bits of the counter, and the rest (nm) inputs with outputs (nm) high x bits of the counter and register inputs mounting | th input of which is connected to the reset input of the counter and to the first output of the control unit, the first, second and third inputs of which are connected. respectively, to the outputs of the clock generator, the first element And to the corresponding output of the decoder, the second and third outputs of the control unit are connected to the synchronization inputs of the trigger and register, respectively; the fourth: the output to the second inputs of the error indicator and element And, and the fifth output - to the third input of the error indicator, the output of which is connected to the third inputs of the second and third elements AND, while the fourth input of the third element AND is connected to the corresponding output of the decoder, and the output to another the input of the output element OR. 2. The device according to claim 1, which is indicated by the fact that the error indicator contains a trigger with an element I connected to the installation input, the inputs of which are the inputs of the error indicator and the inverse output of the trigger is the output of the error indicator. 3. The device according to claim 1, characterized in that the control unit contains a two-channel delay element, a driver of a predetermined interval and a synchronization unit whose inputs are the inputs of the control unit, the first output is connected to the control input of the two-channel delay element and the first output of the control unit , - the second and third outputs are respectively the second and fourth outputs of the control unit, and the fourth output is connected to the information input of the two-channel delay element and one input of the driver is specified about Tervala and whose other input is connected to output two-channel delay element and to third output of the control unit, and the output is the fifth output of the control unit. Sources of information taken into account in the examination of 1, USSR Author's Certificate fP, cl. And 03 K 1/00, 1972. 2. USSR author's certificate №, cl. H 03 K 1/00, 1977. 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