SU1541763A1 - Switchboard for switching stanby generators - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in the synchronization systems of computing devices with increased reliability. The purpose of the invention — improving the reliability of the switch — is achieved by increasing the number of channels and the majority selection of the output signal. The switchboard contains three identical channels, each of the first inputs of which are connected to the first, second and third input buses, respectively, and to the second and third inputs of adjacent channels, and each channel contains AND 7, majority element 8, counter 9, two registers 5, 6 , two inverters 12, 14 and multiplexer 4, the first, second and third information inputs of which are connected to the first 1, second 2 and third 3 inputs of the channel, and the third information input of the multiplexer 4 is connected to the synchronization inputs of the registers 5, 6 faults, output 15 ka dogo channel coupled to inputs 16 and 17 of adjacent elements majority 8. The switch allows the block a permanent failures by a single switching on reserve. The switch does not parry repeated failures; however, in the case of short-term and intermittent failures in different generators, it is possible to repeatedly replace the failed generators around the ring. 2 Il.

Description

05 & 0

Fig1

15 16 P 10

The invention relates to automation and computing and can be used in systems for synchronizing computing devices with increased reliability.

The aim of the invention is to increase reliability by increasing the number of channels and the majority Sampling of the output signal.

Figure 1 shows the functional and channel diagram of a three-channel switch; Fig. 2 is a schematic of Channel Connections (e.g., three) for switching back-up generators.

Each switch channel contains inputs 1-3, connected to the information inputs of multiplexer 4, while input 3 is also connected to the synchronization inputs of registers 5 and 6, the higher-order output of which is connected to the inputs of the And 7 element, the output of which through the majority element 8 is connected to the counting input of the counter 9, with its installation input connected to the installation bus 10 to the initial state, and the outputs with the control inputs of the multiplexer 4, the output of which is the information output 11 of the device connected to the enable input parallel recording of the fault register 5 and through the inverter 12 with the input of the parallel recording write register 6, the parallel recording inputs of registers 5 and 6 are connected to the logical unit 13 bus, and the serial write inputs to the output of the inverter 14 connected to the logical unit 13 bus , while the output element And 7 is connected to the output 15 of the channel. The second and third inputs of the majority element 8 are connected respectively to the fourth 16 and fifth

17 channel inputs.

The switch for switching the backup generators (FIG. 2) contains the first 18, second 19 and third 20 channels. First input 1 of the first channel

18 is connected to the first input bus 21, with the second input 2 of the second channel

19 and the third input 3 of the third channel 20. The second input bus 22 is connected to the input 3 of channel 18, the input 1 of channel 19 and the input 2 of channel 20. The third input bus 23 is connected to the input 2 of channel 18, the input 3 of channel 19 and the input 1 of channel 20 Exit 15

five

0

five

0

five

0

five

0

five

channel 18 is connected to inputs 17 and 16, respectively, channels 18 and 20. Output 15 of channel 20 is connected to inputs 17 and 16, respectively, channels 18 and 19.

The switch works as follows.

When the signal is reset to the initial state via bus 10, the counters 9 of all channels, the number of possible states of which are equal to the number of switched generators, in this case three, are set to different states, for example, in channel 19 to 00, in channel 20 - 01, in channel 18-10. These codes go to the control inputs of multiplexers 4, while in channel 19 the information output 11 receives a signal from input 1, in channel 20 from input 2, in channel 18 from input 3, t . Outputs 11 of all channels are given a signal from bus 22.

The signals from the output of multiplexer 4 are fed to output 11, as well as in direct and inverse form - to the enable inputs of parallel recording of registers 5 and 6, respectively, and under the influence of logic 1, coming through bus 13 to the inputs of parallel recording of these registers, set them to the original state With the next signal when this signal is confirmed. In the event of a malfunction in the generator, output 11 is set to a constant one or zero level, and one of the 5 L registers 6 is freed from the setting enable signal in the single state. In this register, under the action of synchronizing pulses from input 3, the operation of a logical O applied to the input of a sequential record from the output of the inverter begins. The shift occurs in two channels of the device in which the failed generator is not connected to inputs 3.

In the remaining channel, the shift is impossible due to the absence of shear pulses at the inputs of the register Sensors 5 and 6. As a result of the shift after a time equal to N periods of the signal following frequency at input 3, where N is the number of bits of registers 5 and 6, the output the oldest bit appears to be a malfunction in the form

logical 0m and through the element 7 and the majority element 8 together with the fault signal of the adjacent channel is fed to the counting input of the control counter 9, which increases its state by one.

The effect of increasing the state of the counters occurs in all channels, while for the initial state specified above, the output values of the control counters are as follows: channel 19–01, channel 20–10, channel 18–00, i.e. a backup generator connected to bus 21 is connected to the outputs II of all channels, i.e. The signal from one, but already backup, generator is connected. The delay time of the formation of a fault signal by registers 5 and 6 is determined by their width, so the choice of bit is due to the allowable time interval during which there are no signals on the input bus selected by the switch. If this interval is exceeded, the selected generator is automatically discarded and replaced with a backup one.

In case of permanent failures, the switch performs a single switch to the reserve and does not counter the second failure. However, in the case of short-term and moving failures in different generators, multiple replacement of the failed generators around the ring is possible, provided that by the time of the occurrence of the subsequent failure the previous one is removed.

Claims (1)

Invention Formula A switch for switching back-up generators, containing two channels, a new input of each of which is connected respectively to the first and second input buses, each channel contains the first and second registers, the parallel recording inputs of which are connected to the bus. Logical unit, first and second inverters, counter, element And the first and second inverters, characterized in that, in order to increase reliability, a third channel is introduced, the first input of which is connected to the third input bus, to the second input of the first channel and the third input of the second channel,. the first input bus is connected to the second input of the second channel and the third the input of the third channel, the second input bus is connected to the second input of the third channel and the third input of the first channel, the output of the first channel is connected to the fifth input of the second and fourth entrance of the third channel, the output of the second channel is connected to the fourth input of the first and third input of the third channel, output the third channel is connected to the fifth input of the first 0 and the fourth input of the second channel, each channel additionally contains a major element and a multiplexer, the first, second and third information inputs of which are connected to the first, second and third inputs of the channel, respectively, and the third information input of the multiplexer is connected to the synchronization inputs of the first and second registers, consecutive write inputs of which are connected to the output of the first inverter, whose input is connected to the bus. Logical unit, the enable input of the parallel recording of the first register and through the second inverter, the parallel-write enable input of the second register is connected to the multiplexer output and the information output of the channel, and the high-order outputs of the first and second registers are connected respectively to the first and second inputs of the AND element whose output is connected to the first input of the major element and the channel output, the output of which is combined with the counting input of the counter, the installation input of which is connected to the installation bus to its initial state, and the outputs - with the control inputs of the multiplexer, the second and the third yi The inputs of the majority element are connected respectively to the fourth and fifth inputs of the channel. 21 21 Have 18 15 sixteen 17jF 23 7 t 3 1 g s ig zo ww 15 sixteen 17 Figg