SU805319A2 - Redundancy device - Google Patents

Description

(54) RESERVED DEVICE

The invention relates to automation and computer technology and can be used in automatic control and monitoring systems to increase their reliability. According to the main author. St. 506859 a redundant device is known which contains in each channel a reserved block, a major control element, an inequality element, an integrating element, a first memory element, an OR-AND element, a restoring authority, and the first AND element l. A disadvantage of the known device is that it loses operability after any failure of one of the two remaining operational redundant blocks, since the process of shutting down the failed redundant block or changing the trigger threshold of the restoring authority continues after two operable redundant blocks remain in the device. In this connection, the structural capabilities of the device are not sufficiently utilized to enhance its Scalability. A disadvantage of the known device is that it loses operability in case signals at the outputs of redundant blocks are formed with frequencies exceeding the frequency of shaping useful signals two or more times. For example, if such faults occur in the device sequentially in time, then after the number of failed redundant blocks is equal to the response threshold of the repressor, the spurious signals pass to the output of the device and it loses operability. This is due to the fact that the re-inclusion in the scheme of the device of the reserved block after its failure or failure occurs when the signal at its output coincides with the signal at the output of the major control element. As a result, the reliability of the device is reduced. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that the device according to ed. St. No. 506859, a second memory element, a second AND element, a delay element and an additional majority element, whose inputs are connected respectively to the first memory elements of other channels, are inserted into each channel.

The output is with the additional input of the unequal element, the output of the first element I is connected with the counting stroke of the second memory element And through the second element I is connected to the input of the first memory element O and the output of the second memory element is connected with the second input of the second element And, the installation input to the O of the second memory element is connected to the output of the integrating element, and the output of the restoring organ is connected through the delay element to the installation input to the To of the redundant unit.

The drawing shows a functional diagram of the device.

 The device contains in each of the m channels a reserved block 1 (for example, a counting device), major-. container element 2 controls, element 3 inequalities, restorations organ 4., integrating element 5, element b OR-AND first memory element 7, first element 8 AND, inputs 9 redundant units 1, device outputs 10, input .11 of initial installation the device, in addition, the device contains in each channel an additional majority element 12, a second memory element 13, a second AND element 14 and a delay element 15. The element 3 inequivalence of each channel includes the elements 16 NOT, the element 17 AND and the element 18 OR. The inputs to the inequality element 3 are inputs 19-21.

The device works as follows.

When the power is turned on, the first memory element 1 and the second memory element 13 in each channel, as well as the reserved block 1 (if necessary) are set to O by the initial setup signal, received at input 11 of the initial setup of the device. In the initial state, the signal from the output of the first memory element 7 allows the input of the signal from the output of the reserved block 1 through the b OR-I element, and the signal from the output of the second memory element 13 prevents the signal from the output of the first element 8 AND through the second element 14 AND When the reserved blocks 1 work correctly, the signals from their outputs go through the element 6 OR-I to the inputs of the recovery organs 4 and then to the output 10 of the device. The signal from the output of the reducing body 4 in each channel performs (if necessary) the installation of the redundant unit 1 in the state O through the element. 15 delays to prepare the device for the next cycle | work. In addition, the signal from the output of the reducing organ 4 in each channel is fed to the inputs of the major control element 2 in its

nale and all other channels. Since the signals at the inputs 19 and 20 of the element 3 unequalities coincide in time, then at the inputs of the element 18 OR the signal is not generated. Due to the influence of the response time of the 6 OR-AND elements, the recovery body 4 and the major control element 2, the signal at the input 19 of the inequality element 3 may be delayed, which can lead to the formation of an interference signal at the output of the OR element 18. The elimination of short-term interference from the output of element 18 OR to the single input of the first memory element 7 is carried out using the integration of element 5, which can be performed, for example, in the form of a KS chain. The failure or failure of any redundant block 1 is detected using the unequal elements 3, to the inputs 19 and 20 of which, respectively, signals from the inputs of the majority element are received. 2 control and reserved block 1 in the same channel. In the event that the signals at the output of the major control element 2 and the redundant block 1 do not match, a corresponding pair of elements 16 NOT and elements 17 And generates a signal that, through element 18 OR and integrating element 5, enters the unit input of the first memory element 7 and the second input zero. memory element 13. By a signal from the output of the integral element 5, the first memory element 7 is set to state 1, and a control signal is generated at the output of the first memory element 7, which is fed to the input of element 6 OR-AND. If AND elements are used as b OR-AND elements, then the control signal from the output of the first memory element 7 prohibits the signal from the failed redundant block 1 to the inputs of the recovery organs 4. If the OR-AND elements are OR circuits, the control signal from the output of the first memory element 7 passes to the inputs of the recovery organs 4 and reduces them by triggered by 1. Therefore, when using the OR elements, the thresholds of the recovery organs 4 must be equal to ml, and when used The elements and thresholds of the regenerating organs 4 must be 2.

The first memory element 7 failed due to the failure of the redundant block 1, and not due to its final failure, WHAT is detected when the normal signal is generated by block 1 in successive work cycles, the disabled channel is again included in the device circuit using the second memory element 13, the first and

The second elements are 8 and 14 I. This happens as follows. When the signal at the output of the reserved block 1 coincides with the signal at the output of the major control element 2 at the output of the first element 8, a signal is generated that does not pass through the second element 14, since the latter is closed by a signal from the output of the second element 13 Psi. After the fall of the trailing edge of the output signal. the first element 8 And the second memory element 13 goes into state 1 and prepares the second element 14 for passing the next pulse generated at the output of the first element 8 and in the next cycle of operation. If after this in the next cycle of operation of the device at the output of the redundant unit 1 a signal is generated that coincides with the signal at the output of the major control element 2, which indicates restoration of the operability of the reserved block 1, then the output of the first element 8 again generates a signal that passes, through the open second element 14 and to the input of the installation of the first memory element 7 in the state O. Thus, the signal from the output of the redundant unit 1 to the inputs of the recovery authorities 4 is allowed if the AND elements are used or restored ( is increased by 1) the threshold of response of the reducing organs 4, if the elements OR are used as the elements of 6 OR-AND. After the falling edge of the falling edge, the signal at the output of the first element 8 is reset to the initial state of the second memory element 13.

As the redundant -1 blocks fail, for example, if the failure type is false 1 or false 0, the first memory elements 7 in the failed channels are set to state 1 and prepared for the first 1 action of the majority elements 12 in all channels except their own. The thresholds for triggering the majority elements 12 are selected equal to t-2 in order to ensure the formation of the signal at their outputs in the correct operation of the cx channels after the device has two operational redundant backup devices 1. At the same time, in each of the two remaining operational channels, the signal from the output of the majority elements 12 are fed to input 21 of element 3 of ambiguity and prohibits the operation of elements 17I. Thus, further operation of the first memory elements 7 in the remaining two healthy channels is prohibited. when the signals at the outputs of the reserved blocks 1 and the majority elements of the control 2 do not match. If the elements OR, AND the two remaining operable | redundant blocks 1 turn out to be connected by the OR circuit, and if the elements AND are used, - according to the scheme I. If the subsequent failure in the first case was of the false O type, and in the second case - of the false 1 type, then the device continues to function normally with one remaining operational channel. In the failed channels, the function of the 3 unequalities is not prohibited. This is necessary in order for a failure, for example, of the false 1 type, which is always present at the output of the failed redundant block 1 ,. The possibility of generating signals at the output of the unequal element 3 was not excluded if the signals at its inputs 19 and 20 did not match to confirm the single state of the first memory element 7 and the zero state of the second memory element 13. This happens as follows. If the output of the failed redundant block 1 is always present, the signal is false 1, and only two operational channels remain in the device, that is, and the time when the signal was formed at the outputs 10 of the device, in turn, at the outputs of the first element and 8 a signal that leads to the setting of the second memory element 13. . But at the moment when there are no signals at the outputs 10 of the device and, consequently, at the outputs of the major control elements 2, an inconsistent signal is again formed. Outputs: element 3 inequalities in the channel in which the outputs of the redundant unit 1 is constant

0, the signal is false 1, which leads to the confirmation of the single state of the first element 7 pn and the zero state of the second memory element 13 by a signal from the output of the integrating element 5. This eliminates the possibility of connecting the faulty redundant unit 1 into the device circuit.

The device ensures the preservation of operability with one healthy channel and if the outputs of the failed redundant blocks 1 generate signals with a frequency exceeding the frequency of the trace 5 useful signals two or more times. This happens as follows. If, for example, the frequency of the signals following the output of the first failed redundant block 1

0 is twice the frequency of the useful signals, then at the time of the occurrence of a false-type signal 1 at the input 20 of element 3 inequalities, a mismatch is fixed in this channel

Claims (1)

1. USSR author's certificate, 506859, cl. G 06 F 11/00, 1973.