SU1099388A1 - Device for checking counters - Google Patents

Abstract

DEVICE FOR CHECKING COUNTERS, containing m groups of information buses, h equivalence elements, AND-NOT element, pulse generator, first AND element, first trigger and control bus, which is connected to the installation input of the first first trigger, direct output which is connected to the first input of the first element I, the second input and the output of which are connected respectively to the output of the pulse generator and to the output clock bus, the inputs of each equivalent element are connected to the information buses of the same name of each YES g The information bus group, the outputs of the elements of equivalence are connected to the input of the AND-HB element, characterized in that, in order to expand the functional capabilities, an OR element, an OR-NOT element, a second, third AND element, an NOT element, an element delays, a second trigger and n additional triggers, the installation inputs in O are connected to the installation input O of the second trigger and the control bus, the installation input to 1 of each of the 11 additional triggers is connected to the corresponding information bus of one of the M information groups tires with the corresponding input of the element OR NOT, the output of which is connected to the first input of the second element AND, the rest: the inputs of which are connected to the corresponding direct outputs and additional (L triggers, the output of the second element AND is connected to the installation input 1 of the second trigger, The direct and inverse outputs of which are connected respectively to the inputs of the NOT element and the delay element, the outputs of which are connected to the inputs of the third AND element, the output of which X) is connected to the first input of the OR element, the second input and the OUTPUT th; it is connected respectively with the output: about the NAND element and with the input, and installed the V of the first trigger. X 00

Description

The invention relates to computing and is intended to control digital sequential devices, in particular, counters, shift rotors, etc. A device for checking counters is known, comprising a pulse generator, an AND element, a control bus, and n + 1 OR-NOT 1 elements. A disadvantage of the known device is the relatively narrow functionality associated with the fact that each discharge of the counters is not controlled, i.e. There is no information about exactly what kind of counter discharge failed. A device for checking counters is known, containing groups of tt information buses, n equal elements, the AND-NOT element, the pulse generator, the first AND element, the first trigger and the control bus, which is connected to the installation input of the first first trigger, direct output which is connected to the first input of the first element And, the second input and output of which are connected to the output of the pulse generator, and With the output clock bus, respectively, the inputs of each element of equivalence are connected to the same information buses of each of the m RUPP data lines, the equivalence element outputs are connected to inputs of element Q-NOT output is connected to a vhodzyum ustanrvki On the first trigger. When monitoring counters, the output clock is connected to the clock inputs of the counters, the information outputs of each of which are connected to the corresponding group of information buses of the device. The device indicates a failure when there is a mismatch of at least one bit of a counter by the same name of a number of other 2J counters. A disadvantage of the known device is relatively narrow functionality, i.e. it does not allow detecting constant faults (const 1, const 0), which can occur on the same outputs of the checked counting decades during their serial production, for example, if on the same output of checked eras "counting decades," If this signal is logical O or logical 1, then regardless of the algorithm for checking the counters at the output of the corresponding element of equivalence, whose inputs are connected to the faulty one-exchange outputs of the first counting decade, the constant signal is logical 1, It corresponds to the state of the meter is working properly in their real fault. The purpose of the invention is to expand the functionality. The goal is achieved ten, that in the device for checking the counters, containing M groups of AND information buses, equivalence elements, the element AND-NOT, the pulse generator, the first element AND, the first trigger and the control bus, which is connected to the input of the installation in 1 of the first trigger The direct output of which is connected to the first input of the first element I, the second input and output of which is connected to the output of the pulse generator and the output clock bus, respectively, the inputs of each element are equal to those of the same name. With each tires of informational groups of information buses, the outputs of the equivalence elements are connected to the inputs of the NAND element, the OR element, the OR OR element, the second, third AND elements, the NO element, the delay element, the second trigger and the AND additional triggers, the inputs are entered. installations in About which are connected to the input of the installation in О of the second trigger and with the control bus the installation input in 1 of each of n additional triggers is connected to the corresponding information bus of one of the information bus groups and to the corresponding input of the I element LI-NOT, the output of which is connected to the first input of the second element I, the remaining inputs of which are connected to the corresponding direct outputs n additional triggers, the output of the second element I connected to the installation input 1 of the second trigger, the direct and inverse outputs of which are connected to the inputs of the element NOT and the delay element, respectively, the outputs of which are connected to the inputs of the third element AND, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the NAND element and to the installation input in O first trigger respectively. The drawing shows a diagram of a device for checking five counters. The device contains the first element 1 and, the generator of 2 pulses, the first trigger 3, counters (counting decades) -, element 5 AND –NE, elements - equivalence, control bus 7, additional triggers 8 - 11, element 12 OR-NOT, the second element 13 and the second trigger 14, element 15 NOT, the delay element 16, the third element 17 AND, element 18 OR, the group of information buses and the output clock 20. control plane 7 is connected with, the installation inputs in About the silent triggers 8-11, the second trigger 1 4 and with the installation input into the 1st first trigger 3, the direct output of which is connected to the first input of the first element 1 I, the second input and output of which are connected to the generator output 2 pulses and the output clock clock 20, respectively, the inputs of the element equivalencies are connected to the first information buses from groups - the second information buses of which are connected to the inputs of the equipotency element, the inputs of the equivalence element are connected by t third information buses from groups 19, the fourth information buses of which are connected to in The signals of the equivalence element, the outputs of the equivalence elements are connected to the inputs of element 5 AND-NOT, the output of which is connected to the second input of element 18 OR, the output and the first input of which are connected respectively to the installation input on the first trigger .. 3 and the output tert The element 17 AND whose inputs are connected to the output of the delay element 16 and the output of element 15 is NOT responsibly, the inputs of which are connected to the inverse and direct outputs of the second trigger 14, respectively, the input of which 1 is connected to the C output the second element 13 the first input of which is connected to the output of the element 12 OR-NOT, the inputs of which are connected to the information buses from the group, respectively, and connected to the installation inputs to 1 additional triggers 8 11, respectively, whose npHNbie outputs are connected to the additional inputs of the second element 13 I. Output clock - 20 is connected to the clock inputs of the counters -, the outputs of which are connected to groups - information buses, respectively. The device works as follows. With the arrival of the enable signal on the control bus 7, the triggers 8.9, TO, 11 and 14 are set to the state O, and the trigger 3 to the state 1, At the inverse input of the trigger 14 the signal 1 appears, which through the element 16 delays, with a time delay (; -C- arriving at the first input of element 17I. Element, delay 16 ment provides a delay of a single signal for time where n is the counting limit of the counter} t oscillator frequency 2, which corresponds to the passage of two times checked cycles (20 pulses) needed to check the counting decade for lack of cons When the trigger 3 is set to the resolving state, the pulses from the generator 2 through the two-input element 1 simultaneously arrive at the inputs of all checked counting decades - if all the decades are good, then the inputs of the elements 6 are in phase with the same amplitude signals, consequently, the signal 1 appears at the output of the equivalence elements 6, and the signal O at the output of element 5 is AND, which is fed to the first input of the installation at the O flip-flop 3 through the element 18 OR, with the result that the flip-flop 3 is held in the resolving PICs SRI generator 2 shutdown occurs. At the first checkout cycle, at the outputs of the counting decade, according to the algorithm of the counter, single signals appear, as a result of which the triggers 8-11 are alternately set to state 1, therefore the direct outputs of these triggers will also have signals 1 that arrive at the corresponding the inputs of element 13I. With the arrival of the tenth pulse, the counting decade is set to state O, and the output of element 12 OR-NOT is signal 1, which is fed to the input of element 13 I. At the output of element 13, AND signal 1 cat ing for the unit 1 input in the flip-flop 14 and causes the signal on occurrence of 1-forward output of this flip-flop. The signal 1 from the forward output of the trigger 14 is inverted by the element 15 NOT and the signal O already arrives at the second input of the element 17 AND, since the trigger 14 is set to state 1., therefore, the O signal appears at the inverse of its output at least 16 delay. The delay element 16 has a time delay 1 o therefore the signal 1 delayed by two cycles from the inverse output of the trigger 14 arrives at the first input of the element 17 And then when its second input in the absence of constant faults in the counting decade, the signal O does not come from the output of the element 15 consequently, at the output of element 17, a signal O appears, which through element 18 OR is fed to the input R of trigger 3 and keeps it in the enable state, the generator 2 does not turn off,; The time delay of element 16 is not critical to the upper limit; it can be greater than or equal to the expression / i, which greatly simplifies its choice. For example, if the test is performed by generator 2 with a frequency of 1 MHz, then in order to check the counting decade for the absence of constant faults, it is sufficient to use a delay element with characteristic

2 10 zhch-000-OOO- 0.00002 s. The check time of the counters is determined by the required number of check cycles and the pulse frequency of the generator 2, so, when the pulse frequency of the generator is 1 MHz, 1 000 000 check cycles are performed per second.

If there is a malfunction of the decades, the signal at the output of one of the counting decades is different in amplitude or phase from the signals on the same outputs of the remaining counting decades. In this case, at the output of the equivalent element 6, the signal O appears, therefore, at the output of element 5, an IS signal is NOT, which is through element 18 OR arrives at the installation input into the O of the trigger 3 and sets it to the state prohibiting further passage of the generator pulses 2 through element 1 And, as a result, a signal 1 appears at the inverse output of trigger 3, signaling the presence of a fault in the counting decades.

In the case when constant faults (const O or const 1) of the counters occur on the same output of the checked counting decades, the device detects them using triggers 8-11 (faults of the const type 0) or element 12 OR-NOT (faults of the const 1 type ).

Let the O signal be permanently present at one of the same outputs of checked counting decades, regardless of the algorithm of their operation, in this case one of the triggers 8-11 corresponding to the fault location does not go to state 1 for the first two check cycles, therefore, element outlet

13A signal O is always present, on the inverse of the trigger output

14- signal 1, and on its direct output signal O, resulting in time 1; element output

17 And a signal 1 appears, which through element 18 OR enters the installation of the trigger 3 and sets it to the state prohibiting the passage of pulses from generator 2 through element 1 AND, and the inverse output of trigger 3 gives a signal that there is a fault . Similarly, the device works if signal 1 is permanently present at one of the outputs of the same number of countable decades tested, in this case, the output of element 12 OR is NOT constant signal of O, therefore, at the output of element 13 AND the signal of O as given the algorithm prevents the passage of pulses from generator 2 through element 1 AND,

The proposed device can be used without any changes to verify the performance of various counters, distributors, etc., since the verification process consists in a search for the amplitude and phase of deliberately unambiguous output signals of the monitored devices and does not depend on the algorithm of operation of these devices.

Thus, the introduction of new design features into a device allows one to expand its functionality, i.e. in addition, you will see constant faults.

GE

18

No. |

Claims (1)

DEVICE FOR CHECKING COUNTERS, containing m groups of data and information buses, h equivalence elements, AND element, pulse generator, first AND element, first trigger and control bus, which is connected to the installation input in 1 of the first trigger, the direct output of which is connected to the first input of the first element And, the second input and the output of which are connected respectively with the output of the pulse generator and with the output clock bus, the inputs of each element of equivalence are connected with the same information buses of each of the m groups of information bus lines, the outputs of the equivalence elements are connected to the input of the Y-NOT element, characterized in that, in order to expand the functionality, an OR element, an OR-HE element, a second, a third AND element, a NOT element, a delay element, a second trigger are introduced into it and η additional triggers, the inputs of the installation at 0 of which are connected to the input of the installation at 0 of the second trigger and the control bus, the input of the installation to 1 of each of the additional triggers is connected to the corresponding information bus of one of the ¼ groups of information buses with the corresponding Leica Geosystems input of OR-NO element whose output is connected to a first input of the second AND element, the other inputs _of which are connected to the corresponding $ stvuyuschimi η additional direct outputs of flip-flops, the output of second AND input is connected to a setting of 1 second trigger, direct and inverse outputs which are connected respectively to the inputs of the element NOT and the delay element, the outputs of which are connected to the inputs of the third element AND, the output of which is connected to the first input of the OR element, the second input and output of which is connected respectively with Odom AND-NO element and to the input, setting CV "0 first trigger. ~ SU «„ 1099388 I>