CN100337404C - Crystal oscillation duplicaltion and its duplicating circuit - Google Patents
Crystal oscillation duplicaltion and its duplicating circuit Download PDFInfo
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- CN100337404C CN100337404C CNB2004100494968A CN200410049496A CN100337404C CN 100337404 C CN100337404 C CN 100337404C CN B2004100494968 A CNB2004100494968 A CN B2004100494968A CN 200410049496 A CN200410049496 A CN 200410049496A CN 100337404 C CN100337404 C CN 100337404C
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Abstract
The present invention relates to a crystal oscillation backup circuit which comprises a crystal oscillation output detection circuit and a clock source switching circuit. The crystal oscillation output detection circuit detects whether the operating states of a first crystal oscillation and a second crystal oscillation are normal or not by utilizing output clocks of the two crystal oscillations which are in mutual backup, and outputs a first crystal oscillation clock detection state signal and a second crystal oscillation clock detection state signal. The clock source switching circuit receives the first crystal oscillation clock detection state signal and the second crystal oscillation clock detection state signal, and automatically switches a clock source according to the variation of the two state signals, and the crystal oscillation with the normal operating state is used as the current clock source. The present invention also provides a crystal oscillation backup method. The present invention can reduce the influence on a system by crystal oscillation fault, the reliability of the system is enhanced, the whole module backup is avoided, and the cost is reduced. The present invention does not introduce the third clock when in clock detection, and the independence and the reliability of the detection are guaranteed.
Description
Technical field
The present invention relates to communicate by letter or the clock technology of electronic applications, refer to a kind of method and circuit of crystal oscillator backup especially.
Background technology
In communication system, clock is vital, and various controls, transfer of data all be unable to do without clock.The work of CPU relies on clock fully, if there is not clock, it will quit work.For CPU provides the crystal oscillator in work clock source is a kind of high failure rate device (common failure rate is about 100FIT, the failure rate of some crystal oscillator even reach hundreds of FIT), and its fault inevitably can cause control system not work.Some pith of communication system requires can long-term stable operation, and the high failure rate of crystal oscillator can not meet this requirement.Therefore, must take other means, avoid the fault of crystal oscillator that system is caused significant impact.
Usually can adopt the method for Redundancy Design for important module, avoid some faults that system is caused significant impact.The common practices of Redundancy Design is: adopt identical two unit to realize to important module, one is the main module of using, in running order, another is a spare module, do not participate in real work, but state and master are consistent with module, when the master uses module failure, spare module is taken over job at once, reduces the influence of fault.
By this Redundancy Design, can avoid the fault of crystal oscillator fault and other circuit to cause system significant problem to occur.
The shortcoming of prior art: adopt two identical modules to back up, two modules are only finished the function of a module, and cost is very high, and technical sophistication.Except crystal oscillator, the module that other component failure rate is not high adopts this method to waste very much for some.
In addition, in the control switching circuit of module, need the clock of crystal oscillator is detected, this detection need provide a clock in addition, and the reliability of this clock can't might cause the testing result mistake owing to detect the fault of clock than detected clock height.
Summary of the invention
The invention provides a kind of crystal oscillator backup method and circuit, to solve cost height that exists in the prior art and the problem that causes the testing result mistake easily.
A kind of crystal oscillator backup method comprises the following steps:
A) two of designs can mutually redundant first crystal oscillator and second crystal oscillator;
B) utilize the output clock of first crystal oscillator and second crystal oscillator to detect described first crystal oscillator mutually and whether the second crystal oscillator operating state is normal;
C) in described first crystal oscillator and second crystal oscillator, select the normal crystal oscillator of an operating state as system clock source.
Whether normal method is to detect the first crystal oscillator operating state among the described step B:
The output clock of first crystal oscillator is input to the clear terminal of first counter, and the output clock of second crystal oscillator is input to the clock end of first counter after anti-phase through first not gate, and the carry end of first counter is connected to first or an input of door;
The output clock of first crystal oscillator is input to the clear terminal of second counter after anti-phase through second not gate, the output clock of second crystal oscillator is input to the clock end of second counter, and the carry end of second counter is connected to first or another input of door;
When first or the output signal of door when being fixed as low level, represent that first crystal oscillator is working properly; When first or the output signal of door when being pulse signal, represent that the first crystal oscillator work is undesired.
Whether normal method is to detect the second crystal oscillator operating state among the described step B:
The output clock of second crystal oscillator is input to the clear terminal of the 3rd counter, and the output clock of first crystal oscillator is input to the clock end of the 3rd counter after anti-phase through the 3rd not gate, and the carry end of the 3rd counter is connected to second or an input of door;
The output clock of second crystal oscillator is input to the clear terminal of four-counter after anti-phase through the 4th not gate, the output clock of first crystal oscillator is input to the clock end of four-counter, and the carry end of four-counter is connected to second or another input of door;
When second or the output signal of door when being fixed as low level, represent that second crystal oscillator is working properly; When second or the output signal of door when being pulse signal, represent that the second crystal oscillator work is undesired.
A kind of crystal oscillator fallback circuit comprises:
The crystal oscillator output detection circuit: whether normal, and export the first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal if utilizing the output clock of mutually redundant first crystal oscillator and second crystal oscillator to detect the operating state of described first crystal oscillator and second crystal oscillator mutually;
Clock source commutation circuit: receive the above-mentioned first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal, according to the situation of change automatic switchover clock source of two status signals, with the normal crystal oscillator of operating state as the present clock source.
Described crystal oscillator fallback circuit also includes a crystal oscillator condition indication circuit, in order to indicate the current crystal oscillator that breaks down.
Described crystal oscillator output detection circuit comprises the first crystal oscillator testing circuit and the second crystal oscillator testing circuit;
The described first crystal oscillator testing circuit comprises first and second logic inverters, first and second counters and first or door; Wherein
The output clock of first crystal oscillator is input to the clear terminal of first counter, and the output clock of second crystal oscillator is input to the clock end of first counter after anti-phase through first not gate, and the carry end of first counter is connected to first or an input of door;
The output clock of first crystal oscillator is input to the clear terminal of second counter after anti-phase through second not gate, the output clock of second crystal oscillator is input to the clock end of second counter, and the carry end of second counter is connected to first or another input of door; First or the door output signal be the first crystal oscillator clock detection status signal;
The described second crystal oscillator testing circuit comprises third and fourth logic inverter, third and fourth counter and second or door; Wherein
The output clock of second crystal oscillator is input to the clear terminal of the 3rd counter, and the output clock of first crystal oscillator is input to the clock end of the 3rd counter after anti-phase through the 3rd not gate, and the carry end of the 3rd counter is connected to second or an input of door;
The output clock of second crystal oscillator is input to the clear terminal of four-counter after anti-phase through the 4th not gate, the output clock of first crystal oscillator is input to the clock end of four-counter, and the carry end of four-counter is connected to second or another input of door; Second or the door output signal be the second crystal oscillator clock detection status signal.
Described clock source commutation circuit comprises:
A T trigger, first NAND gate and two alternative selectors; Wherein
The first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal are input to two inputs of described first NAND gate, and the output of described first NAND gate is connected to the T end of T trigger;
The first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal are input to two inputs of the first alternative selector, the output signal of T trigger is input to the selecting side of the first alternative selector, and the output of the first alternative selector is connected to the clock end of T trigger;
The output clock of first crystal oscillator and the output clock of second crystal oscillator are input to two inputs of the second alternative selector, the output signal of T trigger is input to the selecting side of the second alternative selector, is system clock with the output signal of this second alternative selector.
Described crystal oscillator condition indication circuit comprises:
Two d type flip flops and one second NAND gate;
The reset signal of system and crystal oscillator fault clearance signal are input to two inputs of described second NAND gate, and the output of described second NAND gate is connected to the clear terminal of two d type flip flops;
The clock end of two d type flip flops connects the clock detection status signal of first crystal oscillator and second crystal oscillator respectively; The D of two d type flip flops end connects high level respectively, and the output of two d type flip flops " 0 " or " 1 " are represented that respectively first crystal oscillator and second crystal oscillator are working properly or broken down.
The present invention adopts direct crystal oscillator backup method, has reduced the influence of crystal oscillator fault to system, has improved the reliability of system, and its reliability index and module backup are quite.And avoided whole module is backed up, reduced cost.Because the clock detection part is not introduced the 3rd clock, the independence and the reliability that detect have been guaranteed.
Description of drawings
Fig. 1 is the output clock detection circuit of crystal oscillator A in the embodiment of the invention.
Fig. 2 is the output clock detection circuit of crystal oscillator B in the embodiment of the invention.
Fig. 3 is the clock source commutation circuit in the embodiment of the invention.
Fig. 4 is the sequential chart of circuit shown in Figure 3 each signal when the switching of clock source takes place.
Fig. 5 is the crystal oscillator condition indication circuit in the embodiment of the invention.
Embodiment
The present invention adopts two identical crystal oscillators of model (crystal oscillator A and crystal oscillator B) crystal oscillator that backups each other, and selects crystal oscillator wherein working properly clock source as CPU (system).Its physical circuit can adopt programmable logic device to realize.The failure rate of programmable logic device is about 40FIT, suitable with the failure rate of interface devices such as 71LS244, so adopt this crystal oscillator backup mode and adopt reliability index that module backup institute can reach substantially quite (module backs up and need communicate by interface devices such as 71LS244, and interface device directly influences the reliability of active/standby module).
Crystal oscillator fallback circuit of the present invention comprises: crystal oscillator output detection circuit, clock source commutation circuit and crystal oscillator condition indication circuit.The crystal oscillator output detection circuit detects the output clock of two crystal oscillators, the clock detection status signal of two crystal oscillators of output; Clock source commutation circuit is carried out clock source switching controls according to the detected state signal of testing circuit output; The crystal oscillator condition indication circuit makes system can promptly and accurately obtain the state of clock and crystal oscillator for CPU provides the indication of crystal oscillator state, is convenient to failure location and system maintenance.
Below be specifying of each circuit:
Referring to Fig. 1, among Fig. 1
CLKA: the clock of crystal oscillator A output;
CLKB: the clock of crystal oscillator B output;
LOSSA: the clock detection status signal of crystal oscillator A, low level represent that clock is normal, pulse output expression crystal oscillator A clock failure.
Comprise among Fig. 1 two two binary counters, two not gates and one or.
The output clock CLKA of crystal oscillator A is connected to the clear terminal (being referred to as first counter for convenience of description) of two binary counters; Be connected to the clock end of this first counter after the output clock CLKB process not gate of crystal oscillator B is anti-phase; The carry end of this first counter be connected to or the door an input.
Be connected to the clear terminal (being referred to as second counter for convenience of description) of another two binary counters after the output clock CLKA process not gate of crystal oscillator A is anti-phase; The output clock CLKB of crystal oscillator B is connected to the clock end of this second counter; The carry end of this second counter be connected to or the door another input.
Or the output signal of door is the clock detection status signal LOSSA of crystal oscillator A.
By circuit shown in Figure 1 as can be known, when crystal oscillator A was working properly, LOSSA was fixing low level; And when crystal oscillator A broke down, its performance was not have clock output, and output signal is fixing high level or low level, at this moment, one of two counters in the circuit just can or not overflow by the periodicity zero clearing, produce the carry pulse signal, and LOSSA can output pulse signal.
Other sees also Fig. 2, and wherein LOSSB is the clock detection status signal of crystal oscillator B, and low level represents that crystal oscillator B is normal, pulse output expression crystal oscillator B clock failure.Its operation principle no longer repeats as hereinbefore.
By the crystal oscillator output detection circuit of above-mentioned Fig. 1 and Fig. 2 as can be known, when whether the present invention normally detects the output clock of crystal oscillator A and crystal oscillator B, do not adopt the 3rd clock, thereby can avoid because the fault of the 3rd clock causes the mistake that detects.The present invention is the method that adopts CLKA and CLKB to detect mutually, realizes the detection to clock failure.The possibility of CLKA and CLKB simultaneous faults is minimum, therefore, does not consider this situation in the present invention.
Clock of the present invention source commutation circuit as shown in Figure 3.This part comprises two alternative selectors, a NAND gate and a T trigger.
The clock detection status signal LOSSA of crystal oscillator A and crystal oscillator B and LOSSB are input to two inputs of NAND gate, and the output of NAND gate is connected to the T end of T trigger.
The output of T trigger is exactly the selection signal SELECT that is used to select clock output.
LOSSA and LOSSB are input to 0 and 1 input of an alternative selector respectively, and the SELECT signal connects S (selection) end of this selector, and the output of this selector connects the clock end of T trigger.
CLKA and CLKB are respectively as 0 and 1 input of another alternative selector, and the SELECT signal connects the S end of this selector, selects CLKA output when SELECT be ' 0 ', select CLKB to export for ' 1 ' time; And control the input clock of T trigger simultaneously, and select the clock input of LOSSA for ' 0 ' time as the T trigger, select the clock input of LOSSB for ' 1 ' time as the T trigger.CLKOUT is a work clock of exporting to CPU in the circuit.
According to this circuit, when CLKA and CLKB all just often, LOSSA and LOSSB are " 0 ",, the T end of T trigger is " 1 ", allows the trigger output hopping, promptly allows the clock source to switch.Suppose that Q end (being SELECT) is output as " 0 ", promptly select CLKA output, and select the clock input of LOSSA as the T trigger.When the CLKA fault, according to the testing circuit result of above-mentioned crystal oscillator A, LOSSA can become periodic pulse signal by original " 0 "; When saltus step from " 0 " to " 1 " appearred in LOSSA, the output Q of T trigger can become " 1 " from original " 0 ", has just selected normal CLKB to export as clock this moment so, and selects LOSSB to import as the clock of T trigger.When the Q of T trigger end (being SELECT) when being " 1 " originally, process and top description are similar.
Therefore, this clock source commutation circuit can determine whether the output clock is switched according to the clock detection status signal LOSSA of crystal oscillator A and crystal oscillator B and the variation of LOSSB.The condition of switching is to have a clock normal among CLKA and the CLKB, and current output clock failure.Except finishing handoff functionality, the output clock does not produce the burst pulse less than half clock cycle in the time of also will guaranteeing to switch.Because burst pulse output is equivalent to add a burr on the CPU work clock, some registers are made a mistake, cause unpredictable consequence.Therefore, should satisfy during the work of this clock source commutation circuit: when certain road clock output fixing ' 0 ' time, switch at the low level place of another road clock; When the output of certain road clock fixing ' 1 ' time, switch at the high level place of another road clock.So just can avoid the formation of burst pulse.Guarantee that by LOSSA and the LOSSB signal that above-mentioned testing circuit provides the counter O reset signal in the testing circuit of the present invention and the cooperation at counting clock edge have reached this purpose switching time.When CLKA output continues low level, CLKB can only realize with trailing edge the detection of CLKA, do not work in the rising edge test section, therefore have only after the trailing edge of CLKB detects the fault of CLKA, switch to CLKB immediately, and this moment, CLKB was in low level state, not the burst pulse that can occur switching.In like manner, when CLKA continues high level, have only the rising edge of CLKB that CLKA is detected, and when the high level of CLKB, switch clock.Detection when CLKB continues low level or high level is identical with the switching controls principle, repeats no more.The simulation waveform that switch in clock source when CLKA continues low level and high level as shown in Figure 4.
Fig. 5 is a crystal oscillator condition indication circuit of the present invention.Wherein
STATEA: the condition indicative signal of crystal oscillator A, ' 0 ' expression crystal oscillator A is normal, ' 1 ' expression crystal oscillator A fault;
STATEB: the condition indicative signal of crystal oscillator B, ' 0 ' expression crystal oscillator B is normal, ' 1 ' expression crystal oscillator B fault;
RESET: systematic reset signal, low level resets, and the condition indicative signal STATEA of crystal oscillator A and the condition indicative signal STATEB of crystal oscillator B are changed to ' 0 ';
CLEAR: crystal oscillator malfunction clear signal, low level is removed malfunction.
This circuit comprises d type flip flop and NAND gate of two band clear terminals.
Systematic reset signal and crystal oscillator fault clearance signal are input to the input of NAND gate, and the clear terminal of two d type flip flops is received in the output of NAND gate.
The high level that the D termination of two d type flip flops is fixing.
The clock end of two d type flip flops connects LOSSA and LOSSB signal respectively, and the Q end of two d type flip flops is respectively the condition indicative signal STATEA and the STATEB of crystal oscillator.
The course of work of foregoing circuit is: when system reset or outside send when removing the crystal oscillator malfunction by CLEAR, STATEA and STATEB are changed to ' 0 '; When CLKA broke down, LOSSA was a pulse signal, made the D end signal of d type flip flop be delivered to the Q end at its rising edge, and the STATEA signal becomes ' 1 '; When CLKB broke down, LOSSB was a pulse signal, made the D end signal of d type flip flop be delivered to the Q end at its rising edge, and the STATEB signal becomes ' 1 '; CPU can know by reading SELECT which current selected work clock is by reading the state that STATEA and STATEB obtain clock.After STATEA, STATEB signal become " 1 ", remove this two Reflectors if desired, only need make CLEAR end input low level from external input signal.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (8)
1, a kind of crystal oscillator backup method comprises the following steps:
A) two of designs can mutually redundant first crystal oscillator and second crystal oscillator;
B) utilize the output clock of first crystal oscillator and second crystal oscillator to detect described first crystal oscillator mutually and whether the second crystal oscillator operating state is normal;
C) in described first crystal oscillator and second crystal oscillator, select the normal crystal oscillator of an operating state as system clock source.
2, crystal oscillator backup method as claimed in claim 1 is characterized in that: whether normal method is to detect the first crystal oscillator operating state among the described step B:
The output clock of first crystal oscillator is input to the clear terminal of first counter, and the output clock of second crystal oscillator is input to the clock end of first counter after anti-phase through first not gate, and the carry end of first counter is connected to first or an input of door;
The output clock of first crystal oscillator is input to the clear terminal of second counter after anti-phase through second not gate, the output clock of second crystal oscillator is input to the clock end of second counter, and the carry end of second counter is connected to first or another input of door;
When first or the output signal of door when being fixed as low level, represent that first crystal oscillator is working properly; When first or the output signal of door when being pulse signal, represent that the first crystal oscillator work is undesired.
3, crystal oscillator backup method as claimed in claim 1 is characterized in that: whether normal method is to detect the second crystal oscillator operating state among the described step B:
The output clock of second crystal oscillator is input to the clear terminal of the 3rd counter, and the output clock of first crystal oscillator is input to the clock end of the 3rd counter after anti-phase through the 3rd not gate, and the carry end of the 3rd counter is connected to second or an input of door;
The output clock of second crystal oscillator is input to the clear terminal of four-counter after anti-phase through the 4th not gate, the output clock of first crystal oscillator is input to the clock end of four-counter, and the carry end of four-counter is connected to second or another input of door;
When second or the output signal of door when being fixed as low level, represent that second crystal oscillator is working properly; When second or the output signal of door when being pulse signal, represent that the second crystal oscillator work is undesired.
4, a kind of crystal oscillator fallback circuit is characterized in that comprising:
The crystal oscillator output detection circuit: whether normal, and export the first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal if utilizing the output clock of mutually redundant first crystal oscillator and second crystal oscillator to detect the operating state of described first crystal oscillator and second crystal oscillator mutually;
Clock source commutation circuit: receive the above-mentioned first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal, according to the situation of change automatic switchover clock source of two status signals, with the normal crystal oscillator of operating state as the present clock source.
5, crystal oscillator fallback circuit as claimed in claim 4 is characterized in that: also include a crystal oscillator condition indication circuit, in order to indicate the current crystal oscillator that breaks down.
6, as claim 4 or 5 described crystal oscillator fallback circuits, it is characterized in that: described crystal oscillator output detection circuit comprises the first crystal oscillator testing circuit and the second crystal oscillator testing circuit;
The described first crystal oscillator testing circuit comprises first and second logic inverters, first and second counters and first or door; Wherein
The output clock of first crystal oscillator is input to the clear terminal of first counter, and the output clock of second crystal oscillator is input to the clock end of first counter after anti-phase through first not gate, and the carry end of first counter is connected to first or an input of door;
The output clock of first crystal oscillator is input to the clear terminal of second counter after anti-phase through second not gate, the output clock of second crystal oscillator is input to the clock end of second counter, and the carry end of second counter is connected to first or another input of door; First or the door output signal be the first crystal oscillator clock detection status signal;
The described second crystal oscillator testing circuit comprises third and fourth logic inverter, third and fourth counter and second or door; Wherein
The output clock of second crystal oscillator is input to the clear terminal of the 3rd counter, and the output clock of first crystal oscillator is input to the clock end of the 3rd counter after anti-phase through the 3rd not gate, and the carry end of the 3rd counter is connected to second or an input of door;
The output clock of second crystal oscillator is input to the clear terminal of four-counter after anti-phase through the 4th not gate, the output clock of first crystal oscillator is input to the clock end of four-counter, and the carry end of four-counter is connected to second or another input of door; Second or the door output signal be the second crystal oscillator clock detection status signal.
7, crystal oscillator fallback circuit as claimed in claim 6 is characterized in that: described clock source commutation circuit comprises:
A T trigger, first NAND gate and two alternative selectors; Wherein
The first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal are input to two inputs of described first NAND gate, and the output of described first NAND gate is connected to the T end of T trigger;
The first crystal oscillator clock detection status signal and the second crystal oscillator clock detection status signal are input to two inputs of the first alternative selector, the output signal of T trigger is input to the selecting side of the first alternative selector, and the output of the first alternative selector is connected to the clock end of T trigger;
The output clock of first crystal oscillator and the output clock of second crystal oscillator are input to two inputs of the second alternative selector, the output signal of T trigger is input to the selecting side of the second alternative selector, is system clock with the output signal of this second alternative selector.
8, crystal oscillator fallback circuit as claimed in claim 7 is characterized in that: described crystal oscillator condition indication circuit comprises:
Two d type flip flops and one second NAND gate;
The reset signal of system and crystal oscillator fault clearance signal are input to two inputs of described second NAND gate, and the output of described second NAND gate is connected to the clear terminal of two d type flip flops;
The clock end of two d type flip flops connects the clock detection status signal of first crystal oscillator and second crystal oscillator respectively; The D of two d type flip flops end connects high level respectively, and the output of two d type flip flops " 0 " or " 1 " are represented that respectively first crystal oscillator and second crystal oscillator are working properly or broken down.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100494968A CN100337404C (en) | 2004-06-24 | 2004-06-24 | Crystal oscillation duplicaltion and its duplicating circuit |
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| CNB2004100494968A CN100337404C (en) | 2004-06-24 | 2004-06-24 | Crystal oscillation duplicaltion and its duplicating circuit |
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| CN1713527A CN1713527A (en) | 2005-12-28 |
| CN100337404C true CN100337404C (en) | 2007-09-12 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103399808B (en) * | 2013-06-06 | 2016-05-04 | 北京航天自动控制研究所 | A kind of method that realizes the two redundancies of crystal oscillator in flight control computer |
| CN103973996B (en) * | 2014-05-05 | 2017-06-23 | 中国科学院长春光学精密机械与物理研究所 | A kind of clock circuit standby system of many imaging band systems of space camera |
| WO2016119139A1 (en) * | 2015-01-28 | 2016-08-04 | Texas Instruments Incorporated | Fault detection and self-recovery method for crystal oscillator |
| CN107390045B (en) * | 2017-06-16 | 2023-03-14 | 宗仁科技(平潭)有限公司 | Crystal oscillator detection circuit and crystal oscillator detection method |
| CN108563283B (en) * | 2017-12-25 | 2021-05-18 | 中国航空工业集团公司洛阳电光设备研究所 | Real-time clock monitoring and system awakening device |
| CN109729235B (en) * | 2019-01-03 | 2021-05-14 | 威创集团股份有限公司 | Clock backup circuit in video processor and video processor |
| CN111833799B (en) * | 2019-04-15 | 2022-04-05 | 杭州海康威视数字技术股份有限公司 | LED receiving assembly and receiving card switching method |
| CN110413041B (en) * | 2019-07-29 | 2020-11-17 | 珠海零边界集成电路有限公司 | Chip clock circuit and control method thereof |
| CN111614319A (en) * | 2020-04-29 | 2020-09-01 | 杭州拓深科技有限公司 | Combined crystal oscillator switching method suitable for humid environment |
| CN113448381B (en) * | 2021-05-28 | 2023-02-28 | 山东英信计算机技术有限公司 | CPLD working clock keeping method, system, storage medium and device |
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| JPH02278401A (en) * | 1989-04-20 | 1990-11-14 | Toyota Motor Corp | On-vehicle electronic controller |
| US5416443A (en) * | 1993-12-22 | 1995-05-16 | International Business Machines Corporation | Reliable clock source having a plurality of redundant oscillators |
| CN2582276Y (en) * | 2002-07-24 | 2003-10-22 | 深圳市中兴通讯股份有限公司 | Phase-locked loop circuit |
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|---|---|---|---|---|
| GB2109195A (en) * | 1981-10-13 | 1983-05-25 | Standard Telephones Cables Ltd | Clock pulse generator |
| JPH02278401A (en) * | 1989-04-20 | 1990-11-14 | Toyota Motor Corp | On-vehicle electronic controller |
| US5416443A (en) * | 1993-12-22 | 1995-05-16 | International Business Machines Corporation | Reliable clock source having a plurality of redundant oscillators |
| CN2582276Y (en) * | 2002-07-24 | 2003-10-22 | 深圳市中兴通讯股份有限公司 | Phase-locked loop circuit |
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