CN1302358C - Resettnig method of bridging chip and apparatus thereof - Google Patents
Resettnig method of bridging chip and apparatus thereof Download PDFInfo
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- CN1302358C CN1302358C CNB031366198A CN03136619A CN1302358C CN 1302358 C CN1302358 C CN 1302358C CN B031366198 A CNB031366198 A CN B031366198A CN 03136619 A CN03136619 A CN 03136619A CN 1302358 C CN1302358 C CN 1302358C
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Abstract
The present invention relates to a resetting method and an apparatus for a bridging chip, which has the kernel that when the bridging chip connected to a compact peripheral component interconnection (Compact PCI) bus needs resetting, firstly, a data transmission process of the bridging chip is interrupted via an interrupt signal, and then, a reset signal is sent to the bridging chip for corresponding reset processing. Thus, the present invention can effectively avoid the dead halt of the Compact PCI bus caused by the abnormal data transmission between the bridging chip and other component when the bridging chip receives a reset instruction and carries out reset processing, and the dead halt of the Compact PCI bus can affect the data communication process of the whole communication system.
Description
Technical field
The present invention relates to data communication technology field, relate in particular to a kind of repositioning method and device thereof of bridging chip.
Background technology
In present data communication technology field, interconnected between inner each chip of the veneer of data communications equipment by PCI (external unit is interconnected) bus, then be to be connected to each other between each veneer by CompactPCI (compact external unit is interconnected) bus.For veneer and the external unit of realizing data communications equipment inside carries out data communication, then need to carry out the pci bus and the CompactPCI bus of data communications equipment interconnected, currently used mutual contact mode is for being provided with bridging chip between pci bus and CompactPCI bus, by the data communication between the veneer of bridging chip realization data communications equipment, each chip that is veneer inside is successively by self pci bus, bridging chip, and each chip of the pci bus of each chip of other veneer inside, bridging chip and other veneer inside is realized data communication.
Described bridging chip comprises two pci bus interfaces, is respectively primary side pci bus interface and secondary side pci bus interface.Wherein, the primary side pci bus interface links to each other with the CompactPCI bus, the secondary side pci bus interface links to each other with the pci bus of veneer inside, as shown in Figure 1, bridging chip provides the CompactPCI bus side in the data communications equipment and the bridging functionality of veneer internal pci bus side, thereby realizes the data communication between different veneers.
Information interaction between the inner different veneers of data communications equipment realizes by bridging chip separately, as shown in Figure 2.When some veneers in data communications equipment when artificial or odjective cause need reset because of certain, if this bridging chip does not carry out data communication with other equipment, then reset operation can not cause harmful effect to the CompactPCI bus, but, if the bridging chip that carries out data communication is resetted, then may cause on the CompactPCI bus, producing unusual sequential, and this unusual sequential causes the confusion of other bridging chip states on the CompactPCI bus probably, it is dead further to cause the CompactPCI bus to be hung, and can't carry out data communication.
Now the above-mentioned dead reason of CompactPCI bus extension that may cause is described further in conjunction with Fig. 2, referring to Fig. 2, if bridging chip A carries out data communication by CompactPCI bus and bridging chip B, when data transmission is carried out, if extraneous reset signal resets bridging chip A, the state that then might cause bridging chip B takes place unusual, make signal sequence on the CompactPCI bus not meet definition in the bus specification, and then have influence on the operate as normal of other PCI equipment on same the bus.If do not have data transmission between bridging chip A and the bridging chip B, resetting of bridging chip A just can not caused any adverse effect to bus so.According to the pci bus standard, when the reset signal of PCI equipment was effective, this equipment should be in reset mode immediately and itself and bus are isolated, and no matter the current data transmission of whether carrying out.So just might cause the abnormal state of other equipment that communicate with the equipment that is reset, thereby bus is hung extremely that all use the data transmission of this bus all will interrupt.
By foregoing description as can be seen, existing bridging chip repositioning method exists and may cause bus to hang dead problem, and this is can not be received in the middle of data communication process.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the repositioning method and the device thereof that the purpose of this invention is to provide a kind of bridging chip, to avoid when bridging chip is received reset instruction, still existence is being carried out the data of transmission process and is being caused the CompactPCI bus to be hung extremely, influences the normal data communication of whole C ompactPCI bus.
The present invention adopts following scheme to realize for above-mentioned purpose:
The repositioning method of a kind of bridging chip of the present invention comprises:
The bridging chip that definite needs reset, and produce reset signal;
Reset signal is postponed to handle, interrupt the data transmission procedure between this bridging chip and bus simultaneously;
Have no progeny in described data transmission procedure, the reset signal after will handling through delay sends to this bridging chip, and this bridging chip resets.
The described time that reset signal is postponed to postpone in the processing procedure is: greater than a lasting time of bus burst operation.
Data transmission procedure between this bridging chip of described interruption and bus is:
Send look-at-me to veneer CPU (central processing unit), notify this bridging chip to finish dealing with after the ongoing data transmission by veneer CPU, no longer the new data transfer operation of initiating of response.
Describedly send look-at-me to veneer CPU and be:
When this signal is low level, directly export to veneer CPU;
When this signal is high level, then exports high resistant, and export to veneer CPU after moving high level to by external pull-up resistor.
Described look-at-me is for adopting the look-at-me or the non-maskable look-at-me of high priority.
The resetting means of a kind of bridging chip of the present invention comprises:
Reset circuit: produce the reset signal of bridging chip as required, and described reset signal is sent to the reset signal processing module;
Reset signal processing module: the reset signal that receives reset circuit output, described reset signal is postponed to export to bridging chip after the processing, and when receiving reset signal, send the look-at-me that is used to end data transmission procedure between this bridging chip and bus to veneer CPU.
Described reset signal processing module realizes for the electronic circuit that adopts PLD (Programmable Logic Device) or common electron device to form.
Described reset signal processing module comprises:
State machine: be used for determining different state machine state, and reset signal delay process submodule and look-at-me generation submodule carried out control operation according to different state machine state according to the reset signal of the reset circuit output that receives;
Reset signal delay process submodule: the state according to state machine carries out delay process to reset signal, and when not having the data of transmitting between bridging chip and bus, reset signal is sent to bridging chip;
Look-at-me generates submodule: the state according to state machine sends the look-at-me that is used to interrupt data transmission procedure between this bridging chip and bus to veneer CPU, makes bridging chip no longer respond new data transfer operation request.
Described different state machine state comprises: S0, and S1, S2 and S3 be totally 4 states, wherein:
When state machine was in initial S0 state, the reset signal that the reset signal of reset signal delay process submodule output is followed input changed;
When the reset signal of input becomes when invalid, state machine becomes the S1 state from the S0 state;
When the reset signal of input becomes when effective from invalid, state machine becomes the S2 state from the S1 state, and look-at-me generated submodule and exported effective look-at-me this moment;
Behind the delay time of setting, state machine becomes the S3 state from the S2 state, and this moment, look-at-me was invalid;
Through behind the delay time of setting, state machine is got back to the S0 state from the S3 state again, and this moment, reset signal delay process submodule was exported effective reset signal.
Be provided with pull-up resistor between described reset signal processing module and veneer CPU, described pull-up resistor is connected to the input/output voltage end of veneer CPU.
By technical scheme provided by the present invention as can be seen, the present invention is when doing to reset processing to a certain bridging chip in the system, at first the data transmission procedure between this bridging chip and CompactPCI bus is stopped by look-at-me, make this bridging chip no longer respond new data transfer operation request, guarantee the bridging chip ongoing data transmission procedure of finishing dealing with simultaneously, and then carry out reset processing at this bridging chip.Therefore, the present invention can avoid effectively when bridging chip receives that the horizontal reset processing is gone forward side by side in reset instruction, hang extremely because of the unusual CompactPCI bus that causes of other equipment and the ongoing data transmission procedure of this bridging chip, influence the data communication process of total system.
Above-mentioned advantage of the present invention just can clearly be seen that by contrast experiment's result: do not adopt when of the present invention, general bridging chip is reset repeatedly and will hangs dead CompactPCI bus about 30 times, makes other equipment on this bus can't use bus; Adopt after the present invention, making uses the same method resets 10,000 times to bridging chip, and other equipment on the bus still can normally communicate, and are not subjected to any harmful effect.
Description of drawings
Fig. 1 is the application structure synoptic diagram of bridging chip;
Fig. 2 is the application structure synoptic diagram of chip and CompactPCI bus for bridge joint;
Fig. 3 is existing bridging chip reset schemes synoptic diagram;
Fig. 4 is a bridging chip repositioning method process flow diagram provided by the invention;
Fig. 5 is a bridging chip resetting means structural representation provided by the invention;
Fig. 6 is the signal timing diagram of Fig. 5;
Fig. 7 is the syndeton synoptic diagram between reset signal processing module and CPU among Fig. 5;
Fig. 8 is the structural representation of reset signal processing module among Fig. 5.
Embodiment
Core of the present invention is that the reset signal at bridging chip is carried out delay process, can after ongoing data transmission procedure is finished between bridging chip and bus, reset with assurance, thereby avoid influencing normally carrying out of total system data transmission bridging chip.
Now the embodiment to the repositioning method of a kind of bridging chip of the present invention is described further, and as shown in Figure 4, method of the present invention comprises:
Execution in step 1, determine in communication facilities or the communication system and need carry out reset processing a certain bridging chip, the purpose of bridging chip of resetting can be for bridging chip and CompactPCI bus are isolated, and also can be in order to make veneer restart and to reinitialize wherein each chip; The reset signal of needs when for this reason needing execution in step 2 bridging chip to be done to reset processing with generation, reset signal is produced by the reset circuit in the system usually, and described reset circuit is existing application in the prior art, does not repeat them here.
After having possessed the reset signal of step 2 generation, reseting procedure just can enter step 3 shown in Figure 4, step 3 comprises two operations, one is that reset signal is postponed to handle, another is the data transmission procedure that interrupts between this bridging chip and CompactPCI bus, and step 3 also is core of the present invention place;
The described reset signal that reset circuit is produced is carried out the delay process process and is specially: after the time that described reset signal is postponed to continue greater than bus burst operation, send to bridging chip again, guarantee when bridging chip receives reset signal, between bridging chip and CompactPCI bus, there are not the data in the transmission and processing process, transmit the unusual of data to avoid resetting of bridging chip to cause, thereby influence normally carrying out of total system data transmission;
Data transmission procedure between this bridging chip of described interruption and CompactPCI bus is specially: at first send look-at-me to veneer CPU, make this bridging chip finish and bus between after the data transmission and processing of just carrying out, no longer respond the data transfer operation request that other equipment are initiated, to realize the isolation of bridging chip and CompactPCI bus; Be no more than simultaneously the scope of permission for the voltage that guarantees to import veneer CPU, in order to avoid damage veneer CPU, need handle the look-at-me of input veneer CPU, promptly adopt the leakage level open circuit output mode that to realize different voltage chip chamber interconnection comparatively commonly used at present, when look-at-me is low level, directly export to veneer CPU, when look-at-me is high level, then export high resistant, and export to veneer CPU after moving high level to by external pull-up resistor; Also can use the mode of electric resistance partial pressure to solve for achieving the above object, but the value of resistance comparatively bother;
In addition, the look-at-me of input veneer CPU has different priority levels usually, for guaranteeing the reliable response of veneer CPU to look-at-me of the present invention, need to adopt the look-at-me or the non-maskable look-at-me of high priority, for example, in the NMI of X86 series processors (NonMaskable Interrupt, maskable does not interrupt) look-at-me, or the NMI look-at-me of PowerPC series processors and soft reset interrupt signal, so that the timely response of veneer CPU.
After having passed through step 3, there have not been the data transmitted between bridging chip and CompactPCI bus, at this moment, we just can execution in step 4, reset signal after will handling through delay sends to this bridging chip, this bridging chip resets according to the reset signal that receives, thereby not influencing under the situation that whole data communication system data transmission normally carries out, has realized the isolation of this bridging chip and CompactPCI bus.
Based on the described method of the invention described above, the present invention also provides a kind of resetting means of bridging chip, and the structure of this device specifically comprises as shown in Figure 5:
Reset circuit: the reset signal that produces bridging chip according to the needs of communication facilities or data communication system, this reset signal sends to the reset signal processing module, difference with the prior art of the present invention just is in the prior art it is that the reset signal that directly reset circuit is produced sends to bridging chip, and be that the reset signal that reset circuit produces is sent to earlier after the reset signal processing module that increases newly handles in the present invention, send to bridging chip again;
The reset signal processing module: this module receives the reset signal of reset circuit output, export to veneer CPU after this reset signal postponed to handle, and when receiving reset signal, send the look-at-me of the data transmission procedure that is used to interrupt this bridging chip to veneer CPU;
Described reset signal processing module comprises further that also state machine, reset signal delay process submodule and look-at-me generate submodule, wherein:
State machine: be used for determining different state machine state, and reset signal delay process submodule and look-at-me generation submodule carried out control operation according to different state machine state according to the reset signal of the reset circuit output that receives;
Described state machine has S0, and S1, S2 and S3 be totally 4 states, according to the variation of reseting input signal and in these 4 states, change, be initially the S0 state, when state machine was in the S0 state, the reset signal that the reset signal of reset signal delay process submodule output is followed input changed; When the reset signal of input becomes when invalid, state machine becomes the S1 state from the S0 state; When the reset signal of input becomes when effective from invalid, state machine becomes the S2 state from the S1 state, and look-at-me generated submodule and exported effective look-at-me this moment; Behind the delay time of setting, for example 30 milliseconds, state machine becomes the S3 state from the S2 state, and this moment, look-at-me was invalid; Through behind the delay time of setting, for example 30 milliseconds, state machine is got back to the S0 state from the S3 state again, and this moment, reset signal delay process submodule was exported effective reset signal, and the state variation of state machine is referring to shown in Figure 6;
Reset signal delay process submodule: be used for reset signal being carried out exporting to bridging chip after the delay process, when not having the data of transmitting between bridging chip and bus, reset signal sent to bridging chip according to the state of state machine;
Described state machine cooperates the time that time that reset signal is postponed should respond a data transfer operation and finish the transmission course needs greater than bridging chip with reset signal delay process submodule, the concrete selection of time that postpones can be determined according to the data-handling capacity of bridging chip, for example, the buffer zone of certain bridging chip inside has 256 bytes, the data line bandwidth that this bridging chip links to each other with the CompactPCI bus is 64, and the time that then needs reset signal is postponed is greater than 256/ (64/8)=32 clock period;
Look-at-me generates submodule: be used for the state according to state machine, send the look-at-me that is used to interrupt data transmission procedure between this bridging chip and bus to veneer CPU, make bridging chip no longer respond any new data transfer operation request, effectively bridging chip and CompactPCI bus are isolated, guarantee when bridging chip receives reset signal after delay process, between bridging chip and bus, not have the data of transmitting;
Described reset signal processing module can adopt PLD (Programmable Logic Device), PLD has advantages such as volume is little, capacity is big, low in energy consumption, in the circuit design of electronic technology field, had at present comparatively widely and used, usually a slice PLD can realize the function of more middle and small scale logical circuit, and convenient at the flexible design of various functions;
The sequential chart of device of the present invention as shown in Figure 6, as seen from Figure 6, when becoming significant level when the reset signal generation saltus step of exporting to the reset signal processing module by reset circuit, the reset signal processing module sends to generation the look-at-me of veneer CPU simultaneously, the reset signal of exporting to bridging chip then need send look-at-me or perhaps receive the reset signal of reset circuit generation after after time delay after a while, again reset signal is sent to bridging chip, reset signal after bridging chip postpones to handle according to this process is carried out reset processing, among Fig. 6, the processing time of shown Interrupt Process time for bridging chip and CompactPCI bus being isolated by veneer CPU, look-at-me is the effective signal of negative edge, from being the Interrupt Process time after the look-at-me saltus step when the reset signal processing module is exported reset signal, shown time delay receives the reset signal time for the reset signal processing module and bridging chip receives the interval of reset signal between the time;
Certainly, the reset signal processing module described in the present invention also can adopt the corresponding electronic circuit of ordinary electronic designs to realize, for example, wherein the time-delay to reset signal just can realize with a counter;
In addition, the voltage that also needs to guarantee the look-at-me introduced for veneer CPU is complementary with it, otherwise, may cause veneer CPU can't discern look-at-me on the one hand, also may cause the damage of veneer CPU pin on the other hand, for example, the voltage of supposing look-at-me is 3.3V, and the applied signal voltage that veneer CPU can bear is 2.5V, then will cause the damage of veneer CPU behind this look-at-me input veneer CPU owing to input voltage is too high; In order to realize that the reset signal processing module sends to the magnitude of voltage unanimity of the look-at-me of veneer CPU, also need to be provided with pull-up resistor between reset signal processing module described in the present invention and veneer CPU, as shown in Figure 7, described pull-up resistor is connected to the interrupting input end of veneer CPU, when look-at-me is low level, directly export to veneer CPU, when look-at-me is high level, then export high resistant, and export to veneer CPU again move the input/output voltage value of veneer CPU to by described pull-up resistor after, this setting of leaking level open circuit output mode makes veneer CPU can adapt to the look-at-me of different voltages, guarantee all can not to be damaged when veneer CPU pin is introduced the look-at-me of different voltages, and can effectively discern.
Claims (10)
1, a kind of repositioning method of bridging chip is characterized in that comprising:
The bridging chip that definite needs reset, and produce reset signal;
Reset signal is postponed to handle, interrupt the data transmission procedure between this bridging chip and bus simultaneously;
Have no progeny in described data transmission procedure, the reset signal after will handling through delay sends to this bridging chip, and this bridging chip resets.
2, the repositioning method of a kind of bridging chip according to claim 1 is characterized in that the described time that reset signal is postponed to postpone in the processing procedure is: the time that continues greater than bus burst operation.
3, the repositioning method of a kind of bridging chip according to claim 1 is characterized in that the data transmission procedure between this bridging chip of described interruption and bus is:
Send look-at-me to the veneer central processor CPU, notify this bridging chip to finish dealing with after the ongoing data transmission by veneer CPU, no longer the new data transfer operation of initiating of response.
4, the repositioning method of a kind of bridging chip according to claim 3 is characterized in that describedly sending look-at-me to veneer CPU and being:
When this signal is low level, directly export to veneer CPU;
When this signal is high level, then exports high resistant, and export to veneer CPU after moving high level to by external pull-up resistor.
5,, it is characterized in that described look-at-me is for adopting the look-at-me or the non-maskable look-at-me of high priority according to the repositioning method of claim 3 or 4 described a kind of bridging chips.
6, a kind of resetting means of bridging chip is characterized in that comprising:
Reset circuit: produce the reset signal of bridging chip as required, and described reset signal is sent to the reset signal processing module;
Reset signal processing module: the reset signal that receives reset circuit output, described reset signal is postponed to export to bridging chip after the processing, and when receiving reset signal, send the look-at-me that is used to end data transmission procedure between this bridging chip and bus to veneer CPU.
7, the resetting means of a kind of bridging chip according to claim 6 is characterized in that the electronic circuit realization that described reset signal processing module is formed for adopting Programmable Logic Device PLD or electron device.
8, a kind of bridging chip resetting means according to claim 6 is characterized in that described reset signal processing module comprises:
State machine: be used for determining different state machine state, and reset signal delay process submodule and look-at-me generation submodule carried out control operation according to different state machine state according to the reset signal of the reset circuit output that receives;
Reset signal delay process submodule: the state according to state machine carries out delay process to reset signal, and when not having the data of transmitting between bridging chip and bus, reset signal is sent to bridging chip;
Look-at-me generates submodule: the state according to state machine sends the look-at-me that is used to interrupt data transmission procedure between this bridging chip and bus to veneer CPU, makes bridging chip no longer respond new data transfer operation request.
9, a kind of bridging chip resetting means according to claim 8 is characterized in that described different state machine state comprises: S0, and S1, S2 and S3 be one of four states altogether, wherein:
When state machine was in initial S0 state, the reset signal that the reset signal of reset signal delay process submodule output is followed input changed;
When the reset signal of input becomes when invalid, state machine becomes the S1 state from the S0 state;
When the reset signal of input becomes when effective from invalid, state machine becomes the S2 state from the S1 state, and look-at-me generated submodule and exported effective look-at-me this moment;
Behind the delay time of setting, state machine becomes the S3 state from the S2 state, and this moment, look-at-me was invalid;
Through behind the delay time of setting, state machine is got back to the S0 state from the S3 state again, and this moment, reset signal delay process submodule was exported effective reset signal.
10, the resetting means of a kind of bridging chip according to claim 6 is characterized in that being provided with pull-up resistor between described reset signal processing module and veneer CPU, and described pull-up resistor is connected to the input/output voltage end of veneer CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB031366198A CN1302358C (en) | 2003-05-21 | 2003-05-21 | Resettnig method of bridging chip and apparatus thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031366198A CN1302358C (en) | 2003-05-21 | 2003-05-21 | Resettnig method of bridging chip and apparatus thereof |
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| CN1549081A CN1549081A (en) | 2004-11-24 |
| CN1302358C true CN1302358C (en) | 2007-02-28 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103019870A (en) * | 2012-12-14 | 2013-04-03 | 大唐移动通信设备有限公司 | Method and communication equipment for processing reset signal |
| CN105988541A (en) * | 2015-02-06 | 2016-10-05 | 钜泉光电科技(上海)股份有限公司 | Communication resetting method and system for electric energy metering chip |
| CN110008164A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of NTB link management method, system and relevant apparatus |
| CN111400079B (en) * | 2020-03-16 | 2024-03-01 | 上海金卓科技有限公司 | Isolator, and software resetting method, device and storage medium applicable to isolator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5968156A (en) * | 1997-07-25 | 1999-10-19 | Samsung Electronics Co., Ltd. | Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein |
| CN1233799A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | PCI system and adapter requirements foliowing reset |
| CN1234562A (en) * | 1998-05-04 | 1999-11-10 | 国际商业机器公司 | Intensified error handling for I/O loading/storing operation of -PCI apparatus |
-
2003
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5968156A (en) * | 1997-07-25 | 1999-10-19 | Samsung Electronics Co., Ltd. | Programmable peripheral component interconnect (PCI) bridge for interfacing a PCI bus and a local bus having reconstructable interface logic circuit therein |
| CN1233799A (en) * | 1998-04-27 | 1999-11-03 | 国际商业机器公司 | PCI system and adapter requirements foliowing reset |
| CN1234562A (en) * | 1998-05-04 | 1999-11-10 | 国际商业机器公司 | Intensified error handling for I/O loading/storing operation of -PCI apparatus |
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