CN113448381B - CPLD working clock keeping method, system, storage medium and device - Google Patents
CPLD working clock keeping method, system, storage medium and device Download PDFInfo
- Publication number
- CN113448381B CN113448381B CN202110592477.3A CN202110592477A CN113448381B CN 113448381 B CN113448381 B CN 113448381B CN 202110592477 A CN202110592477 A CN 202110592477A CN 113448381 B CN113448381 B CN 113448381B
- Authority
- CN
- China
- Prior art keywords
- signal
- clock
- cpld
- logic
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a CPLD working clock keeping method, a CPLD working clock keeping system, a CPLD working clock keeping storage medium and CPLD working clock keeping equipment, wherein the method comprises the following steps: responding to the starting of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal to a clock monitoring module so as to enable the logic clock signal to monitor the abnormality of a native clock signal in the CPLD based on the logic clock signal; outputting a clock monitoring signal based on a monitoring result through the clock monitoring module; the clock monitoring signal is received by a multiplexer and the logic clock signal or the native clock signal is selected based on the clock monitoring signal and output as the working clock of the CPLD. The invention monitors the abnormal condition of the original clock in the CPLD, and selects the original clock or the preset delay logic module in the CPLD according to the monitoring condition of the clock monitoring module, thereby selecting a normal clock signal to ensure that the CPLD always works normally.
Description
Technical Field
The invention relates to the technical field of CPLD, in particular to a CPLD working clock keeping method, a CPLD working clock keeping system, a CPLD working clock keeping storage medium and CPLD working clock keeping equipment.
Background
Nowadays, the server is designed to be more and more bulky, and the chip that represents various functions is required more and more, such as the chips commonly used by the server, such as CPU, BMC, etc., and these chips have their own required power timing specifications. In the conventional method, a power supply time sequence is designed in a hardware mode, so that the area of a circuit board is increased, and electronic parts for controlling the power supply time sequence are increased; meanwhile, it causes inconvenience that, for example, if the timing of the power is to be adjusted, parts of the circuit board must be modified to adjust the timing of the power. The most commonly used approach today is to use CPLDs instead of power timing on the circuit board. Because the CPLD itself needs to match the clock signal, otherwise the CPLD cannot work normally, such as the control timing of the power supply, the processing of the data buffer, or various protocol function designs, so the clock signal is the entire operation core of the CPLD, if there is no clock signal, the CPLD cannot be realized in the function of the sequential circuit, and the system of the entire server may not have the correct power supply timing because the power supply timing required by each chip cannot be effectively output.
The clock signal source of the CPLD nowadays usually has an external clock circuit and is directly connected to the inside of the CPLD for use, or a clock module provided by the CPLD manufacturer is adopted, for the designer, the clock can be generated by only starting the internal time module and providing the real-time clock to the sequential circuit inside the CPLD for use, but if the clock inside the CPLD is in a problem or the clock of the external circuit is not connected to the CPLD, the CPLD cannot normally work.
Disclosure of Invention
In view of the above, the present invention provides a method, a system, a storage medium and a device for maintaining a working clock of a CPLD, so as to solve the problem that the CPLD cannot work normally due to the occurrence of a problem in an internal clock of the CPLD or the absence of a clock of an external circuit connected to the CPLD in the prior art.
Based on the above purpose, the present invention provides a CPLD working clock keeping method, which includes the following steps:
responding to the starting of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal into a clock monitoring module so as to enable the clock monitoring module to monitor the abnormality of a native clock signal in the CPLD based on the logic clock signal;
outputting a clock monitoring signal based on a monitoring result through a clock monitoring module;
the clock monitoring signal is received by the multiplexer, and the logic clock signal or the native clock signal is selected based on the clock monitoring signal and is output as the working clock of the CPLD.
In some embodiments, inputting the logical clock signal to the clock monitoring module to cause it to monitor for anomalies in the native clock signal within the CPLD based on the logical clock signal includes:
inputting a logic clock signal to a clock monitoring module, and respectively receiving the logic clock signal and a native clock signal through a low level counter and a high level counter of the clock monitoring module;
monitoring, by a low-level counter, whether the native clock signal continues to be a low-level pulse signal for a preset period of time based on the logic clock signal, and monitoring, by a high-level counter, whether the native clock signal continues to be a high-level pulse signal for a preset period of time based on the logic clock signal.
In some embodiments, outputting, by the clock monitoring module, the clock monitoring signal based on the monitoring result includes:
responding to a low-level counter to monitor that a native clock signal is continuously a low-level pulse signal in a preset time period, and outputting a high-level signal through the low-level counter; or
Responding to a native clock signal monitored by a high-level counter to be a high-level pulse signal continuously in a preset time period, and outputting a high-level signal through the high-level counter;
and outputting the high-level signal of the low-level counter or the high-level counter through the clock monitoring module.
In some embodiments, receiving the clock monitor signal by the multiplexer and selecting and outputting the logical clock signal or the native clock signal as the operating clock of the CPLD based on the clock monitor signal comprises:
and receiving the high level signal of the clock monitoring module through the multiplexer, selecting a logic clock signal based on the high level signal and outputting the logic clock signal as the working clock of the CPLD.
In some embodiments, outputting, by the clock monitoring module, the clock monitoring signal based on the monitoring result includes:
and responding to the condition that the low-level counter monitors that the native clock signal does not continuously become a low-level pulse signal in a preset time period and the high-level counter monitors that the native clock signal does not continuously become a high-level pulse signal in the preset time period, and outputting a low-level signal through the clock monitoring module.
In some embodiments, receiving the clock monitor signal by the multiplexer and selecting and outputting the logical clock signal or the native clock signal as the operating clock of the CPLD based on the clock monitor signal comprises:
the low level signal is received by the multiplexer and the native clock signal is selected based on the low level signal and output as the operating clock of the CPLD.
In some embodiments, the delay logic block includes a flip-flop, an inverter, an exclusive-or gate, and a delay buffer.
In another aspect of the present invention, there is also provided a CPLD operating clock holding system, including:
the native clock signal monitoring module is configured for responding to the opening of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal into the clock monitoring module so as to enable the clock monitoring module to monitor the anomaly of the native clock signal in the CPLD based on the logic clock signal;
the clock monitoring signal output module is configured for outputting a clock monitoring signal based on a monitoring result through the clock monitoring module; and
and the working clock selection module is configured for receiving the clock monitoring signal through the multiplexer, selecting a logic clock signal or a native clock signal based on the clock monitoring signal and outputting the logic clock signal or the native clock signal as the working clock of the CPLD.
In yet another aspect of the present invention, there is also provided a computer readable storage medium storing computer program instructions which, when executed, implement any one of the methods described above.
In yet another aspect of the present invention, a computer device is provided, which includes a memory and a processor, the memory storing a computer program, the computer program executing any one of the above methods when executed by the processor.
The invention has at least the following beneficial technical effects:
the invention can provide clock signals for the CPLD by arranging the delay logic module, so that the CPLD does not need to use a clock provided by an external circuit, external hardware is saved, and the area of a circuit board is reduced; by arranging the clock monitoring module, the abnormal condition of the native clock in the CPLD can be monitored; by arranging the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring condition of the clock monitoring module, so that a normal clock signal is selected, and the CPLD can work normally all the time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic diagram of a CPLD operating clock maintaining method according to an embodiment of the present invention;
fig. 2 is a circuit schematic diagram of a CPLD operation clock holding method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a CPLD operating clock keeping system according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a computer-readable storage medium for implementing a CPLD operation clock keeping method according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a hardware structure of a computer device for executing a CPLD operation clock holding method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two non-identical entities with the same name or different parameters, and it is understood that "first" and "second" are only used for convenience of expression and should not be construed as limiting the embodiments of the present invention. Moreover, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements does not include other steps or elements inherent in the present invention.
In view of the foregoing, a first aspect of the embodiments of the present invention provides an embodiment of a CPLD operating clock holding method. Fig. 1 is a schematic diagram illustrating an embodiment of a CPLD operating clock maintaining method according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
step S10, responding to the opening of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal into a clock monitoring module to enable the clock monitoring module to monitor the abnormality of a primary clock signal in the CPLD based on the logic clock signal;
s20, outputting a clock monitoring signal based on a monitoring result through a clock monitoring module;
step S30, receiving the clock monitoring signal through the multiplexer, selecting a logic clock signal or a native clock signal based on the clock monitoring signal, and outputting the selected logic clock signal or the native clock signal as the working clock of the CPLD.
CPLD (Complex Programming Logic Device) represents a Complex programmable Logic Device, and a high-density, high-speed, and low-power programmable Logic Device is constructed by using Programming technologies such as CMOS EPROM, EEPROM, flash memory, and SRAM (static random access memory). The digital integrated circuit is a digital integrated circuit whose logic function can be self-constructed by user according to their respective requirements, and its basic design method is characterized by that it utilizes integrated development software platform, and uses the methods of schematic diagram and hardware description language to produce correspondent target file, and utilizes download cable to transfer the code into target chip to implement designed digital system.
The embodiment of the invention can provide clock signals for the CPLD by arranging the delay logic module, so that the CPLD does not need to use a clock provided by an external circuit, external hardware is saved, and the area of a circuit board is reduced; by arranging the clock monitoring module, the abnormal condition of the native clock in the CPLD can be monitored; by arranging the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring condition of the clock monitoring module, so that a normal clock signal is selected, and the CPLD can work normally all the time.
In some embodiments, inputting the logical clock signal to the clock monitoring module to cause it to monitor for anomalies in the native clock signal within the CPLD based on the logical clock signal includes: inputting a logic clock signal to a clock monitoring module, and respectively receiving the logic clock signal and a native clock signal through a low level counter and a high level counter of the clock monitoring module; monitoring whether the native clock signal continues to be a low-level pulse signal for a preset time period based on the logic clock signal through a low-level counter, and monitoring whether the native clock signal continues to be a high-level pulse signal for the preset time period based on the logic clock signal through a high-level counter.
In some embodiments, outputting, by the clock monitoring module, the clock monitoring signal based on the monitoring result includes: responding to a low-level counter to monitor that a native clock signal is continuously a low-level pulse signal in a preset time period, and outputting a high-level signal through the low-level counter; or responding to the fact that the high-level counter monitors that the original clock signal is continuously a high-level pulse signal in a preset time period, and outputting the high-level signal through the high-level counter; and outputting the high-level signal of the low-level counter or the high-level counter through the clock monitoring module.
In some embodiments, receiving the clock monitor signal by the multiplexer and selecting and outputting the logical clock signal or the native clock signal as the operating clock of the CPLD based on the clock monitor signal comprises: and receiving the high level signal of the clock monitoring module through the multiplexer, selecting a logic clock signal based on the high level signal and outputting the logic clock signal to serve as the working clock of the CPLD.
In some embodiments, outputting, by the clock monitoring module, the clock monitoring signal based on the monitoring result includes: and outputting a low-level signal through the clock monitoring module in response to the low-level counter monitoring that the native clock signal does not continuously become a low-level pulse signal within a preset time period and the high-level counter monitoring that the native clock signal does not continuously become a high-level pulse signal within the preset time period.
In some embodiments, receiving the clock monitor signal by the multiplexer and selecting and outputting the logical clock signal or the native clock signal as the operating clock of the CPLD based on the clock monitor signal comprises: the low level signal is received by the multiplexer and the native clock signal is selected based on the low level signal and output as the operating clock of the CPLD.
In some embodiments, the delay logic block includes a flip-flop, an inverter, an exclusive-or gate, and a delay buffer.
Fig. 2 shows a circuit diagram of the CPLD operation clock holding method. As shown in fig. 2, the delay logic module uses a flip-flop, an inverter, and an xor gate, and is configured with a delay buffer to delay the signal. In the flip-flop, Q is an output pin, which initially jumps from a low level to a high level, meaning that the logic state changes from 0 to 1, so that the Q initially outputs a high level signal, and when the high level signal passes through an inverter (i.e., not gate), the high level signal changes into a low level signal and is input to a D pin of the flip-flop. The signal (assumed as the first signal) received by the xor gate and not passing through the delay buffer is a high level signal, the high level signal of the xor gate and needing to pass through the delay buffer is not received yet, and the delay buffer outputs a low level signal to the xor gate in an initial state, so that the xor gate receives two different signals initially, and outputs a high level signal, thereby triggering the flip-flop. The Q pin of the flip-flop outputs the low level signal of the D pin, the XOR gate receives the low level signal as a first signal, and the initial high level signal reaches the XOR gate, so that the XOR gate receives two different signals and outputs the high level signal to the flip-flop so as to trigger the flip-flop. Thus, the delay logic module will output high and low signals continuously. The delay buffer may set a delay time or a delay frequency according to a frequency of a clock signal to be output by the delay logic block. Therefore, by the delay buffer, the xor gate can always receive two signals with different levels (logically representing 0 and 1), so as to output a high level signal (logically representing 1) to trigger the flip-flop to operate.
As shown in fig. 2, the clock monitoring module includes a low level counter, a high level counter, and an or gate. Both low level counters and high level counters require a clock generated by the delay logic module for proper operation. The low level counter and the high level counter may record the duration of the low level pulse signal and the high level pulse signal, respectively. If the original clock in the CPLD is normal, the low-level pulse signal and the high-level pulse signal are uniformly performed; if the low-level counter records that the pulse is continuously low-level pulse within a preset time period, the native clock signal is abnormal; or if the high level counter records that the pulse is continuously high level in the preset time period, the original clock signal is abnormal. The preset time period needs to be greater than half of the unit time of the native clock in the CPLD, for example, if one unit time of the native clock in the CPLD is 1 second, then the preset time period needs to be greater than 0.5 second. The or gate receives a high level signal output by the low level counter or the high level counter due to the abnormality of the native clock signal. So as long as one counter outputs a high level signal due to the abnormality of the native clock signal, the or gate will output a high level signal. The signal output by the or gate is also representative of the signal ultimately output by the delay logic block.
The multiplexer may be an alternative multiplexer, that is, one of the two received signals is selected to be output. As shown in fig. 2, when the multiplexer receives the high level signal output by the or gate of the clock monitoring module, that is, the native clock in the CPLD is abnormal, the multiplexer selects the logic clock signal of the delay logic module and outputs the logic clock signal; if the multiplexer receives the low level signal output by the or gate of the clock monitoring module, that is, the native clock in the CPLD is normal, the multiplexer selects the native clock signal of the native clock and outputs the native clock signal.
In a second aspect of the embodiment of the present invention, a CPLD operating clock holding system is also provided. Fig. 3 is a schematic diagram illustrating an embodiment of the CPLD operating clock maintaining system according to the present invention. A CPLD operating clock holding system includes: the native clock signal monitoring module 10 is configured to respond to the starting of the CPLD, generate a logic clock signal through a delay logic module preset in the CPLD, and input the logic clock signal to the clock monitoring module so that the clock monitoring module monitors the abnormality of the native clock signal in the CPLD based on the logic clock signal; a clock monitoring signal output module 20 configured to output a clock monitoring signal based on the monitoring result through the clock monitoring module; and an operating clock selection module 30 configured to receive the clock monitoring signal through the multiplexer, select the logic clock signal or the native clock signal based on the clock monitoring signal, and output the same as the operating clock of the CPLD.
The CPLD working clock holding system provided by the embodiment of the invention can provide clock signals for the CPLD by arranging the delay logic module, so that the CPLD does not need to use a clock provided by an external circuit, external hardware is saved, and the area of a circuit board is reduced; by arranging the clock monitoring module, the abnormal condition of the native clock in the CPLD can be monitored; by arranging the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring condition of the clock monitoring module, so that a normal clock signal is selected, and the CPLD can work normally all the time.
In some embodiments, the native clock signal monitoring module 10 includes an anomaly monitoring module configured to input the logic clock signal to the clock monitoring module and receive the logic clock signal and the native clock signal through a low level counter and a high level counter of the clock monitoring module, respectively; monitoring, by a low-level counter, whether the native clock signal continues to be a low-level pulse signal for a preset period of time based on the logic clock signal, and monitoring, by a high-level counter, whether the native clock signal continues to be a high-level pulse signal for a preset period of time based on the logic clock signal.
In some embodiments, the clock monitoring signal output module 20 is further configured to output a high level signal through the low level counter in response to the low level counter monitoring that the native clock signal continues to be a low level pulse signal for a preset time period; or responding to the fact that the high-level counter monitors that the original clock signal is continuously a high-level pulse signal in a preset time period, and outputting the high-level signal through the high-level counter; and outputting the high-level signal of the low-level counter or the high-level counter through the clock monitoring module.
In some embodiments, the operating clock selection module 30 is further configured to receive a high level signal of the clock monitoring module through the multiplexer, and select the logic clock signal based on the high level signal and output it as the operating clock of the CPLD.
In some embodiments, the clock monitor signal output module 20 is further configured to output the low level signal through the clock monitor module in response to the low level counter monitoring that the native clock signal does not continue to be the low level pulse signal for the preset time period and the high level counter monitoring that the native clock signal does not continue to be the high level pulse signal for the preset time period.
In some embodiments, the operating clock selection module 30 is further configured to receive the low level signal through the multiplexer and select the native clock signal based on the low level signal and output it as the operating clock of the CPLD.
In some embodiments, the delay logic block includes a flip-flop, an inverter, an exclusive-or gate, and a delay buffer.
In a third aspect of the embodiment of the present invention, a computer-readable storage medium is further provided, and fig. 4 is a schematic diagram of a computer-readable storage medium implementing a CPLD working clock holding method according to an embodiment of the present invention. As shown in fig. 4, the computer-readable storage medium 3 stores computer program instructions 31, and when executed, the computer program instructions 31 implement the method of any one of the above embodiments:
it should be understood that all of the embodiments, features and advantages set forth above with respect to the CPLD operating clock retention method according to the present invention are equally applicable to the CPLD operating clock retention system and the storage medium according to the present invention, without conflicting therewith.
In a fourth aspect of the embodiments of the present invention, there is further provided a computer device, including a memory 402 and a processor 401, where the memory stores a computer program, and the computer program, when executed by the processor, implements the method of any one of the above embodiments.
Fig. 5 is a schematic diagram of a hardware structure of an embodiment of a computer device for executing a CPLD operation clock holding method according to the present invention. Taking the computer device shown in fig. 5 as an example, the computer device includes a processor 401 and a memory 402, and may further include: an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 may be connected by a bus or other means, and fig. 5 illustrates an example of a connection by a bus. The input device 403 can receive input numeric or character information and generate key signal inputs related to user settings and function control of the CPLD operating clock retention system. The output device 404 may include a display device such as a display screen.
The memory 402, which is a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the CPLD operating clock keeping method in the embodiment of the present application. The memory 402 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of the CPLD operation clock holding method, and the like. Further, the memory 402 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 402 may optionally include memory located remotely from processor 401, which may be connected to local modules via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The processor 401 executes various functional applications and data processing of the server by running the nonvolatile software programs, instructions and modules stored in the memory 402, that is, the CPLD operating clock keeping method of the above method embodiment is implemented.
Finally, it should be noted that, as those skilled in the art can understand, all or part of the processes in the methods of the foregoing embodiments can be implemented by instructing relevant hardware by a computer program, and the program of the CPLD operating clock keeping method can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the foregoing methods. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (9)
1. A CPLD working clock keeping method is characterized by comprising the following steps:
responding to the starting of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal to a clock monitoring module so as to enable the logic clock signal to monitor the abnormality of a native clock signal in the CPLD based on the logic clock signal;
outputting a clock monitoring signal based on a monitoring result through the clock monitoring module;
receiving the clock monitoring signal through a multiplexer, selecting the logic clock signal or the native clock signal based on the clock monitoring signal, and outputting the logic clock signal or the native clock signal as a working clock of the CPLD;
the delay logic module comprises a flip-flop, an inverter, an exclusive-OR gate and a delay buffer;
an output pin Q in the flip-flop is initially jumped from a low level to a high level, the Q is initially output as a high level signal, and the high level signal is changed into a low level signal after passing through the inverter and is input to a pin D of the flip-flop;
the first signal which is received by the exclusive-OR gate and does not pass through the delay buffer is a high level signal, the high level signal which needs to pass through the delay buffer is not received by the exclusive-OR gate, and the delay buffer can output a low level signal to the exclusive-OR gate in an initial state, so that the exclusive-OR gate receives two different signals initially and outputs the high level signal, and the flip-flop is triggered;
the Q pin of the flip-flop outputs the low level signal of the D pin, the XOR gate receives the low level signal as a first signal, and the initial high level signal reaches the XOR gate, so that the XOR gate receives two different signals and outputs the high level signal to the flip-flop, and the flip-flop is triggered to enable the delay logic module to continuously output the high level signal and the low level signal.
2. The method of claim 1, wherein inputting the logical clock signal to a clock monitoring module to cause it to monitor for anomalies in a native clock signal within the CPLD based on the logical clock signal comprises:
inputting the logic clock signal to a clock monitoring module, and respectively receiving the logic clock signal and a native clock signal through a low level counter and a high level counter of the clock monitoring module;
monitoring, by the low level counter, whether the native clock signal continues to be a low level pulse signal for a preset time period based on the logic clock signal, and monitoring, by the high level counter, whether the native clock signal continues to be a high level pulse signal for the preset time period based on the logic clock signal.
3. The method of claim 2, wherein outputting, by the clock monitoring module, a clock monitoring signal based on the monitoring result comprises:
responding to the low-level counter monitoring that the native clock signal is continuously a low-level pulse signal in the preset time period, and outputting a high-level signal through the low-level counter; or
Responding to the fact that the high-level counter monitors that the native clock signal is continuously a high-level pulse signal in the preset time period, and outputting a high-level signal through the high-level counter;
and outputting the high level signal of the low level counter or the high level counter through the clock monitoring module.
4. The method of claim 3, wherein receiving the clock monitor signal by a multiplexer and selecting and outputting the logical clock signal or native clock signal as an operating clock of a CPLD based on the clock monitor signal comprises:
and receiving a high level signal of the clock monitoring module through a multiplexer, selecting the logic clock signal based on the high level signal and outputting the logic clock signal to serve as a working clock of the CPLD.
5. The method of claim 2, wherein outputting, by the clock monitoring module, a clock monitoring signal based on the monitoring result comprises:
outputting, by the clock monitoring module, a low level signal in response to the low level counter monitoring that the native clock signal does not continue to be a low level pulse signal within the preset time period and the high level counter monitoring that the native clock signal does not continue to be a high level pulse signal within the preset time period.
6. The method of claim 5, wherein receiving the clock monitor signal by a multiplexer and selecting and outputting the logical clock signal or native clock signal as an operating clock of a CPLD based on the clock monitor signal comprises:
the low level signal is received by a multiplexer and based on the low level signal the native clock signal is selected and output as the operating clock of the CPLD.
7. A CPLD working clock holding system is characterized by comprising:
the native clock signal monitoring module is configured to respond to the starting of the CPLD, generate a logic clock signal through a delay logic module preset in the CPLD, and input the logic clock signal to the clock monitoring module so as to enable the clock monitoring module to monitor the abnormality of the native clock signal in the CPLD based on the logic clock signal;
the clock monitoring signal output module is configured for outputting a clock monitoring signal based on a monitoring result through the clock monitoring module; and
the working clock selection module is configured to receive the clock monitoring signal through a multiplexer, select the logic clock signal or the native clock signal based on the clock monitoring signal and output the logic clock signal or the native clock signal as a working clock of the CPLD;
the delay logic module comprises a flip-flop, an inverter, an exclusive-OR gate and a delay buffer;
an output pin Q in the flip-flop is initially jumped from a low level to a high level, the Q is initially output as a high level signal, and the high level signal is changed into a low level signal after passing through the inverter and is input to a pin D of the flip-flop;
the first signal which is received by the exclusive-OR gate and does not pass through the delay buffer is a high level signal, the high level signal which needs to pass through the delay buffer is not received by the exclusive-OR gate, and the delay buffer can output a low level signal to the exclusive-OR gate in an initial state, so that the exclusive-OR gate receives two different signals initially and outputs the high level signal, and the flip-flop is triggered;
the Q pin of the flip-flop outputs the low level signal of the D pin, the XOR gate receives the low level signal as a first signal, and the initial high level signal reaches the XOR gate, so that the XOR gate receives two different signals and outputs the high level signal to the flip-flop, and the flip-flop is triggered to enable the delay logic module to continuously output the high level signal and the low level signal.
8. A computer-readable storage medium, characterized in that computer program instructions are stored which, when executed, implement the method according to any one of claims 1-6.
9. A computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when executed by the processor, performs the method according to any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110592477.3A CN113448381B (en) | 2021-05-28 | 2021-05-28 | CPLD working clock keeping method, system, storage medium and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110592477.3A CN113448381B (en) | 2021-05-28 | 2021-05-28 | CPLD working clock keeping method, system, storage medium and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113448381A CN113448381A (en) | 2021-09-28 |
| CN113448381B true CN113448381B (en) | 2023-02-28 |
Family
ID=77810355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110592477.3A Active CN113448381B (en) | 2021-05-28 | 2021-05-28 | CPLD working clock keeping method, system, storage medium and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113448381B (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100337404C (en) * | 2004-06-24 | 2007-09-12 | 华为技术有限公司 | Crystal oscillation duplicaltion and its duplicating circuit |
| US20080013664A1 (en) * | 2006-07-11 | 2008-01-17 | Mediatek Inc. | Phase error measurement circuit and method thereof |
| CN100563171C (en) * | 2006-09-29 | 2009-11-25 | 华为技术有限公司 | A kind of method and system that improve BITS equipment output reliability |
| CN101494498B (en) * | 2009-03-06 | 2012-09-05 | 中兴通讯股份有限公司 | Apparatus and method for collecting SFP optical module signal |
| CN101764594A (en) * | 2009-11-09 | 2010-06-30 | 天津南大强芯半导体芯片设计有限公司 | Clock signal detection circuit and abnormal clock signal detection method |
| CN102223143A (en) * | 2010-04-16 | 2011-10-19 | 电信科学技术研究院 | Clock signal protective device, clock signal protective method and clock detection compensating circuit |
| CN102694616B (en) * | 2012-06-11 | 2014-11-26 | 福建星网锐捷网络有限公司 | Clock detection circuit, clock circuit and clock exception detection method |
| CN111856916A (en) * | 2019-04-30 | 2020-10-30 | 联合汽车电子有限公司 | External clock diagnosis method |
| CN112114616B (en) * | 2020-08-04 | 2022-10-25 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
-
2021
- 2021-05-28 CN CN202110592477.3A patent/CN113448381B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113448381A (en) | 2021-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11100224B2 (en) | Interference detection device and detection sensitivity adjusting method thereof | |
| US20140130189A1 (en) | Transition between states in a processor | |
| JPS6245572B2 (en) | ||
| CN102567671A (en) | Encryption system and encryption method for field-programmable gate array (FPGA) configuration data | |
| WO2021098077A1 (en) | True random number generator and true random number generation method | |
| CN110109694B (en) | Device pin control method and programmable logic device | |
| US20050246586A1 (en) | Device capable of detecting BIOS status for clock setting and method thereof | |
| CN113448381B (en) | CPLD working clock keeping method, system, storage medium and device | |
| US6148418A (en) | Computer environment monitor device | |
| CN109491491A (en) | A kind of server timing control and signal monitoring board | |
| US8891302B2 (en) | Electronic equipment | |
| US6147537A (en) | Reset circuit for flipflop | |
| US20030097618A1 (en) | Microcontroller capable of correcting program codes and method for driving the same | |
| CN111800379A (en) | Industrial control private protocol detection method and device based on Lua | |
| US11879938B2 (en) | Method for detecting perturbations in a logic circuit and logic circuit for implementing this method | |
| TW201918925A (en) | Data accessing device and method | |
| JP6697776B2 (en) | Unique information generator | |
| EP3767849A1 (en) | A hardware component and a method for implementing a camouflage of current traces generated by a digital system | |
| US20030005347A1 (en) | Flip-flop having multiple clock sources and method therefore | |
| US20080238490A1 (en) | Semiconductor device and method for driving the same | |
| JP2007299247A (en) | System control device, server device provided with system control circuit | |
| KR100193759B1 (en) | How to update data in cache memory | |
| US10761581B2 (en) | Method and module for programmable power management, and system on chip | |
| KR19980027922A (en) | Multiple test mode setting method and device accordingly | |
| CN110794282B (en) | dSPACE-HIL system based method and apparatus for communicating with electronic devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |