CN110109694B - Device pin control method and programmable logic device - Google Patents
Device pin control method and programmable logic device Download PDFInfo
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- CN110109694B CN110109694B CN201910352066.XA CN201910352066A CN110109694B CN 110109694 B CN110109694 B CN 110109694B CN 201910352066 A CN201910352066 A CN 201910352066A CN 110109694 B CN110109694 B CN 110109694B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The disclosure provides a device pin control method and a programmable logic device, and relates to the technical field of communication. The method comprises the following steps: when the programmable logic device is upgraded, receiving an enabling signal sent by the processor, wherein the enabling signal is used for triggering the latch state of an output pin of the programmable logic device; and the programmable logic device controls an output pin to keep a latch state according to the enable signal, wherein the output pin keeps a preset fixed signal in the latch state. The output pin is controlled to be in a latch state, so that the output signal of the output pin is kept unchanged in the upgrading process of the programmable logic device, the abnormal condition caused by jumping of the signal output by the output pin is avoided, and the reliability and flexibility of the programmable logic device in the upgrading process are improved.
Description
Technical Field
The disclosure relates to the technical field of communication, and particularly relates to a device pin control method and a programmable logic device.
Background
The network device (e.g. router, server, etc.) may include a programmable logic device, so that the programmable logic device may perform analysis and calculation, thereby controlling the network device to perform operations corresponding to calculation results, so that the network device may implement data interaction with other network devices or terminals.
However, before and after the programmable logic device is upgraded, signal jump occurs at an output pin of the programmable logic device, which causes an abnormality in a system where the network device is located.
Disclosure of Invention
The present disclosure aims to provide a device pin control method and a network device, so as to solve the problem that before and after a programmable logic device is upgraded, an output pin of the programmable logic device may generate signal jump, which causes an abnormality in a system in which the network device is located.
In order to achieve the above purpose, the technical solution adopted in the embodiments of the present disclosure is as follows:
in a first aspect, an embodiment of the present disclosure provides a device pin control method, where the method is applied to a programmable logic device in a programmable logic device upgrade system, the system further includes a processor, and the programmable logic device is communicatively connected to the processor, where the method includes:
when the programmable logic device is upgraded, receiving an enabling signal sent by the processor, wherein the enabling signal is used for triggering the latch state of an output pin of the programmable logic device;
and the programmable logic device controls the output pin to keep a latch state according to the enable signal, wherein the output pin keeps a preset fixed signal in the latch state.
In a second aspect, an embodiment of the present disclosure further provides a programmable logic device, including: the device comprises a design module, a latch unit, an output pin and a device input interface, wherein a first input end of the latch unit is connected with the device input interface, and an output end of the latch unit is connected with the output pin;
when the design module upgrades the programmable logic device, the latch unit is used for receiving an enabling signal sent by a processor through the device input interface, and the enabling signal is used for triggering the latch state of an output pin;
the latch unit is further configured to control the output pin to maintain a latch state through an output end of the latch unit according to the enable signal, where the output pin maintains a preset fixed signal in the latch state.
In a third aspect, an embodiment of the present disclosure further provides a network device, including: a processor, a memory for storing processor-executable instructions, a communication interface and a communication bus, the processor, the memory and the communication interface being connected and communicating through the communication bus, the processor being configured to execute the instructions stored in the memory to implement the steps of the method of any one of the first aspect.
In a fourth aspect, the disclosed embodiments also provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method in any one of the first aspect.
The beneficial effects of this disclosure are:
the embodiment of the disclosure receives an enable signal sent by a processor and used for triggering the latch state of an output pin of a programmable logic device when the programmable logic device is upgraded, and controls the output pin to keep the latch state according to the enable signal, so that the output pin keeps a preset fixed signal in the latch state. The output pin is controlled to be in a latch state, so that the output signal of the output pin is kept unchanged in the upgrading process of the programmable logic device, the abnormal condition caused by jumping of the signal output by the output pin is avoided, and the reliability and flexibility of the programmable logic device in the upgrading process are improved.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present disclosure and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings may be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a network device according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a programmable logic device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a programmable logic device according to another embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a programmable logic device according to yet another embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a programmable logic device according to yet another embodiment of the present disclosure;
fig. 6 is a schematic flow chart of a device pin control method according to an embodiment of the present disclosure;
fig. 7 is a schematic flow chart of a device pin control method according to another embodiment of the present disclosure;
fig. 8 is a schematic diagram of a network device according to an embodiment of the present disclosure.
Icon: 110-programmable logic devices; 120-a processor; 1101-a design module; 1102-a latch unit; 1103 — output pin; 1104-device input interface; 1105-an inverter; 1106-inverting not gate; 1101 a-a first input of the design module; 1101 b-the output of the design module; 1101 c-a second input of the design module; 1102 a-a first input of a latch unit; 1102 b-output of latch unit; 1102 c-a second input of the latch unit; 1102 d-third input of latch unit; 801-a processor; 802-a memory; 803 — a communication interface; 804-communication bus.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure.
Fig. 1 is a schematic structural diagram of a network device according to a device pin control method provided in the present disclosure, and as shown in fig. 1, the network device may include: programmable logic device 110 and processor 120, programmable logic device 110 is communicatively coupled to processor 120.
In the related art, the configuration data of the programmable logic device 110 may be updated in a manner that the processor 120 analyzes and processes the upgrade file, so as to upgrade the programmable logic device 110. For example, the programmable logic device 110 may be upgraded in a Flash Programming Mode (Flash loading Mode), and after the configuration data of the programmable logic device 110 is updated, the programmable logic device 110 may be upgraded.
However, before and after the programmable logic device 110 is upgraded, signal jump may occur at the output pin of the programmable logic device 110, which may cause an abnormality in the system in which the network device is located.
Therefore, in the present disclosure, when the programmable logic device 110 is upgraded, the programmable logic device 110 is configured to receive an enable signal sent by the processor 120, where the enable signal is used to trigger the latch state of the output pin of the programmable logic device 110.
The programmable logic device 110 is further configured to control an output pin to maintain a latch state according to the enable signal, wherein the output pin maintains a predetermined fixed signal in the latch state.
In order to avoid the output pin of the programmable logic device 110 being abnormal during the upgrade process, the processor 120 may control the programmable logic device 110 to keep the output pin in a latch state, so as to control the output of the programmable logic device 110 to be a preset fixed signal.
Specifically, when the programmable logic device 110 is upgraded, the processor 120 may send an enable signal to the programmable logic device 110, and the programmable logic device 110 may receive the enable signal and control the output pin of the programmable logic device 110 to maintain the latch state according to the enable signal, so that the output pin keeps outputting the preset fixed signal in the latch state.
The output pin of the programmable logic device 110 may be exemplified as an output pin having a latch function. After the programmable logic device 110 receives the enable signal sent by the processor 120, the latch function of the output pin may be triggered by the enable signal, so that the output pin is in a latch state, thereby controlling the signal output by the output pin.
Alternatively, as shown in fig. 2, the programmable logic device 110 may include: a design block 1101, a latch unit 1102, an output pin 1103, and a device input interface 1104.
The first input terminal 1102a of the latch unit is connected to the device input interface 1104, and the output terminal 1102b of the latch unit is connected to the output pin 1103.
When the design module 1101 upgrades the programmable logic device 110, the latch unit 1102 is configured to receive an enable signal sent by the processor 120 through the device input interface 1104, where the enable signal is used to trigger the latch state of the output pin.
The latch unit 1102 is further configured to control the output pin 1103 to maintain a latch state according to the enable signal through the output terminal 1102b of the latch unit, wherein the output pin 1103 maintains a preset fixed signal in the latch state.
Specifically, the latch unit 1102 in the programmable logic device 110 may control the output pin 1103 to be in a latch state according to the enable signal, and store the currently output preset fixed signal as the output feedback signal through the design module 1101, so that when the programmable logic device 110 unlocks the latch state, the output feedback signal may be output according to the stored output feedback signal.
Alternatively, referring to fig. 3, the first input terminal 1101a of the design block is connected to the output terminal 1102b of the latch unit.
The design module 1101 is configured to receive the preset fixing signal output by the output terminal 1102b of the latch unit through a first input terminal 1101a of the design module, and the design module 1101 is further configured to store the preset fixing signal as an output feedback signal.
Optionally, the latch unit 1102 is further configured to receive an unlocking instruction sent by the processor 120 after the design module 1101 is upgraded, and the latch unit 1102 is further configured to release the latch state of the output pin 1103 according to the unlocking instruction.
Optionally, referring to fig. 4, the second input terminal 1102c of the latch unit is connected to the output terminal 1101b of the design module, the second input terminal 1101c of the design module is connected to the device input interface 1104, and the output terminal 1102b of the latch unit is connected to the third input terminal 1102d of the latch unit.
The design module 1101 is further configured to output an output feedback signal through an output end 1101b of the design module according to the unlocking instruction;
the latch unit 1102 is further configured to release the latch state of the output terminal 1102b of the latch unit according to the output feedback signal received by the second input terminal 1102c of the latch unit and the unlock instruction received by the first input terminal 1102a of the latch unit, so that the output pin 1103 releases the latch state.
Optionally, the latch unit 1102 is further configured to release the latch state of the output pin 1103 after a preset time period in which the output pin 1103 maintains the latch state.
It should be noted that, in practical applications, referring to fig. 5, the programmable logic device 110 may include an inverter 1105 and an inverter not gate 1106, and the embodiments of the present disclosure do not limit the positions and the numbers of the inverter 1105 and the inverter not gate 1106 in the programmable logic device 110.
In addition, in practical applications, the Programmable Logic Device 110 may be a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or another Device having a data processing function, which is not limited in this disclosure.
To sum up, the network device provided in the embodiment of the present disclosure receives, when the programmable logic device is upgraded, an enable signal sent by the processor and used for triggering the latch state of the output pin of the programmable logic device, and controls the output pin to maintain the latch state according to the enable signal, so that the output pin maintains the preset fixed signal in the latch state. The output pin is controlled to be in a latch state, so that the output signal of the output pin is kept unchanged in the upgrading process of the programmable logic device, the abnormal condition caused by jumping of the signal output by the output pin is avoided, and the reliability and flexibility of the programmable logic device in the upgrading process are improved.
Fig. 6 is a schematic flowchart of a device pin control method according to an embodiment of the present disclosure, as shown in fig. 6, and is applied to the network device shown in fig. 1, where the method includes:
and 601, receiving an enabling signal sent by a processor when the programmable logic device is upgraded.
Wherein the enable signal is used to trigger the latch state of the output pin of the programmable logic device.
In the process of upgrading the programmable logic device, the configuration data of the programmable logic device can be updated, and after the configuration data of the programmable logic device is updated, the programmable logic device is upgraded.
However, in the upgrade process of the programmable logic device, in order to avoid a change in a signal output by an output pin of the programmable logic device, when the upgrade of the programmable logic device is detected, the processor may send an enable signal to the programmable logic device, so that in a subsequent step, the programmable logic device may control the output pin of the programmable logic device according to the enable signal.
Specifically, if the processor detects that the programmable logic device is upgraded, the processor may send control information to the programmable logic device, and the programmable logic device may process the control information according to a preset function module to obtain an enable signal.
The control information is used for controlling an output pin of the programmable logic device to be in a latch state.
For example, if a Central Processing Unit (CPU) detects that a CPLD is upgraded, the CPU may send control information to the CPLD through a Local Bus (Local Bus), and the CPLD receives the control information and analyzes the control information according to a preset seamless switching control module to obtain an enable signal.
It should be noted that, in practical applications, the processor may analyze the upgrade file, so as to update the configuration data of the programmable logic device according to the result obtained by the analysis, thereby implementing the upgrade of the programmable logic device.
The upgrade file may be a configuration file of the CPLD, for example, the upgrade file may be text data, table data, or other data for recording configuration parameters, which is not limited in this embodiment of the present disclosure.
Wherein the output pin holds a preset fixed signal in a latch state.
After the enable signal is obtained, the programmable logic device can control the output pin to continuously output a preset fixed signal according to the enable signal, so that the output pin is controlled to keep a latch state until the programmable logic device is upgraded, namely the configuration data of the programmable logic device is completely updated.
Specifically, after obtaining the enable signal, the programmable logic device may send the enable signal to a latch unit in the programmable logic device, and then the latch unit may control an output terminal of the latch unit to maintain a latch state according to the enable signal, and accordingly, an output pin connected to the output terminal of the latch unit also maintains the latch state.
In practical applications, in order to make the signal output by the output terminal of the latch unit and the feedback signal received by the third input terminal of the latch unit consistent, two inverters may be disposed between the output terminal and the first input terminal of the latch unit, and accordingly, an output pin may be connected between the two inverters.
To sum up, in the device pin control method provided by the embodiment of the present disclosure, when the programmable logic device is upgraded, the enable signal sent by the processor and used for triggering the latch state of the output pin of the programmable logic device is received, and according to the enable signal, the output pin is controlled to maintain the latch state, so that the output pin maintains the preset fixed signal in the latch state. The output pin is controlled to be in a latch state, so that the output signal of the output pin is kept unchanged in the upgrading process of the programmable logic device, the abnormal condition caused by jumping of the signal output by the output pin is avoided, and the reliability and the flexibility of the programmable logic device in the upgrading process are improved.
Fig. 7 is a schematic flowchart of a device pin control method according to another embodiment of the present disclosure, as shown in fig. 7, and is applied to the network device shown in fig. 1, where the method includes:
and step 701, when the programmable logic device loads the upgrade file, receiving an enable signal sent by the processor.
Wherein the enable signal is used to trigger the latch state of the output pin of the programmable logic device.
And step 702, the programmable logic device controls the output pin to keep a latch state according to the enable signal.
Wherein, the output pin keeps a preset fixed signal in a latch state.
After the enable signal is obtained, the programmable logic device can control the output pin to be in a latch state according to the enable signal, and the situation that the signal output by the output pin is suddenly changed in the upgrading process of the programmable logic device is avoided.
The programmable logic device may include: a plurality of components such as a latch unit, an output pin and a device input interface. Accordingly, various components in the programmable logic device may perform different operations in controlling the output pin to maintain the latched state.
Optionally, the latch unit may receive an enable signal transmitted by the device input interface through the first input end of the latch unit, and the latch unit may control the output end of the latch unit to be in a latch state according to the enable signal, so as to control the output pin to maintain the latch state.
Specifically, the programmable logic device may receive an enable signal sent by the processor through the device input interface, and receive the enable signal transmitted by the device input interface through the first input end of the latch unit, and the latch unit may trigger the latch state according to the enable signal, and control the signal output by the latch unit not to be affected by the design module, so that the output end of the latch unit maintains the latch state, that is, the output end of the latch unit continuously outputs a preset fixed signal.
Because the output end of the latch unit is connected with the output pin, and the output pin outputs the signal of the programmable logic device according to the signal output by the latch unit, when the output end of the latch unit keeps the latch state, the output pin correspondingly keeps the latch state, thereby realizing the control of the output pin in the latch state.
For example, the programmable logic device receives a high-level enable signal sent by the processor, the latch unit may trigger the latch state according to the high-level signal, so that the output terminal of the latch unit continuously outputs the currently output high level or low level, and the output pin may output the same or opposite level signal, which is not limited herein.
And step 703, acquiring an output feedback signal.
In order that the programmable logic device can quickly continue to normally work after the upgrade is finished, the currently output signal of the programmable logic device can be stored. Therefore, the programmable logic device can acquire the preset fixed signal output by the latch unit and store the preset fixed signal as an output feedback signal, so that the latch state of the output pin can be released according to the output feedback signal in the subsequent step.
Optionally, the first input end of the design module may receive a preset fixed signal output by the output end of the latch unit, and the design module may further store the preset fixed signal as an output feedback signal.
Specifically, when the output pin is in the latch state, the output pin and the output end of the latch unit continuously output the preset fixed signal, and the design module in the programmable logic device may obtain the preset fixed signal output by the output end of the latch unit through the first input end of the design module, and store the preset fixed signal as the output feedback signal in the design module.
And 704, the programmable logic device receives an unlocking instruction sent by the processor after the programmable logic device is detected to be upgraded.
After the programmable logic device finishes updating the configuration data, the programmable logic device is upgraded, and the latch state can be released so as to continue working. Therefore, after the processor detects that the programmable logic device is upgraded, the processor can send an unlocking instruction to the programmable logic device, so that the latch state of the programmable logic device is released through the unlocking instruction.
Specifically, after the programmable logic device is upgraded, feedback information indicating that the upgrade is completed may be fed back to the processor, and the processor may receive the feedback information and send an unlocking instruction to the programmable logic device according to the feedback information.
Correspondingly, the programmable logic device can receive the unlocking instruction and release the latch state of the output pin according to the unlocking instruction, so that the programmable logic device is controlled to release the latch state, and the programmable logic device works with the upgraded function to update the function of the programmable logic device.
Further, in the process of receiving the recovery instruction by the programmable logic device, the device input interface may receive an unlocking instruction sent by the processor after the programmable logic device is detected to be completely loaded, the latch unit may receive the unlocking instruction sent by the device input interface through the first input end of the latch unit, and the design module may receive the unlocking instruction sent by the processor and received by the device input interface through the second input end of the design module.
Specifically, the device input interface of the programmable logic device may receive an unlocking instruction sent by the processor, and then the latch unit and the design module may receive the unlocking instruction through the first input terminal of the latch unit and the second input terminal of the design module, respectively, so that in the subsequent step, both the latch unit and the design module may release the latch state of the programmable logic device according to the unlocking instruction.
It should be noted that, in practical applications, the programmable logic device may not send feedback information to the processor after the upgrade is completed, and the processor may also be unable to receive the feedback information sent by the programmable logic device. Therefore, the programmable logic device cannot receive the unlocking instruction sent by the processor, and if the programmable logic device does not receive the unlocking instruction sent by the processor within the preset time period, step 706 may be executed after step 703 is executed, so that the programmable logic device releases the latch state.
After receiving the unlocking instruction sent by the processor, the programmable logic device can send the unlocking instruction to the latch unit and the design module of the programmable logic device respectively so as to release the latch state of the output pin, and the programmable logic device can continue to work normally.
Optionally, the design module may output an output feedback signal through an output end of the design module according to the unlocking instruction, and the latch unit may release the latch state of the output end of the latch unit according to the output feedback signal received by the second input end of the latch unit and the unlocking instruction received by the first input end of the latch unit, so that the output pin releases the latch state.
Specifically, after the programmable logic device receives the unlocking instruction, both the design module and the latch unit of the programmable logic device may obtain the unlocking instruction, and after the design module obtains the unlocking instruction, the design module may control the design module to use the signal received by the first input end of the design module as the signal output by the output end of the design module, that is, to use the output feedback signal stored in step 703 as the signal output by the output end of the design module.
Moreover, after the latch unit obtains the unlocking instruction, the latch unit can unlock the signal output by the output end of the latch unit according to the unlocking instruction, that is, the signal output by the latch unit is not locked any more, but the latch unit is controlled to output according to the signal received by the second input end of the latch unit, so that the signal output by the output end of the latch unit is consistent with the signal received by the second input end of the latch unit, the signal output by the output end of the latch unit is unlocked, and the output pin is unlocked.
In step 706, the programmable logic device releases the latch state of the output pin after a preset time period in which the output pin remains in the latch state.
If the programmable logic device does not receive the unlocking instruction sent by the processor within the preset time period, the programmable logic device or the processor is abnormal, but the latch state needs to be released because the programmable logic device is upgraded.
Therefore, the programmable logic device still does not receive the unlocking instruction sent by the processor after the preset time period, and the latch state of the output pin can be released.
The preset time period can be set according to the time length required by upgrading the programmable logic device, and the time length of the preset time period is not limited in the embodiment of the disclosure.
Moreover, the process of the step 706 for releasing the latch state of the output pin is similar to the process of releasing the latch state of the output pin in the step 705, and is not described herein again.
In practical applications, an application program with a timer function may be compiled in the programmable logic device, and when the timer indicates that the counting is finished, the latch state of the output pin may be released.
To sum up, in the device pin control method provided by the embodiment of the present disclosure, when the programmable logic device is upgraded, the enable signal sent by the processor and used for triggering the latch state of the output pin of the programmable logic device is received, and according to the enable signal, the output pin is controlled to maintain the latch state, so that the output pin maintains the preset fixed signal in the latch state. The output pin is controlled to be in a latch state, so that the output signal of the output pin is kept unchanged in the upgrading process of the programmable logic device, the abnormal condition caused by jumping of the signal output by the output pin is avoided, and the reliability and the flexibility of the programmable logic device in the upgrading process are improved.
Furthermore, after the programmable logic device is upgraded, the programmable logic device does not need to be restarted, and the function of the programmable logic device can be recovered in real time after the programmable logic device is upgraded, so that the programmable logic device can rapidly release the latch state, the problem that much time is consumed for restarting the programmable logic device is avoided, and the efficiency of releasing the latch state of the programmable logic device is improved.
Fig. 8 is a schematic diagram of a network device according to an embodiment of the present disclosure, where the network device may be integrated in a terminal device or a chip of the terminal device, and the network device may be a programmable logic device with a device pin control function in the foregoing embodiment.
The network device includes: a processor 801, a memory 802 for storing processor-executable instructions, a communication interface 803, and a communication bus 804.
The processor 801, the memory 802, and the communication interface 803 are coupled and in communication by a communication bus 804, and the processor 801 is configured to execute instructions stored in the memory 802 to perform the above-described method embodiments.
Optionally, the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A device pin control method, applied to a programmable logic device in a programmable logic device upgrade system, the system further comprising a processor, the programmable logic device and the processor being communicatively connected, the method comprising:
when the programmable logic device is upgraded, receiving an enabling signal sent by the processor, wherein the enabling signal is used for triggering the latch state of an output pin of the programmable logic device;
the programmable logic device controls the output pin to keep a latch state according to the enable signal, wherein the output pin keeps a preset fixed signal in the latch state;
the programmable logic device receives an unlocking instruction sent by the processor after the programmable logic device is detected to be upgraded;
the programmable logic device releases the latch state of the output pin according to the unlocking instruction;
the programmable logic device includes: the device comprises a latch unit, a design module, an output pin and a device input interface;
a first input end of the latch unit and a second input end of the design module are both connected with the device input interface, a second input end of the latch unit is connected with an output end of the design module, and an output end of the latch unit is respectively connected with the output pin and a third input end of the latch unit;
the programmable logic device unlocks the latch state of the output pin according to the unlocking instruction, and the unlocking method comprises the following steps:
the design module outputs an output feedback signal through the output end of the design module according to the unlocking instruction;
the latch unit unlocks the latch state of the output end of the latch unit according to the output feedback signal received by the second input end of the latch unit and the unlocking instruction received by the first input end of the latch unit, so that the output pin unlocks the latch state.
2. The method of claim 1, wherein the programmable logic device comprises: the latch unit, the output pin and the device input interface; the output end of the latch unit is connected with the output pin, and the first input end of the latch unit is connected with the device input interface; the programmable logic device controls the output pin to keep a latch state according to the enabling signal, and the method comprises the following steps:
the latch unit receives the enable signal transmitted by the device input interface through a first input end of the latch unit;
the latch unit controls the output end of the latch unit to be in a latch state according to the enable signal so as to control the output pin to keep the latch state.
3. The method of claim 2, wherein the programmable logic device further comprises: the output end of the latch unit is also connected with a first input end of the design module;
after the programmable logic device controls the output pin to maintain the latch state according to the enable signal, the method further comprises:
a first input end of the design module receives a preset fixed signal output by an output end of the latch unit;
and the design module stores the preset fixed signal as an output feedback signal.
4. The method of any of claims 1 to 3, wherein after the programmable logic device controls the output pin to maintain a latched state in accordance with the enable signal, the method further comprises:
the programmable logic device releases the latched state of the output pin after a preset period of time in which the output pin remains latched.
5. A programmable logic device, comprising: the device comprises a design module, a latch unit, an output pin and a device input interface, wherein a first input end of the latch unit is connected with the device input interface, and an output end of the latch unit is connected with the output pin;
the design module is used for storing and outputting a feedback signal, the latch unit is used for receiving an enable signal sent by the processor through the device input interface, and the enable signal is used for triggering the latch state of an output pin;
the latch unit is further used for controlling the output pin to keep a latch state through the output end of the latch unit according to the enable signal, wherein the output pin keeps a preset fixed signal in the latch state;
the latch unit is also used for receiving an unlocking instruction sent by the processor after the processor detects that the design module is upgraded;
the latch unit is also used for releasing the latch state of the output pin according to the unlocking instruction;
a second input end of the latch unit is connected with an output end of the design module, a second input end of the design module is connected with the device input interface, and an output end of the latch unit is connected with a third input end of the latch unit;
the design module is further used for outputting the output feedback signal through an output end of the design module according to the unlocking instruction;
the latch unit is further configured to release the latch state of the output end of the latch unit according to the output feedback signal received by the second input end of the latch unit and the unlock instruction received by the first input end of the latch unit, so that the output pin releases the latch state.
6. The programmable logic device of claim 5, wherein a first input of the design block is connected to an output of the latch unit;
the design module is used for receiving a preset fixed signal output by the output end of the latch unit through a first input end of the design module;
the design module is further configured to store the preset fixed signal as an output feedback signal.
7. The programmable logic device as claimed in claim 5 or 6, wherein said latch unit is further configured to release the latched state of said output pin after a preset period of time in which said output pin remains latched.
8. A network device, comprising: a processor, a memory for storing processor executable instructions, a communication interface and a communication bus, the processor, the memory and the communication interface being connected and communicating through the communication bus, the processor being configured to execute the instructions stored in the memory to implement the steps of the method of any one of claims 1 to 4.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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| CN110647340A (en) * | 2019-09-19 | 2020-01-03 | 锐捷网络股份有限公司 | Complex programmable logic device CPLD upgrading method and CPLD |
| CN111208891B (en) * | 2020-01-10 | 2021-10-26 | 浪潮商用机器有限公司 | CPLD updating system and method |
| CN111479372A (en) * | 2020-04-29 | 2020-07-31 | 杭州迪普科技股份有限公司 | Indicator lamp control device and method |
| CN113821240B (en) * | 2021-09-03 | 2023-11-17 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic device, storage medium and signal latch circuit |
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