CN105468387A - Upgrade processing method, device and system - Google Patents
Upgrade processing method, device and system Download PDFInfo
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- CN105468387A CN105468387A CN201410446645.8A CN201410446645A CN105468387A CN 105468387 A CN105468387 A CN 105468387A CN 201410446645 A CN201410446645 A CN 201410446645A CN 105468387 A CN105468387 A CN 105468387A
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Abstract
The embodiment of the invention provides an upgrade processing method, device and system. The method comprises the following steps: through a background mode, loading an upgrade program of a CPLD (Complex Programmable Logic Device) into a flash memory of the CPLD; backing up the register information and the pin signal of the CPLD; locking the pin of the CPLD; loading the upgrade program in the flash memory of the CPLD into the SRAM (Static Random Access Memory) of the CPLD; according to the backup register information and pin signal of the CPLD, recovering the register information and the pin signal of the CPLD; and after the register information and the pin signal of the CPLD finish being recovered, releasing the pin of the CPLD. The method can guarantee the consistency of an equipment state before and after the CPLD is upgraded without interrupting the current business of the system, so that no impacts are generated on the business, and system reliability is improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of upgrade processing method, device and system.
Background technology
(complexprogrammablelogicdevice is called for short: be CPLD) a kind of digital integrated circuit according to user's request constitutive logic function, be widely used in various communication network device CPLD.Along with the reliability to equipment, security requirement are more and more higher, if CPLD operationally goes wrong, or user's request change, then the program of the CPLD that needs to upgrade.But, the pin of CPLD can be discharged after the program of the complete CPLD of usual upgrading, the pin signal generation saltus step of CPLD before and after upgrading may be made like this, the front and back state of CPLD place equipment is caused to differ, need by the consistance ensureing state before and after upgrading that resets, thus cause equipment current business to be interrupted.Such as, if the signal that saltus step occurs is key signal, the control signal of equipment, the function of some Service Processing Modules on opertaing device, just likely affect the business of whole equipment.
Summary of the invention
The embodiment of the present invention provides a kind of upgrade processing method, device and system, does not need the current business of interrupt system, with the consistance of rear equipment state of upgrading before can ensureing CPLD upgrading.Avoid producing business impacting, improve the reliability of system.
The embodiment of the present invention provides a kind of upgrade processing method, comprising:
By background mode, ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD);
Back up register information and the pin signal of described CPLD;
Lock the pin of described CPLD;
Described ROMPaq in the flash memory of described CPLD is loaded in the static RAM SRAM of described CPLD;
The register information of CPLD and pin signal according to the register information of described CPLD of backup and pin signal recuperation;
After completing the register information and pin signal recovering described CPLD, discharge the pin of described CPLD.
Further, described by background mode ROMPaq is loaded in the flash memory of CPLD before, described method also comprises:
Generate serial vector format SVF file, in described SVF file, add backup command word and recover command word; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, for recovering register information and the pin signal of described CPLD.
Described flash memory ROMPaq being loaded into CPLD by background mode comprises:
By background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
Register information and the pin signal of the described CPLD of described backup comprise:
When running to described backup command word, back up register information and the pin signal of described CPLD;
According to the register information of described CPLD of backup and pin signal recuperation, the register information of CPLD and pin signal comprise:
When running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
The embodiment of the present invention provides a kind of upgrading processing device, comprising:
Load-on module, for being loaded in the flash memory of complex programmable logic device (CPLD) by background mode by ROMPaq;
Backup module, for backing up register information and the pin signal of described CPLD;
Locking module, for locking the pin of described CPLD;
Described load-on module, also for being loaded in the static RAM SRAM of described CPLD by the described ROMPaq in the flash memory of described CPLD;
Recover module, for register information and the pin signal of CPLD according to the register information of described CPLD of backup and pin signal recuperation;
Release module, for after completing the register information and pin signal recovering described CPLD, discharges the pin of described CPLD.
Further, described device also comprises:
Generation module, for generating serial vector format SVF file, adding corresponding backup command word and recovering command word in described SVF file; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
Described load-on module, specifically for by background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
Described backup module, specifically for when running to described backup command word, backs up register information and the pin signal of described CPLD;
Described recovery module, specifically for when running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
The embodiment of the present invention provides a kind of upgrading processing equipment, comprising: processor, storer;
Described storer, for depositing program; Particularly, program can comprise program code, and described program code comprises computer-managed instruction;
Described processor performs the program that described storer is deposited, for:
By background mode, ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD);
Back up register information and the pin signal of described CPLD;
Lock the pin of described CPLD;
Described ROMPaq in the flash memory of described CPLD is loaded in the static RAM SRAM of described CPLD;
The register information of CPLD and pin signal according to the register information of described CPLD of backup and pin signal recuperation;
After completing the register information and pin signal recovering described CPLD, discharge the pin of described CPLD.
Further, described by background mode ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD) before, also comprise:
For for generating serial vector format SVF file, in described SVF file, adding backup command word and recover command word; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
The described flash memory for by background mode ROMPaq being loaded into described CPLD is comprised:
For by background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
Register information and the pin signal of the described CPLD of described backup comprise:
When running to described backup command word, back up register information and the pin signal of described CPLD;
According to the register information of described CPLD of backup and pin signal recuperation, the register information of CPLD and pin signal comprise:
When running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
The embodiment of the present invention provides a kind of disposal system, for the upgrading to complex programmable logic device (CPLD), comprising: CPLD and upgrading processing device, and described upgrading processing device adopts above-mentioned upgrading processing device.
The upgrade processing method of CPLD provided by the invention, in device and system, after by background mode the ROMPaq of CPLD being loaded in the Flash of CPLD, the register information of backup CPLD and pin signal, and then the ROMPaq in the Flash of CPLD is loaded in the SRAM of CPLD, at this moment the pin of CPLD is not discharged immediately, but first by the register information of the CPLD of above-mentioned backup and pin signal recuperation in described CPLD, make the rear current register information of CPLD of the register information of the CPLD before upgrading and pin signal and upgrading and the pin Signal Matching of CPLD, the last pin discharging described CPLD again, complete the upgrading processing of CPLD, with the consistance of rear equipment state of upgrading before CPLD upgrading can be ensured, the business of current system can not be interrupted, avoid producing business impacting, improve the reliability of system.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The process flow diagram of the upgrade processing method that Fig. 1 provides for the embodiment of the present invention;
The structural representation of a kind of upgrading processing device that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the another kind of upgrading processing device that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the upgrading processing system that Fig. 4 provides for the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The process flow diagram of the upgrade processing method that Fig. 1 provides for the embodiment of the present invention, can be used in the equipment running process of described CPLD place, do not interrupt the normal work of CPLD, under needing the scene to the program upgrade of described CPLD, the operation of the CPLD that upgrades under can realizing equipment on-line state.As shown in Figure 1, described upgrade processing method comprises:
Step 101, by background mode, ROMPaq to be loaded in the flash memory of CPLD.
Particularly, the ROMPaq of CPLD is loaded in the flash memory Flash of CPLD by background mode by upgrading processing device.Wherein, by background mode, the ROMPaq of CPLD is loaded in the Flash of CPLD, the normal work of CPLD can be ensured.In the embodiment of the present invention, described upgrading processing device can be specialized equipment, also can be arranged in an equipment with described CPLD, as long as can realize the technical scheme of the embodiment of the present invention, be not construed as limiting this embodiment of the present invention.
Step 102, the register information backing up described CPLD and pin signal.
The register information of CPLD and pin signal backup in the storage unit of described upgrading processing device by upgrading processing device.
Step 103, lock the pin of described CPLD.
The pin status of upgrading processing device locking current C PLD.
Step 104, the described ROMPaq in the flash memory of described CPLD to be loaded in the static RAM SRAM of described CPLD.
The ROMPaq of CPLD is loaded into static RAM (StaticRandom-AccessMemory, abbreviation: run SRAM), complete the upgrading of CPLD in CPLD by upgrading processing device from the Flash in CPLD.
Step 105, according to the register information of described CPLD of backup and pin signal recuperation the register information of CPLD and pin signal.
After CPLD upgrading, also need the register information before recovering CPLD upgrading and pin signal.Upgrading processing device by the register information of CPLD of backup in step 102 and pin signal, the register information of the CPLD namely before upgrading and pin signal recuperation to current, that is, in the CPLD after upgrading.Register information before such CPLD upgrading and pin signal upgrade with CPLD after register information and pin signal be consistent, thus the equipment that can ensure is before CPLD upgrading and the consistance of rear state of upgrading.
Step 106, after completing the register information and pin signal recovering described CPLD, discharge the pin of described CPLD.
After completing the register information and pin signal recovering described CPLD, the pin of the described CPLD that the release of upgrading processing device is locked, the signal that the pin of described CPLD is exported is consistent with the signal that the pin of described CPLD before the described CPLD of upgrading exports.For example, before the program of upgrading CPLD, the pin signal of CPLD is high level, pin signal is backed up, after the program of upgrading CPLD, due to the pin signal of pin signal recuperation CPLD according to backup, the control signal on the pin of the CPLD after upgrading like this can not saltus step, is still high level.
Before above-mentioned steps 101, described method also comprises: (SerialVectorFormat, is called for short: SVF) file, adds backup command word and recover command word in described SVF file to generate serial vector format; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word is used to indicate the register information and pin signal that back up described CPLD, and described recovery command word is used to indicate the register information and pin signal that recover described CPLD.
Particularly, SVF file described in the schema creation that upgrading processing device loads with backstage, the primary importance in described SVF file adds described backup command word, adds described recovery command word in the second place.Described primary importance is before the pin status of the described CPLD of locking; After the described second place is run in the SRAM ROMPaq of described CPLD being loaded into described CPLD, and before the pin of the described CPLD of release.
Described flash memory ROMPaq being loaded into CPLD by background mode comprises: by background mode by described SVF files loading in the flash memory of described CPLD, (English: In-SystemProgrammingVitualMachineEmbedded according to described SVF file generated embedded on-line system programming virtual machine, be called for short: ispVME) data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
When being resolved to the backup command word in ispVME data file when upgrading processing device, enter backup flow process, perform backup current, the register information of the described CPLD namely before upgrading and pin signal, i.e. step 102.When being resolved to the recovery command word in ispVME data file when upgrading processing device, enter recovery flow process, perform by the register information of the described CPLD of above-mentioned backup and pin signal recuperation to current, in the register information of the described CPLD after namely upgrading and pin signal, i.e. step 105.Described like this SVF file just can indicate the escalation process of described CPLD to perform according to above-mentioned steps 101 ~ 106.
In the present embodiment, after by background mode the ROMPaq of CPLD being loaded in the Flash of CPLD, the register information of backup CPLD and pin signal, and then the ROMPaq in the Flash of CPLD is loaded in the SRAM of CPLD, at this moment the pin of CPLD is not discharged immediately, but first by the register information of the CPLD of above-mentioned backup and pin signal recuperation in described CPLD, register information and the pin signal of the CPLD before making upgrading and after upgrading are consistent, the last pin discharging described CPLD again, complete the upgrading processing of CPLD, with the consistance of rear equipment state of upgrading before CPLD upgrading can be ensured, the business of current system can not be interrupted, avoid producing business impacting, improve the reliability of system.
Because the ROMPaq of CPLD to be loaded in the Flash of CPLD consuming time longer by background mode by upgrading processing device, during this period of time upgrading processing device cannot operate current CPLD, if backed up register information and the pin signal of CPLD be loaded in the Flash of CPLD in the ROMPaq of CPLD before, so likely to be loaded in the Flash of CPLD the output signal of CPLD during this period of time in the ROMPaq of CPLD can change, thus cause front and after upgrading the output signal of CPLD upgrading inconsistent, so after ROMPaq being loaded in the Flash of CPLD, carry out the register information and the pin signal that back up CPLD again.Because consuming time very short to the register information and this process of pin signal recovering CPLD from the register information and pin signal backing up CPLD, so just can further ensure like this CPLD before upgrading with upgrade after state consistency, make system more stable.
The structural representation of a kind of upgrading processing device that Fig. 2 provides for the embodiment of the present invention, for described CPLD place equipment, such as, in equipment running process, do not interrupt the normal work of CPLD, under needing the scene to the program upgrade of described CPLD, the operation of the CPLD that upgrades under can realizing equipment on-line state.As shown in Figure 2, the upgrading processing device 01 of the CPLD of the present embodiment can comprise: load-on module 011, backup module 012, locking module 013, recovery module 014, release module 015.
Concrete, load-on module 011, for being loaded into ROMPaq in the flash memory of CPLD by background mode.
Backup module 012, for backing up register information and the pin signal of described CPLD.
Locking module 013, for locking the pin of described CPLD.
Described load-on module 011, also for the described ROMPaq in the flash memory of described CPLD being loaded in the static RAM SRAM of described CPLD.
Recover module 014, for register information and the pin signal of CPLD according to the register information of described CPLD of backup and pin signal recuperation.
Release module 015, for after completing the register information and pin signal recovering described CPLD, discharges the pin of described CPLD.
Further, described upgrading processing device 01 also comprises: generation module 016.
Concrete, generation module 016, for generating serial vector format SVF file, adding backup command word and recovering command word in described SVF file; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
Described load-on module 011, specifically for by background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
Described backup module 012, specifically for when running to described backup command word, backs up register information and the pin signal of described CPLD;
Described recovery module 014, specifically for when running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
The upgrading processing device of the CPLD of the present embodiment, may be used for the technical scheme performing above-mentioned shown embodiment of the method, it realizes principle and technique effect is similar, repeats no more herein.
The structural representation of the another kind of upgrading processing device that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, the upgrading processing device 02 of the present embodiment comprises: processor 021, storer 022, communication interface 023 and bus 024; Described processor 021, described storer 022 and described communication interface 023 are interconnected by described bus 024.
Above-mentioned storer 022, for depositing program.Particularly, program can comprise program code, and described program code comprises computer-managed instruction.Storer may comprise random access memory (randomaccessmemory is called for short RAM), still may comprise nonvolatile memory (non-volatilememory), such as at least one magnetic disk memory.
Above-mentioned processor 021 can be general processor, comprises central processing unit (CentralProcessingUnit is called for short CPU), network processing unit (NetworkProcessor is called for short NP) etc.; Can also be digital signal processor (DSP), special IC (ASIC), field programmable gate array (FPGA) or other programmable logic device (PLD).
The program that processor 021 execute store 022 is deposited, for:
By background mode, ROMPaq is loaded in the flash memory of CPLD;
Back up register information and the pin signal of described CPLD;
Lock the pin of described CPLD;
Described ROMPaq in the flash memory of described CPLD is loaded in the static RAM SRAM of described CPLD;
The register information of CPLD and pin signal according to the register information of described CPLD of backup and pin signal recuperation;
After completing the register information and pin signal recovering described CPLD, discharge the pin of described CPLD.
Further, described by background mode ROMPaq is loaded in the flash memory of CPLD before, described program also comprises:
For generating serial vector format SVF file, in described SVF file, adding backup command word and recover command word; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
Described flash memory ROMPaq being loaded into described CPLD by background mode comprises: by background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
Register information and the pin signal of the described CPLD of described backup comprise: when running to described backup command word, back up register information and the pin signal of described CPLD;
According to the register information of described CPLD of backup and pin signal recuperation, the register information of CPLD and pin signal comprise: when running to described recovery command word, with register information and the pin signal of CPLD described in the register information of the described CPLD of backup and pin signal recuperation.
The upgrading processing device 02 of the present embodiment can be specialized equipment, also can be arranged in an equipment with described CPLD, and for performing the technical scheme of above-mentioned shown embodiment of the method, it realizes principle and technique effect is similar, repeats no more herein.
The structural representation of the upgrading processing system that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, the system of the present embodiment comprises: upgrading processing device 400 and CPLD401.Wherein, described upgrading processing device 400 is as shown in Fig. 2 or Fig. 3 of the present invention, for performing the technical scheme in Fig. 1 described in embodiment, it realizes principle and technique effect see described in embodiment of the method shown in above-mentioned Fig. 1 and Fig. 2 and Fig. 3 shown device embodiment, can repeat no more herein.
One of ordinary skill in the art will appreciate that: all or part of step realizing above-mentioned each embodiment of the method can have been come by the hardware that programmed instruction is relevant.Aforesaid program can be stored in a computer read/write memory medium.This program, when performing, performs the step comprising above-mentioned each embodiment of the method; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a upgrade processing method, is characterized in that, comprising:
By background mode, ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD);
Back up register information and the pin signal of described CPLD;
Lock the pin of described CPLD;
Described ROMPaq in the flash memory of described CPLD is loaded in the static RAM SRAM of described CPLD;
The register information of CPLD and pin signal according to the register information of described CPLD of backup and pin signal recuperation;
After completing the register information and pin signal recovering described CPLD, discharge the pin of described CPLD.
2. method according to claim 1, is characterized in that, described by background mode ROMPaq is loaded in the flash memory of CPLD before, described method also comprises:
Generate serial vector format SVF file, in described SVF file, add backup command word and recover command word; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
3. method according to claim 2, is characterized in that, described flash memory ROMPaq being loaded into CPLD by background mode comprises:
By background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
4. according to the method in claim 2 or 3, it is characterized in that, register information and the pin signal of the described CPLD of described backup comprise:
When running to described backup command word, back up register information and the pin signal of described CPLD;
According to the register information of described CPLD of backup and pin signal recuperation, the register information of CPLD and pin signal comprise:
When running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
5. a upgrading processing device, is characterized in that, comprising:
Load-on module, for being loaded in the flash memory of complex programmable logic device (CPLD) by background mode by ROMPaq;
Backup module, for backing up register information and the pin signal of described CPLD;
Locking module, for locking the pin of described CPLD;
Described load-on module, also for being loaded in the static RAM SRAM of described CPLD by the described ROMPaq in the flash memory of described CPLD;
Recover module, for register information and the pin signal of CPLD according to the register information of described CPLD of backup and pin signal recuperation;
Release module, for after completing the register information and pin signal recovering described CPLD, discharges the pin of described CPLD.
6. device according to claim 5, is characterized in that, described device also comprises:
Generation module, for generating serial vector format SVF file, adding backup command word and recovering command word in described SVF file; Wherein, described SVF file is used to indicate the upgrade process of described CPLD, described backup command word, is used to indicate the register information and pin signal that back up described CPLD, described recovery command word, is used to indicate the register information and pin signal that recover described CPLD.
7. device according to claim 6, is characterized in that,
Described load-on module, specifically for by background mode by described SVF files loading in the flash memory of described CPLD, according to described SVF file generated embedded on-line system programming virtual machine ispVME data file, and perform described ispVME data file; Wherein, described ispVME data file is for performing the upgrading processing of described CPLD, and described ispVME data file comprises described backup command word and described recovery command word.
8. the device according to claim 6 or 7, is characterized in that,
Described backup module, specifically for when running to described backup command word, backs up register information and the pin signal of described CPLD;
Described recovery module, specifically for when running to described recovery command word, with register information and the pin signal of CPLD described in the register information of described CPLD of backup and pin signal recuperation.
9. a upgrading processing system, for the upgrading to complex programmable logic device (CPLD), is characterized in that, comprising: CPLD and upgrading processing device, and described upgrading processing device adopts the upgrading processing device according to any one of claim 5 ~ 8.
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| CN110442365A (en) * | 2019-07-26 | 2019-11-12 | 锐捷网络股份有限公司 | The upgrade method and device of programmable logic device |
| CN111158734A (en) * | 2019-12-29 | 2020-05-15 | 苏州浪潮智能科技有限公司 | Seamless upgrading method, system and equipment for CPLD-FPGA |
| CN113741928A (en) * | 2021-07-25 | 2021-12-03 | 苏州浪潮智能科技有限公司 | Firmware upgrading method and system of logic device based on I2C |
| CN113821240A (en) * | 2021-09-03 | 2021-12-21 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic equipment, storage medium and signal latch circuit |
| CN116932009A (en) * | 2023-09-13 | 2023-10-24 | 合肥康芯威存储技术有限公司 | Method, device and medium for upgrading field firmware of storage device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1987787A (en) * | 2006-12-06 | 2007-06-27 | 华为技术有限公司 | Method and system for on-line upgrading logic device |
| CN101770376A (en) * | 2008-12-31 | 2010-07-07 | 华为技术有限公司 | Software updating method and control device |
| US7772881B1 (en) * | 2006-09-29 | 2010-08-10 | Altera Corporation | Method and apparatus for in-system programmability |
-
2014
- 2014-09-03 CN CN201410446645.8A patent/CN105468387A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7772881B1 (en) * | 2006-09-29 | 2010-08-10 | Altera Corporation | Method and apparatus for in-system programmability |
| CN1987787A (en) * | 2006-12-06 | 2007-06-27 | 华为技术有限公司 | Method and system for on-line upgrading logic device |
| CN101770376A (en) * | 2008-12-31 | 2010-07-07 | 华为技术有限公司 | Software updating method and control device |
Non-Patent Citations (1)
| Title |
|---|
| LATTICE: "Programming Tools User Guide", 《 HTTP://WWW.LATTICE.COM/~/MEDIA/LATTICESEMI/DOCUMENTS/USERMANUALS/MQ/PROGRAMMINGTOOLSUSERGUIDE31.PDF?DOCUMENT_ID=50445》 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019084916A1 (en) * | 2017-11-03 | 2019-05-09 | 华为技术有限公司 | Method and system for recovering logic in fpga chip, and fpga apparatus |
| CN110109694A (en) * | 2019-04-28 | 2019-08-09 | 新华三技术有限公司 | Device pin control method and programmable logic device |
| CN110109694B (en) * | 2019-04-28 | 2023-04-07 | 新华三技术有限公司 | Device pin control method and programmable logic device |
| CN110442365A (en) * | 2019-07-26 | 2019-11-12 | 锐捷网络股份有限公司 | The upgrade method and device of programmable logic device |
| CN111158734A (en) * | 2019-12-29 | 2020-05-15 | 苏州浪潮智能科技有限公司 | Seamless upgrading method, system and equipment for CPLD-FPGA |
| CN113741928A (en) * | 2021-07-25 | 2021-12-03 | 苏州浪潮智能科技有限公司 | Firmware upgrading method and system of logic device based on I2C |
| CN113741928B (en) * | 2021-07-25 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Firmware upgrading method and system of logic device based on I2C |
| CN113821240A (en) * | 2021-09-03 | 2021-12-21 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic equipment, storage medium and signal latch circuit |
| CN113821240B (en) * | 2021-09-03 | 2023-11-17 | 锐捷网络股份有限公司 | Firmware upgrading method, electronic device, storage medium and signal latch circuit |
| CN116932009A (en) * | 2023-09-13 | 2023-10-24 | 合肥康芯威存储技术有限公司 | Method, device and medium for upgrading field firmware of storage device |
| CN116932009B (en) * | 2023-09-13 | 2024-01-23 | 合肥康芯威存储技术有限公司 | Method, device and medium for upgrading field firmware of storage device |
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