CN106610844A - Upgrading processing method - Google Patents
Upgrading processing method Download PDFInfo
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- CN106610844A CN106610844A CN201510695749.7A CN201510695749A CN106610844A CN 106610844 A CN106610844 A CN 106610844A CN 201510695749 A CN201510695749 A CN 201510695749A CN 106610844 A CN106610844 A CN 106610844A
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- cpld
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- pin signal
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Abstract
An embodiment of the invention provides an upgrading processing method. The upgrading processing method comprises the steps of loading an upgrading program to a flash memory of a complex programmable logic device (CPLD) through a background pattern; performing backup on register information and a pin signal of the CPLD; locking a pin of the CPLD; loading the upgrading program in the flash memory of the CPLD to a static random-access memory (SRAM) of the CPLD; and recovering the register information and the pin signal of the CPLD according to the backuped register information and pin signal of the CPLD to complete the upgrading processing of the CPLD. Consistency of equipment states of the CPLD before upgrading and after upgrading can be ensured without interrupting the current system service, so that impact to the service is avoided, and system reliability is improved.
Description
Technical field
The present invention relates to communication technical field, more particularly to a kind of upgrade processing method.
Background technology
CPLD (complex programmable logic device, referred to as：
CPLD it is) a kind of digital integrated electronic circuit according to user's request constitutive logic function, widely should
For in various communication network devices.With the reliability to equipment, security requirement more and more higher,
If CPLD operationally goes wrong, or user's request change, then need to upgrade CPLD's
Program.But, the pin of CPLD can be discharged after the program of CPLD of generally having upgraded, so may be used
There is saltus step in the pin signal that can cause CPLD before and after upgrading, before and after causing CPLD places equipment
State differs, and needs ensure the concordance of state before and after upgrading by resetting, so as to cause equipment to be worked as
Front service disconnection.It is key signal in the event of the signal of saltus step, the control signal of such as equipment is used
The function of some Service Processing Modules on control device, it is possible to affect the business of whole equipment.
The content of the invention
The embodiment of the present invention provides a kind of upgrade processing method, it is not necessary to interrupt the current business of system, can
With ensure CPLD upgrading before with upgrading after equipment state concordance.Avoid producing impact to business, carry
The high reliability of system.
The embodiment of the present invention provides a kind of upgrade processing method, including：
ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD) by background mode；
Back up the register information and pin signal of the CPLD；
Lock the pin of the CPLD；
The static random that the ROMPaq in the flash memory of the CPLD is loaded into the CPLD is deposited
In reservoir SRAM；
The deposit of the CPLD is recovered according to the register information and pin signal of the CPLD of backup
Device information and pin signal.
Method as above, wherein, ROMPaq is loaded into by CPLD by background mode described
Flash memory in before, methods described also includes：
Serial vector format SVF files are generated, backup command word and recovery are added in the SVF files
Command word；Wherein, the SVF files are used to indicate the upgrade process of the CPLD, described standby
Part command word, for indicating the register information and pin signal of the backup CPLD, the recovery life
Word is made, for indicating to recover the register information and pin signal of the CPLD.
Method as above, wherein, it is described that ROMPaq is loaded into into CPLD's by background mode
Flash memory includes：
The SVF files are loaded in the flash memory of the CPLD, according to described by background mode
The embedded on-line system of SVF file generateds programs virtual machine ispVME data files, and performs described
IspVME data files；Wherein, the ispVME data files are used to perform the upgrading of the CPLD
Process, the ispVME data files include the backup command word and the recovery command word.
Method as above, wherein, the register information and pin signal for backing up the CPLD
Including：
When the backup command word is run to, the register information and pin signal of the CPLD is backed up；
The register information and pin signal of the CPLD according to backup recovers the CPLD's
Register information and pin signal include：
When the recovery command word is run to, with the register information and pin of the CPLD of backup
Signal recovers the register information and pin signal of the CPLD.
Method as above, wherein, the register information and pin for completing to recover the CPLD
After signal, also include：Discharge the pin of the CPLD.
The upgrade processing method of the CPLD that the present invention is provided, is loaded into ROMPaq by background mode
In the flash memory of complex programmable logic device (CPLD)；Back up the register information and pin of the CPLD
Signal；Lock the pin of the CPLD；The ROMPaq in the flash memory of the CPLD is loaded
To in the SRAM SRAM of the CPLD；According to the depositor of the CPLD of backup
Information and pin signal recover the register information and pin signal of the CPLD, complete the liter of CPLD
Level is processed, it is ensured that before CPLD upgradings with upgrading after equipment state concordance, will not interrupt current
The business of system, it is to avoid impact is produced to business, the reliability of system is improve.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to reality
Apply the accompanying drawing to be used needed for example or description of the prior art to be briefly described, it should be apparent that, under
Accompanying drawing in the description of face is some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative labor, can be with according to these other accompanying drawings of accompanying drawings acquisition.
Fig. 1 is the flow chart of upgrade processing method provided in an embodiment of the present invention.
Specific embodiment
To make purpose, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with this
Accompanying drawing in bright embodiment, is clearly and completely described to the technical scheme in the embodiment of the present invention,
Obviously, described embodiment is a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made
The every other embodiment for obtaining, belongs to the scope of protection of the invention.
Fig. 1 is the flow chart of upgrade processing method provided in an embodiment of the present invention, can be used for the CPLD
In the equipment running process of place, the normal work of CPLD is not interrupted, need the program to the CPLD
Under the scene of upgrading, it is possible to achieve the operation of the CPLD that upgrades under equipment on-line state.As shown in figure 1,
The upgrade processing method includes：
Step 101, ROMPaq is loaded in the flash memory of CPLD by background mode.
Specifically, the ROMPaq of CPLD can be loaded into CPLD by upgrading processing device by background mode
Flash memory Flash in.Wherein, the ROMPaq of CPLD is loaded into into CPLD's by background mode
In Flash, it is ensured that the normal work of CPLD.In the embodiment of the present invention, the upgrading processing device
Can be special equipment, it is also possible to be located in an equipment, as long as the present invention can be realized with the CPLD
The technical scheme of embodiment, is not construed as limiting to this embodiment of the present invention.
Step 102, the register information and pin signal that back up the CPLD.
The register information of CPLD and pin signal are backuped to the upgrading processing dress by upgrading processing device
In the memory element put.
Step 103, the pin for locking the CPLD.
Upgrading processing device locks the pin status of current CPLD.
Step 104, the ROMPaq in the flash memory of the CPLD is loaded into into the CPLD's
In SRAM.
Upgrading processing device is loaded into CPLD in the Flash by the ROMPaq of CPLD from CPLD
Interior SRAM (Static Random-Access Memory, abbreviation：SRAM operation in),
Complete the upgrading of CPLD.
Step 105, according to backup the CPLD register information and pin signal recover described in
The register information and pin signal of CPLD.
After CPLD upgradings, in addition it is also necessary to recover register information and pin signal before CPLD upgradings.
Upgrading processing device upgrades the register information and pin signal of the CPLD backed up in step 102
The register information and pin signal of front CPLD is returned to currently, i.e. in the CPLD after upgrading.
The register information after register information and pin signal and CPLD upgrading before so CPLD upgradings and
Pin signal is consistent, thereby may be ensured that equipment CPLD upgrading before with upgrade after state it is consistent
Property.
Further, after the register information and pin signal that complete to recover the CPLD, release
The pin of the CPLD.
After the register information and pin signal that complete to recover the CPLD, upgrading processing device is released
The pin of the locked CPLD is put, makes the signal that the pin of the CPLD is exported described with upgrading
The signal of the pin output of CPLD as described before CPLD is consistent.For example, upgrading CPLD's
Before program, the pin signal of CPLD is high level, and pin signal is backed up, in upgrading CPLD
Program after, due to according to backup pin signal recover CPLD pin signal, so upgrading after
CPLD pin on control signal will not saltus step, be still high level.
Before above-mentioned steps 101, methods described also includes：Generate serial vector format (Serial Vector
Format, referred to as：SVF) file, backup command word is added in the SVF files and recovers order
Word；Wherein, the SVF files are used to indicate the upgrade process of the CPLD, the backup life
Make word for indicate the backup CPLD register information and pin signal, the recovery command word use
In the register information and pin signal that indicate to recover the CPLD.
Specifically, SVF files described in the schema creation that upgrading processing device is loaded with backstage, in the SVF
First position in file adds the backup command word, and in the second position recovery command word is added.
The first position is before the pin status of the CPLD are locked；The second position is will be described
The ROMPaq of CPLD is loaded in the SRAM of the CPLD after operation, and described in release
Before the pin of CPLD.
It is described to be included the flash memory that ROMPaq is loaded into CPLD by background mode：By backstage mould
Formula is loaded into the SVF files in the flash memory of the CPLD, embedding according to the SVF file generateds
Enter formula on-line system programming virtual machine (English：In-System Programming Vitual Machine
Embedded, referred to as：IspVME) data file, and perform the ispVME data files；Wherein,
The ispVME data files are used to perform the upgrading processing of the CPLD, the ispVME data
File includes the backup command word and the recovery command word.
When upgrading processing device is resolved to the backup command word in ispVME data files, into backup
Flow process, performs the register information and pin signal of the CPLD that backup is current, that is, before upgrading, i.e.,
Step 102.When upgrading processing device is resolved to the recovery command word in ispVME data files, enter
Recover flow process, perform to return to the register information and pin signal of the CPLD of above-mentioned backup and work as
Before, that is, in the register information and pin signal of the CPLD after upgrading, i.e. step 105.So
The SVF files can just indicate that the escalation process of the CPLD is performed according to above-mentioned steps 101～105.
In the present embodiment, the ROMPaq of CPLD is loaded into by background mode for the Flash of CPLD
In after, back up CPLD register information and pin signal, then again by the Flash of CPLD
ROMPaq be loaded in the SRAM of CPLD, at this moment not immediately discharge CPLD pin, and
It is first the register information of the CPLD of above-mentioned backup and pin signal to be returned in the CPLD, makes
Upgrading before with upgrade after CPLD register information and pin signal be consistent, institute is finally discharged again
The pin of CPLD is stated, the upgrading processing of CPLD is completed, it is ensured that before CPLD upgradings and after upgrading
The concordance of equipment state, will not interrupt the business of current system, it is to avoid produce impact to business, improve
The reliability of system.
Because the ROMPaq of CPLD is loaded into CPLD's by upgrading processing device by background mode
Time-consuming longer in Flash, during this period of time upgrading processing device is that current CPLD cannot be grasped
Make, if backing up CPLD's before the ROMPaq of CPLD is loaded in the Flash of CPLD
Register information and pin signal, are so possible to be loaded into CPLD's in the ROMPaq of CPLD
The output signal of CPLD can change in this period in Flash, so as to cause CPLD upgrading before with
Output signal after upgrading is inconsistent, so after ROMPaq is loaded in the Flash of CPLD,
Carry out again backing up the register information and pin signal of CPLD.Because from the depositor letter of backup CPLD
Breath and pin signal are to the register information and time-consuming very short, the institute of this process of pin signal for recovering CPLD
With thus can further ensure CPLD before upgrading with upgrading after state consistency, make be
System is more stable.
One of ordinary skill in the art will appreciate that：Realize all or part of step of above-mentioned each method embodiment
Suddenly can be completed by the related hardware of programmed instruction.Aforesaid program can be stored in a computer can
In reading storage medium.The program upon execution, performs the step of including above-mentioned each method embodiment；And
Aforesaid storage medium includes：ROM, RAM, magnetic disc or CD etc. are various can be with store program codes
Medium.
Finally it should be noted that：Various embodiments above is only illustrating technical scheme rather than right
Its restriction；Although being described in detail to the present invention with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It still can modify to the technical scheme described in foregoing embodiments,
Either equivalent is carried out to which part or all technical characteristic；And these modifications or replacement, and
The scope of the essence disengaging various embodiments of the present invention technical scheme of appropriate technical solution is not made.
Claims (5)
1. a kind of upgrade processing method, it is characterised in that include：
ROMPaq is loaded in the flash memory of complex programmable logic device (CPLD) by background mode；
Back up the register information and pin signal of the CPLD；
Lock the pin of the CPLD；
The static random that the ROMPaq in the flash memory of the CPLD is loaded into the CPLD is deposited
In reservoir SRAM；
The deposit of the CPLD is recovered according to the register information and pin signal of the CPLD of backup
Device information and pin signal.
2. method according to claim 1, it is characterised in that will be risen by background mode described
Before level program is loaded in the flash memory of CPLD, methods described also includes：
Serial vector format SVF files are generated, backup command word and recovery are added in the SVF files
Command word；Wherein, the SVF files are used to indicate the upgrade process of the CPLD, described standby
Part command word, for indicating the register information and pin signal of the backup CPLD, the recovery life
Word is made, for indicating to recover the register information and pin signal of the CPLD.
3. method according to claim 2, it is characterised in that described to be upgraded by background mode
Program is loaded into the flash memory of CPLD to be included：
The SVF files are loaded in the flash memory of the CPLD, according to described by background mode
The embedded on-line system of SVF file generateds programs virtual machine ispVME data files, and performs described
IspVME data files；Wherein, the ispVME data files are used to perform the upgrading of the CPLD
Process, the ispVME data files include the backup command word and the recovery command word.
4. according to the method in claim 2 or 3, it is characterised in that described to back up the CPLD
Register information and pin signal include：
When the backup command word is run to, the register information and pin signal of the CPLD is backed up；
The register information and pin signal of the CPLD according to backup recovers the CPLD's
Register information and pin signal include：
When the recovery command word is run to, with the register information and pin of the CPLD of backup
Signal recovers the register information and pin signal of the CPLD.
5. method according to claim 1, it is characterised in that described to complete to recover the CPLD
Register information and pin signal after, also include：Discharge the pin of the CPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510695749.7A CN106610844A (en) | 2015-10-22 | 2015-10-22 | Upgrading processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510695749.7A CN106610844A (en) | 2015-10-22 | 2015-10-22 | Upgrading processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106610844A true CN106610844A (en) | 2017-05-03 |
Family
ID=58613568
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510695749.7A Pending CN106610844A (en) | 2015-10-22 | 2015-10-22 | Upgrading processing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110109694A (en) * | 2019-04-28 | 2019-08-09 | 新华三技术有限公司 | Device pin control method and programmable logic device |
| CN111158734A (en) * | 2019-12-29 | 2020-05-15 | 苏州浪潮智能科技有限公司 | Seamless upgrading method, system and equipment for CPLD-FPGA |
-
2015
- 2015-10-22 CN CN201510695749.7A patent/CN106610844A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110109694A (en) * | 2019-04-28 | 2019-08-09 | 新华三技术有限公司 | Device pin control method and programmable logic device |
| CN110109694B (en) * | 2019-04-28 | 2023-04-07 | 新华三技术有限公司 | Device pin control method and programmable logic device |
| CN111158734A (en) * | 2019-12-29 | 2020-05-15 | 苏州浪潮智能科技有限公司 | Seamless upgrading method, system and equipment for CPLD-FPGA |
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Application publication date: 20170503 |