CN111208891B - CPLD updating system and method - Google Patents
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Abstract
The application discloses a CPLD updating system and a method, comprising the following steps: the BMC sends out an asynchronous reset signal and updates the CPLD when receiving the CPLD updating instruction, and sends out a latch enable signal and a power supply shutdown restart signal when receiving the CPLD updating restart instruction; the power module receives a power-off restarting signal; the clock signal end and the D signal end are both connected with the output end of the power supply module and receive a D trigger of the asynchronous reset signal; the state display unit is connected with the D trigger; the enable signal terminal receives the latch of the latch enable signal. The updating state of the CPLD is prompted to the outside through the D trigger and the state display unit, the CPLD is controlled to be restarted after configuration updating by sending a shutdown and restart signal to the power module through the BMC, and meanwhile, the level of a controlled terminal is not affected in the CPLD updating process through the latch, so that the CPLD can be updated timely and effectively, and the updating efficiency is improved.
Description
Technical Field
The invention relates to the field of server hardware, in particular to a CPLD updating system and a CPLD updating method.
Background
On a server motherboard, functions such as on/off timing control, key debounce, signal delay, and indicator light control are often implemented by integrating a CPLD (Complex Programmable Logic Device) chip. Due to the reasons of new function introduction, legacy problem repair and the like, the CPLD needs to be updated when the server runs, and the BMC (Baseboard management Controller) receives JTAG (Joint Test Action Group) or I2C (Inter-Integrated Circuit bus) signals to the CPLD to update the configuration of the CPLD.
Two modes are mainly adopted for updating the CPLD, and in the first mode, after the configuration is updated, the configuration information takes effect immediately; in the second mode, the configuration information is stored in the CPLD built-in flash and is regenerated after the CPLD is started. The first mode has the disadvantage that when the CPLD is updated in the power-on state, the interface output level of the CPLD may change, which may adversely affect the system function. The second mode avoids this problem, but requires a reboot to power up the CPLD again to enable the configuration to take effect. Sometimes, the server runs business, and is inconvenient to restart, and when the server is in a non-business state, the server is restarted by a worker. The system has no indication that the server needs to be restarted to enable the configuration to be effective currently, and if the operator forgets to restart the server, the configuration cannot be enabled to be effective for a long time because the CPLD is not restarted after the CPLD is possibly updated.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a CPLD updating system and method. The specific scheme is as follows:
a CPLD update system, comprising:
the BMC sends out an asynchronous reset signal and updates the CPLD when receiving the CPLD updating instruction, and sends out a latch enable signal and a power supply shutdown restart signal when receiving the CPLD updating restart instruction;
the power supply module is connected with the CPLD at the output end and receives the power supply turn-off and restart signal;
the clock signal end and the D signal end are both connected with the output end of the power supply module and receive the D trigger of the asynchronous reset signal;
the state display unit is connected with the Q output end of the D trigger;
the enabling signal end receives the latch enabling signal, the signal input end is connected with the control signal output end of the CPLD, and the signal output end is connected with the latch of the controlled terminal.
Preferably, the state display unit is specifically an indicator light and/or a buzzer.
Preferably, the CPLD update restart instruction is an instruction generated for receiving a feedback signal after the CPLD completes updating.
Preferably, the power supply module includes:
a switch unit controlled by the BMC;
the output end of the power supply is controlled by the switch unit to output voltage;
preferably, the switch unit is specifically configured to:
and when the power supply shutdown restart signal is received, controlling the power supply to stop voltage output, and after waiting for a first preset time, controlling the power supply to output voltage again.
Preferably, the BMC is further configured to:
and when the power supply module is restarted and waits for a second preset time, stopping sending the latch enabling signal.
Correspondingly, the invention also discloses a CPLD updating method, which is applied to any one of the CPLD updating systems, and comprises the following steps:
when receiving a CPLD updating instruction, sending an asynchronous reset signal to a D trigger so as to enable a state display unit to display a state being updated;
when a CPLD updating restart instruction is received, a latch enabling signal is sent to a latch so that the latch temporarily stores the current control signal of the CPLD and sends the current control signal to a controlled terminal, and a power supply shutdown restart signal is sent to a power supply module so that the power supply module is restarted after being shut down for a first preset time.
Preferably, the CPLD updating method further includes:
and when the power supply module is restarted and waits for a second preset time, stopping sending the latch enabling signal.
The application discloses CPLD updates system includes: the BMC sends out an asynchronous reset signal and updates the CPLD when receiving the CPLD updating instruction, and sends out a latch enable signal and a power supply shutdown restart signal when receiving the CPLD updating restart instruction; the power supply module is connected with the CPLD at the output end and receives the power supply turn-off and restart signal; the clock signal end and the D signal end are both connected with the output end of the power supply module and receive the D trigger of the asynchronous reset signal; the state display unit is connected with the Q output end of the D trigger; the enabling signal end receives the latch enabling signal, the signal input end is connected with the control signal output end of the CPLD, and the signal output end is connected with the latch of the controlled terminal. The updating state of the CPLD is prompted to the outside through the D trigger and the state display unit, the CPLD is controlled to be restarted after configuration updating by sending a shutdown and restart signal to the power module through the BMC, and meanwhile, the level of a controlled terminal is not affected in the CPLD updating process through the latch, so that the CPLD can be updated timely and effectively, and the updating efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural distribution diagram of a CPLD updating system according to an embodiment of the present invention;
fig. 2 is a flowchart illustrating steps of a CPLD updating method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The current CPLD is updated in two ways, namely, the CPLD is updated in a starting state and takes effect immediately, and the interface input level of the CPLD is possibly changed in the process, so that adverse effects are generated on a system; secondly, the configuration information is temporarily stored in the built-in flash of the CPLD, and the next boot becomes effective, and the method can be effective only by manually restarting the CPLD. The method and the device utilize the state display unit to prompt the update state of the CPLD to the outside, restart the CPLD by controlling the power module through the BMC, and simultaneously ensure that the level of the controlled terminal is not influenced in updating by utilizing the latch, thereby ensuring that the update of the CPLD is effective immediately.
The embodiment of the invention discloses a CPLD updating system, which is shown in figure 1 and comprises the following components:
the BMC 2 is used for sending out an asynchronous reset signal and updating the CPLD 1 when receiving a CPLD updating instruction, and sending out a latch enable signal and a power supply shutdown restart signal when receiving a CPLD updating restart instruction;
the power module 3 is connected with the CPLD 1 at the output end and receives a power supply shutdown restart signal;
the clock signal end and the D signal end are both connected with the output end of the power module 3, and the D trigger 4 is used for receiving an asynchronous reset signal;
a state display unit 5 connected to the Q output terminal of the D flip-flop 4;
the enabling signal end receives the latch enabling signal, the signal input end is connected with the control signal output end of the CPLD, and the signal output end is connected with the latch 7 of the controlled terminal 6.
Specifically, the status display unit 5 is specifically an indicator light and/or a buzzer.
It is understood that the power module 3 includes:
a switching unit 31 controlled by the BMC 2;
a power supply 32 whose output terminal is controlled by the switching unit 31 to output a voltage;
further, the switch unit 31 is specifically configured to:
and when a power supply shutdown restart signal is received, controlling the power supply to stop voltage output, and after waiting for a first preset time, controlling the power supply to output voltage again.
Further, BMC 2 is also used to:
and when the power supply module 3 is restarted and waits for the second preset time, stopping sending the latch enabling signal.
Typically, BMC 2 connects JTAG signals to CPLD 1, which may require burning, to support configuration updates to CPLD 1 through JTAG. The BMC 2 is connected with a D trigger 4 with an asynchronous reset function through a GPIO pin, the D trigger 4 connects a clock signal end and a D signal end to the output end of the power module 3, and meanwhile, the power module 3 supplies power for the CPLD 1. The Q output end of the D trigger 4 is connected with the state display unit 5, and the state display unit 5 is used for indicating the output state and feeding back to the BMC 2.
The control signal originally sent by the CPLD 1 directly to the controlled terminal 6 is input to the latch 7, and the control signal is sent to the controlled terminal 6 through the latch 7. The latch control signal of the latch 7 is from the BMC 2, namely when the BMC 2 does not send out the latch control signal, the CPLD 1 can directly send the multi-channel control signal to each controlled terminal 6; when the BMC 2 sends the latch control signal, the control signals received by other controlled terminals 6 keep the previous state unchanged.
The shutdown restart signal of the power module 3 is sent by the BMC 2, and the shutdown restart signal actually includes a shutdown signal and a start signal after a first preset time interval, and since the CPLD 1 and the D trigger 4 are both directly associated with the power supply output of the switch unit 31, the state moments of the CPLD 1 and the D trigger 4 are affected by the power module 3.
When the server normally works, the BMC 2 does not send out an asynchronous reset signal, when the power module 3 is powered on to supply power to the CPLD 1, the D input end and the clock signal end of the D trigger 4 are both high levels, the Q output end also outputs high levels, that is, the Q output end indicates that the CPLD 1 is in a normal working state if the Q output end is high levels, the state display unit 5 does not send out a prompt, and the specific state includes, but is not limited to, indicating modes such as the turning-off of an indicator light, the muting of a buzzer and the like. Meanwhile, the BMC 2 does not send a latch control signal, and the multi-channel control signal output by the CPLD 1 is directly sent to the controlled terminal 6.
When the server needs to update the CPLD 1, the BMC 2 receives the CPLD update instruction, and at this time, the BMC 2 sends an asynchronous reset signal to reset the D trigger 4, so that the output level of the Q output end changes to a low level, the state of the state display unit 5 changes, and the CPLD 1 is prompted to have an update action, and the specific state of the state display unit 5 includes but is not limited to lighting of an indicator light, sounding of a buzzer, and the like.
Then, upgrading is performed through a second mode in the background technology of the application, and a CPLD update restart instruction is sent to the BMC 2 after upgrading is completed, specifically, the CPLD update restart instruction is sent to the power module 3 by the BMC 2, and can be sent after the update of the CPLD 1 is automatically detected, that is, the CPLD update restart instruction is an instruction generated for receiving a feedback signal after the update of the CPLD 1 is completed; or after observing the update state represented by the state display unit 5, the operator may manually send a CPLD update restart instruction to the BMC 2 to control the BMC 2 to send a power shutdown restart signal to the power module 3. Specifically, the power shutdown restart signal includes a shutdown signal and a start signal spaced by a first preset time.
Specifically, the BMC 2 receives a CPLD update restart instruction, sends a latch control signal to the latch 7, and sends a shutdown signal to the power module 3 to power off the CPLD 1; after waiting for the first preset time, sending a starting signal to the power module 3 to electrify the CPLD 1; and waiting for a second preset time to confirm that the output level of the CPLD 1 is not abnormal, and stopping sending the latch enabling signal to enable the CPLD 1 to directly control the controlled terminal 6. When the latch control signal appears, the latch 7 always keeps the control signal sent to the controlled terminal 6 by the last state CPLD 1, and the influence of sudden disappearance or level variation of the control signal on the controlled terminal 6 in the power-down and power-up updating processes of the CPLD 1 is avoided.
Meanwhile, since the D flip-flop 4 is also connected to the power module 3, when the power module 3 is turned off, the D flip-flop 4 is also powered off. After the power module 3 is restarted, the D trigger 4 does not receive the asynchronous reset signal any more, and the D input end is at a high level, so the Q output end is also at a high level, and the state display unit 5 indicates that the CPLD 1 does not have a new updating action currently.
The application discloses CPLD updates system includes: the BMC sends out an asynchronous reset signal and updates the CPLD when receiving the CPLD updating instruction, and sends out a latch enable signal and a power supply shutdown restart signal when receiving the CPLD updating restart instruction; the power module is connected with the CPLD at the output end and receives a power supply turn-off and restart signal; the clock signal end and the D signal end are both connected with the output end of the power supply module and receive a D trigger of the asynchronous reset signal; the state display unit is connected with the Q output end of the D trigger; the enabling signal end receives the latch enabling signal, the signal input end is connected with the control signal output end of the CPLD, and the signal output end is connected with the latch of the controlled terminal. The updating state of the CPLD is prompted to the outside through the D trigger and the state display unit, the CPLD is controlled to be restarted after configuration updating by sending a shutdown and restart signal to the power module through the BMC, and meanwhile, the level of a controlled terminal is not affected in the CPLD updating process through the latch, so that the CPLD can be updated timely and effectively, and the updating efficiency is improved.
Correspondingly, the embodiment of the present invention further discloses a CPLD updating method, which is applied to any one of the CPLD updating systems described above, as shown in fig. 2, and includes:
s1: when receiving a CPLD updating instruction, sending an asynchronous reset signal to a D trigger so as to enable a state display unit to display a state being updated;
s2: when a restarting instruction of updating the CPLD is received, a latch enabling signal is sent to the latch so that the latch temporarily stores the current control signal of the CPLD and sends the current control signal to the controlled terminal, and a power supply shutdown restarting signal is sent to the power supply module so that the power supply module is restarted after being shut down for a first preset time.
Further, this embodiment may further include:
s3: and when the power supply module is restarted and waits for a second preset time, stopping sending the latch enabling signal.
When the server normally works, the BMC cannot send out an asynchronous reset signal, when the power supply module is electrified to supply power to the CPLD, the D input end and the clock signal end of the D trigger are both high levels, the Q output end also outputs high levels, namely the Q output end indicates that the CPLD is in a normal working state if the Q output end is high levels, the state display unit does not send out prompts, and the specific states include but are not limited to indicating modes such as indicator light turning-off, buzzer muting and the like. Meanwhile, the BMC does not send a latch control signal, and the multi-channel control signal output by the CPLD is directly sent to the controlled terminal.
When the server needs to update the CPLD, the BMC receives a CPLD updating instruction, sends an asynchronous reset signal to reset the D trigger, changes the output level of the Q output end into low level, changes the state of the state display unit, prompts the CPLD to have updating action, and the specific state of the state display unit comprises but is not limited to the lightening of an indicator light, the sounding of a buzzer and the like.
Then, upgrading is carried out through a second mode in the background technology of the application, and a CPLD updating and restarting instruction is sent to the BMC after upgrading is finished, specifically, the CPLD updating and restarting instruction is sent to the power module by the BMC, and can be sent after the CPLD updating is automatically detected to be finished, namely the CPLD updating and restarting instruction is an instruction generated after a feedback signal generated after the CPLD is updated; or after observing the update state represented by the state display unit, the operator can manually send a CPLD update restart instruction to the BMC to control the BMC to send a power-off restart signal to the power module. Specifically, the power shutdown restart signal includes a shutdown signal and a start signal spaced by a first preset time.
Specifically, the BMC receives a CPLD update restart instruction, sends a latch control signal to the latch, and sends a turn-off signal to the power module to power off the CPLD; after waiting for the first preset time, sending a starting signal to the power module to electrify the CPLD; and waiting for a second preset time to confirm that the output level of the CPLD is not abnormal, and stopping sending the latch enabling signal to enable the CPLD to directly control the controlled terminal. When the latch control signal appears, the latch always keeps the control signal sent to the controlled terminal by the CPLD in the last state, and the influence of sudden disappearance of the control signal or level variation on the controlled terminal in the power-off and power-on updating processes of the CPLD is avoided.
Meanwhile, the D trigger is also connected to the power supply module, and when the power supply module is turned off, the D trigger is also powered off. After the power module is restarted, the D trigger can not receive the asynchronous reset signal any more, and the D input end is at a high level, so the Q output end is also at a high level, and the state display unit indicates that the current CPLD has no new updating action.
According to the embodiment of the application, the updating state of the CPLD is prompted to the outside through the D trigger and the state display unit, the power module is sent with a shutdown and restart signal through the BMC to control the CPLD to restart after configuration updating, and meanwhile, the level of a controlled terminal in the CPLD updating process is not affected by the latch, so that the CPLD can be updated in time, and the updating efficiency is improved.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The CPLD updating system and method provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (5)
1. A CPLD update system, comprising:
the BMC sends out an asynchronous reset signal and updates the CPLD when receiving the CPLD updating instruction, and sends out a latch enable signal and a power supply shutdown restart signal when receiving the CPLD updating restart instruction; the BMC is further configured to: when the power supply module is restarted and waits for a second preset time, stopping sending the latch enabling signal;
the power supply module is connected with the CPLD at the output end and receives the power supply turn-off and restart signal; the power module includes: a switch unit controlled by the BMC; the output end of the power supply is controlled by the switch unit to output voltage; the switch unit is specifically configured to: when the power supply shutdown restart signal is received, controlling the power supply to stop voltage output, and after waiting for a first preset time, controlling the power supply to output voltage again;
the clock signal end and the D signal end are both connected with the output end of the power supply module and receive the D trigger of the asynchronous reset signal;
the state display unit is connected with the Q output end of the D trigger; if the output level of the Q output end is a high level, the state display unit does not send out a prompt; if the output level of the Q output end is low level, the state display unit sends out a prompt;
the enabling signal end receives the latch enabling signal, the signal input end is connected with the control signal output end of the CPLD, and the signal output end is connected with the latch of the controlled terminal.
2. The CPLD updating system of claim 1, wherein said status display unit is specifically an indicator light and/or a buzzer.
3. The CPLD updating system of claim 1, wherein said CPLD update restart instruction is an instruction generated upon receiving a feedback signal after said CPLD completes updating.
4. A CPLD updating method applied to the CPLD updating system according to any one of claims 1 to 3, comprising:
when receiving a CPLD updating instruction, sending an asynchronous reset signal to a D trigger so as to enable a state display unit to display a state being updated;
when a CPLD updating restart instruction is received, a latch enabling signal is sent to a latch so that the latch temporarily stores the current control signal of the CPLD and sends the current control signal to a controlled terminal, and a power supply shutdown restart signal is sent to a power supply module so that the power supply module is restarted after being shut down for a first preset time.
5. The CPLD updating method according to claim 4, characterized in that it further comprises:
and when the power supply module is restarted and waits for a second preset time, stopping sending the latch enabling signal.
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| TWI768769B (en) * | 2021-03-16 | 2022-06-21 | 英業達股份有限公司 | Server motherboard for single-processor system |
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| CN109976926B (en) * | 2019-03-27 | 2023-01-06 | 苏州浪潮智能科技有限公司 | Method, circuit, terminal and storage medium for shielding, restarting and protecting update process of BMC |
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