CN113127045A - Electronic equipment and CPLD (complex programmable logic device) firmware loading method - Google Patents

Abstract

The application relates to electronic equipment and a CPLD firmware loading method, and belongs to the technical field of computers. The electronic device includes: the processor, the reset delay circuit, the CPLD and the CPLD are respectively connected with the processor and the reset delay circuit. The CPLD is used for determining that the firmware version in the CPLD is refreshed and sending a reset request signal to the processor; the processor is used for responding to the reset request signal to generate a shutdown signal; the CPLD is also used for receiving a shutdown signal and sending a first reset signal to the reset delay circuit; the reset delay circuit is used for carrying out delay preprocessing on the first reset signal to obtain a second reset signal; the CPLD is also used for receiving a second reset signal, resetting and loading and running the updated firmware version after resetting. The method effectively solves the problems that the existing firmware upgrading mode is long in upgrading waiting time and the CPLD updating information is easy to lose.

Description

Electronic equipment and CPLD (complex programmable logic device) firmware loading method

Technical Field

The application belongs to the technical field of computers, and particularly relates to an electronic device and a CPLD firmware loading method.

Background

In a server system, a CPLD (Complex Programmable Logic Device) is usually used as a hardware power-on timing controller, an auxiliary hardware platform management function, and the like in a whole system. The operational stability of the CPLD is an important factor for determining the healthy operation of the entire server system, and therefore, the operation and maintenance (e.g., firmware update) of the CPLD is one of the indispensable and very important links in the server system.

In a traditional server system, the upgrading method of the CPLD firmware is mainly divided into two types. In the first category, firmware upgrade is performed before products are marketed, and as shown in fig. 1, a BMC (Baseboard Management Controller) is connected to a CPLD through a JTAG (Joint Test Action Group) or I2C (Integrated Circuit bus) signal line. The BMC sends an IEEE 1532 refresh command to enable the CPLD to execute the action of loading the firmware. However, the scheme inevitably causes resetting of the IO port of the CPLD while completing loading of the CPLD firmware, thereby causing risks of system reset, power failure and the like which are difficult to predict. Firmware upgrades in this manner are typically only performed before the product is marketed.

And in the second category, firmware upgrading is carried out during the use period of a terminal user, at the moment, a server system is generally in a starting operation state, the BMC performs new version preloading of the CPLD, and after the preloading is completed, the new CPLD version is enabled to take effect by adopting a manual power-off server mode. However, in the process of the server running important services, the user generally does not allow the server to be powered off, so that the upgrade waiting period is long. If the user urgently needs to refresh and validate the version of the CPLD due to some specific factors, if the power is cut off forcibly, situations such as BMC burning or loss of CPLD update information may occur, so that the service processing requirement and the validation requirement of the CPLD version of the user cannot be met at the same time.

Disclosure of Invention

In view of this, an object of the present application is to provide an electronic device and a CPLD firmware loading method, so as to solve the problems that the upgrade latency of the existing firmware upgrade method is long and the CPLD update information is easily lost.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides an electronic device, including: the device comprises a processor, a reset delay circuit and a CPLD, wherein the CPLD is respectively connected with the processor and the reset delay circuit; the CPLD is used for determining that the firmware version in the CPLD is refreshed and sending a reset request signal to the processor; the processor is used for responding to the reset request signal to generate a shutdown signal; the CPLD is also used for receiving the shutdown signal and sending a first reset signal to the reset delay circuit; the reset delay circuit is used for carrying out delay preprocessing on the first reset signal to obtain a second reset signal; and the CPLD is also used for receiving the second reset signal, resetting and loading and running the updated firmware version after resetting.

In the embodiment of the application, when the CPLD determines that the firmware version in the CPLD is refreshed, the CPLD sends a reset request signal to the processor, sends a first reset signal to the reset delay circuit after receiving a shutdown signal generated by the processor responding to the reset request signal, and resets after receiving a second reset signal generated by the reset delay circuit responding to the first reset signal, so that the firmware can be automatically upgraded, and the problem of long waiting time of the existing upgrade is solved; meanwhile, the first reset signal is subjected to delay preprocessing by introducing the reset delay circuit, so that the problems that the CPLD starts to reset after receiving a shutdown signal, the internal logic of the CPLD is disordered, the IO port is abnormal and the update information is lost can be effectively avoided.

With reference to one possible implementation manner of the embodiment of the first aspect, the CPLD includes a register and an IO control unit, where the register is preset with an identification bit used for representing whether a firmware version in the CPLD is refreshed; the IO control unit is used for determining whether the firmware version in the CPLD is refreshed or not by judging whether the characters in the preset identification bits of the register are preset characters or not; and when the character in the preset identification bit of the register is the preset character, determining that the firmware version in the CPLD is refreshed. In the embodiment of the application, whether the firmware version in the CPLD is refreshed or not is represented in a mode of presetting the identification bit in the register, so that whether the firmware version in the CPLD is refreshed or not can be quickly determined, and the problem of memory loss caused by hang-up or re-refreshing in the later period of the BMC is avoided.

With reference to one possible implementation manner of the embodiment of the first aspect, the reset delay circuit includes: the RC delay circuit and the shaping circuit are both connected with the CPLD, and the RC delay circuit is also connected with the shaping circuit; the RC delay circuit is used for delaying the first reset signal to obtain a signal which slowly changes from a low level to a high level or obtain a signal which slowly changes from a high level to a low level; the shaping circuit is used for shaping a signal which slowly changes from a low level to a high level or a signal which slowly changes from a high level to a low level to obtain a second reset signal which smoothly changes from a high level to a low level. According to the embodiment of the application, the first reset signal is delayed through the RC delay circuit, the problem that the internal logic of the CPLD is disordered to cause the IO port to be abnormal can be effectively avoided, meanwhile, the signal delayed by the RC delay circuit is shaped through the shaping circuit, and the second reset signal smoothly changed from a high level to a low level is output, so that the resetting accuracy of the CPLD is improved, and misoperation is avoided.

With reference to one possible implementation manner of the embodiment of the first aspect, an active level of the first reset signal is a low level, and an active level of the second reset signal is a low level; the RC delay circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a diode and a switching tube; the shaping circuit includes: a reverse phase schmitt trigger; the first end of the first resistor is connected with the CPLD, the first end of the first resistor is further connected with a power supply through a second resistor, the first end of the first resistor is further connected with an anode end of a diode, the second end of the first resistor is grounded through the first capacitor, the second end of the first resistor is further connected with a cathode end of the diode and the first end of the switch tube respectively, the second end of the switch tube is grounded, the third end of the switch tube is connected with the input end of the reverse Schmitt trigger, the third end of the switch tube is further connected with the power supply through a third resistor, and the output end of the reverse Schmitt trigger is connected with the CPLD. In the implementation of the application, the voltage of the first capacitor and the first end of the switching tube is clamped through the diode, so that the problem of output logic error caused by voltage oscillation is avoided, and meanwhile, a high-level signal is output when a CPLD does not need to load new firmware through the reversed-phase Schmitt trigger; when the CPLD receives a shutdown signal sent by the processor and changes the first reset signal from a high level to a low level, the reverse-phase Schmitt trigger delays and jumps the output signal from the high level to the low level for output and outputs a second reset signal smoothly changing from the high level to the low level, thereby improving the resetting accuracy of the CPLD and avoiding misoperation.

With reference to one possible implementation manner of the embodiment of the first aspect, an active level of the first reset signal is a high level, and an active level of the second reset signal is a low level; the RC delay circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a diode and a switching tube; the shaping circuit includes: a positive phase schmitt trigger; the first end of the first resistor is connected with the CPLD, the first end of the first resistor is further connected with a power supply through a second resistor, the first end of the first resistor is further connected with the cathode end of a diode, the second end of the first resistor is grounded through the first capacitor, the second end of the first resistor is further connected with the anode end of the diode and the first end of the switch tube respectively, the second end of the switch tube is grounded, the third end of the switch tube is connected with the input end of the normal phase Schmitt trigger, the third end of the switch tube is further connected with the power supply through a third resistor, and the output end of the normal phase Schmitt trigger is connected with the CPLD. In the implementation of the application, the voltage of the first capacitor and the first end of the switching tube is clamped through the diode, so that the problem of output logic error caused by voltage oscillation is avoided, and meanwhile, a high-level signal is output when a CPLD does not need to load new firmware through the normal-phase Schmitt trigger; when the CPLD receives a shutdown signal sent by the processor and changes the first reset signal from a low level to a high level, the normal phase Schmitt trigger delays and jumps the output signal from the high level to the low level for output and outputs a second reset signal smoothly changing from the high level to the low level, thereby improving the resetting accuracy of the CPLD and avoiding misoperation.

With reference to one possible implementation manner of the embodiment of the first aspect, the CPLD includes: the logic gate circuit is respectively connected with the IO control unit, the processor and the reset delay circuit; the IO control unit is configured to determine that the firmware version in the CPLD has been refreshed, and send the reset request signal to the processor and the logic gate circuit, respectively; and the logic gate circuit is used for performing logic operation on the reset request signal and the shutdown signal and outputting the first reset signal. In the embodiment of the application, the logic gate circuit is used for realizing the logic switching of the level, compared with a software mode, the processing speed is higher, and logic errors are not easy to occur.

With reference to a possible implementation manner of the embodiment of the first aspect, an active level of the shutdown signal is a low level, and an active level of the first reset signal is a low level, where the logic gate circuit includes: a first NAND gate and a second NAND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving the shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the second NAND gate, the second input end of the second NAND gate is connected with the IO control unit, the second input end of the second NAND gate is used for receiving the reset request signal, and the output end of the second NAND gate is connected with the reset delay circuit.

With reference to one possible implementation manner of the embodiment of the first aspect, an active level of the shutdown signal is a low level, and an active level of the first reset signal is a high level; the logic gate circuit comprises: a first NAND gate and a first AND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving the shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the first AND gate, the second input end of the first AND gate is connected with the IO control unit, the second input end of the first AND gate is used for receiving the reset request signal, and the output end of the first AND gate is connected with the reset delay circuit.

With reference to one possible implementation manner of the embodiment of the first aspect, an active level of the shutdown signal is a high level, and an active level of the first reset signal is a high level; the logic gate circuit comprises: a first AND gate and a second AND gate; the first input end of the first AND gate is connected with the processor, the first input end of the first AND gate is used for receiving the shutdown signal, and the second input end of the first AND gate is used for combining a high-level signal; the output end of the first AND gate is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with the IO control unit, the second input end of the second AND gate is used for receiving the reset request signal, and the output end of the second AND gate is connected with the reset delay circuit.

In a second aspect, an embodiment of the present application further provides a CPLD firmware loading method, which is applied to a CPLD in an electronic device, where the electronic device further includes a processor and a reset delay circuit; the CPLD is respectively connected with the processor and the reset delay circuit; the method comprises the following steps: determining that the firmware version in the CPLD has been refreshed, and sending a reset request signal to the processor; receiving a shutdown signal sent by the processor in response to the reset request signal, and sending a first reset signal to the reset delay circuit; receiving a second reset signal generated by the reset delay circuit in response to the first reset signal, and resetting; after reset, the updated firmware version is loaded and run.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 is a schematic diagram of a conventional circuit for firmware upgrade of a CPLD.

Fig. 2 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Fig. 3 shows a schematic circuit diagram of a reset delay circuit according to an embodiment of the present application.

Fig. 4 shows a schematic circuit diagram of another reset delay circuit provided in an embodiment of the present application.

Fig. 5 shows a schematic diagram illustrating a waveform relationship between the first reset signal, the signal delayed by the RC delay circuit, and the second reset signal according to an embodiment of the present application.

Fig. 6 shows a schematic diagram illustrating a waveform relationship between the first reset signal, the signal delayed by the RC delay circuit, and the second reset signal according to an embodiment of the present application.

Fig. 7 shows a schematic structural diagram of another electronic device provided in an embodiment of the present application.

Fig. 8 shows a schematic structural diagram of another electronic device provided in an embodiment of the present application.

Fig. 9 shows a schematic structural diagram of another electronic device provided in an embodiment of the present application.

Fig. 10 shows a flowchart of a CPLD firmware loading method provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In view of the defects of the existing firmware upgrading method in the CPLD, if the firmware is upgraded by the structure shown in fig. 1, the IO port of the CPLD is inevitably reset, so that risks such as system reset and power failure which are difficult to predict are caused, and the upgrading method can be adopted only before products are on the market; however, when the terminal user uses the CPLD version, the new CPLD version is enabled to take effect by manually powering off the server, which may cause a problem that the service processing requirement and the CPLD version enabling requirement of the user cannot be satisfied at the same time. Based on this, the embodiment of the application provides a CPLD firmware loading method, where the CPLD performs firmware preloading by using a Back-ground mode, and after the loading is completed, sends a reset request signal to a processor, after receiving a shutdown signal generated by the processor in response to the reset request signal, sends a first reset signal to a reset delay circuit, and after receiving a second reset signal generated by the reset delay circuit in response to the first reset signal, resets the processor, thereby completing firmware upgrade and solving the problem of long waiting time for existing upgrade; meanwhile, the first reset signal is subjected to delay preprocessing by introducing the reset delay circuit, so that the problem that the CPLD starts to reset after receiving a shutdown signal, so that the internal logic of the CPLD is disordered and the IO port is abnormal can be effectively avoided.

For ease of understanding, the electronic device of the present application will be described below with reference to fig. 2. The electronic device includes: a processor, a reset delay circuit, a CPLD and a BMC. The CPLD is respectively connected with the processor, the reset delay circuit and the BMC.

The BMC is connected with the CPLD through JTAG and I2C signal lines. The BMC can burn a Flash (Flash memory) arranged in the CPLD through the JTAG so as to preload the new firmware into the Flash; and a flag that Flash has been refreshed can also be set to a register inside the CPLD through the I2C interface to indicate that the firmware version in the CPLD has been refreshed. Defining 1 preset identification bit in the register to indicate whether the firmware version in the CPLD has been refreshed: if the character in the preset identification bit is 1, the firmware version in the CPLD is refreshed, otherwise, if the character in the preset identification bit is 0, the firmware version in the CPLD is not refreshed. For example, when the BMC completes through JTAG pre-burning the CPLD, bit0 in the register is set to 1 through I2C to indicate that the firmware version in the CPLD has been refreshed. The CPLD will automatically set bit0 to 0 after reset.

In addition, the character indicating whether the firmware version has been refreshed or not may be reversed, and if the character in the preset flag is 1, it indicates that the firmware version in the CPLD has not been refreshed, whereas if the character in the preset flag is 0, it indicates that the firmware version in the CPLD has been refreshed. It will be appreciated that, in addition to the numeral 0/1 indicating whether the firmware version in the CPLD has been refreshed, other numerals or letters can be used, such as 1 indicating refresh and 2 indicating no refresh, and therefore the example of 0/1 indicating whether the firmware version in the CPLD has been refreshed is not to be construed as limiting the present application.

Besides, whether the firmware version in the CPLD is refreshed or not is represented by presetting the flag bit in the register, the CPLD may be informed that the firmware version thereof is refreshed in an existing manner, for example, by sending an IEEE 1532 refresh command to the CPLD by the BMC. If the CPLD is informed that the firmware version thereof has been refreshed by sending an IEEE 1532 refresh command to the CPLD by the BMC, the CPLD may not include a register.

The process of how the BMC preloads or burns the new firmware version in Flash in the CPLD in the Back-ground mode is well known to those skilled in the art and will not be described here.

The CPLD is used for determining that the firmware version in the CPLD is refreshed and sending a reset request signal to the processor. In an optional implementation manner, whether the firmware version in the CPLD is refreshed or not may be determined by judging whether a character in a preset identification bit of a register in the CPLD is a preset character or not, when the character in the preset identification bit of the register is the preset character, it is determined that the firmware version in the CPLD is refreshed, and if the character in the preset identification bit is 1, it is determined that the firmware version in the CPLD is refreshed. In this embodiment, the CPLD includes a register and an IO control unit. The register is preset with an identification bit for representing whether the firmware version in the CPLD is refreshed or not. The IO control unit is used for determining whether the firmware version in the CPLD is refreshed or not by judging whether the characters in the preset identification bits of the register are preset characters or not; and when the character in the preset identification bit of the register is a preset character, determining that the firmware version in the CPLD is refreshed.

The processor is used for responding to the reset request signal to generate a shutdown signal, and after receiving the reset request signal sent by the CPLD, the processor responds to the reset request signal to generate the shutdown signal. In one embodiment, the priority of the reset request signal may be set to a lower priority, and when the processor receives the reset request signal, the processor waits for the end of the processing of other events with higher priority to respond. The processor in this embodiment may be a Central Processing Unit (CPU), a Platform Controller Hub (PCH), and the like.

The CPLD is also used for receiving a shutdown signal generated by the processor in response to the reset request signal and sending a first reset signal to the reset delay circuit. And the reset delay circuit is used for carrying out delay preprocessing on the first reset signal to obtain a second reset signal which smoothly changes from a high level to a low level. The CPLD is also used for receiving a second reset signal generated by the reset delay circuit responding to the first reset signal, resetting after receiving the second reset signal, and loading and running the updated firmware version after resetting so as to finish firmware upgrading. The first reset signal is subjected to delay preprocessing by introducing the reset delay circuit, so that the problems that the CPLD starts to reset after receiving a shutdown signal, the internal logic of the CPLD is disordered, the IO port is abnormal and the update information is lost can be effectively avoided.

Wherein, reset delay circuit includes: and the RC delay circuit and the shaping circuit are both connected with the CPLD and are also connected with the shaping circuit. And the RC delay circuit is used for delaying the first reset signal to obtain a signal which slowly changes from a low level to a high level or obtain a signal which slowly changes from a high level to a low level. And the shaping circuit is used for shaping the signal which slowly changes from the low level to the high level or the signal which slowly changes from the high level to the low level to obtain a second reset signal which smoothly changes from the high level to the low level. The active level of the second reset signal is a low level, and the active level of the first reset signal may be a low level or a high level.

If the active level of the first reset signal is low, the RC delay circuit delays the falling edge of the first reset signal for about 23ms, and a signal slowly changing from low to high is obtained. If the active level of the first reset signal is high level, the RC delay circuit delays the rising edge of the first reset signal to obtain a signal that slowly changes from high level to low level.

Optionally, the RC delay circuit comprises: the circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a diode D1 and a switching tube Q1.

If the active level of the first reset signal is a low level, the first end of the first resistor R1 is connected to the CPLD, the first end of the first resistor R1 is further connected to the power supply through the second resistor R2, the first end of the first resistor R1 is further connected to the anode of the diode D1, the second end of the first resistor R1 is grounded through the first capacitor C1, the second end of the first resistor R1 is further connected to the cathode of the diode D1 and the first end of the switching tube Q1, the second end of the switching tube Q1 is grounded, the third end of the switching tube Q1 is connected to the input end of the shaping circuit, and the third end of the switching tube Q1 is further connected to the power supply through the third resistor R3, which is schematically illustrated in fig. 3.

When the CPLD does not need to load new firmware, the first reset signal is at a high level, the first terminal of C1 or Q1 is clamped at 3V through D1, at this time, Q1 is in an on state, the voltage of the third terminal of Q1 is 0V, after the CPLD receives a shutdown signal sent by a processor, the first reset signal is changed from the high level to a low level, C1 and R1 form a discharge loop to start slow discharge for about 23ms, as the current of the first terminal of Q1 becomes smaller, the operating state of Q1 changes from a saturation region to an intercept region, when the current of the first terminal of Q1 is smaller than a turn-on current, Q1 is in an intercept state, the voltage of the third terminal of Q1 gradually changes from 0V to 3.3V, and the falling edge of the first reset signal is delayed by an RC delay circuit, so that a signal slowly changes from the low level to the high level is obtained.

If the active level of the first reset signal is a high level, the first end of the first resistor R1 is connected to the CPLD, the first end of the first resistor R1 is further connected to the power supply through the second resistor R2, the first end of the first resistor R1 is further connected to the cathode of the diode D1, the second end of the first resistor R1 is grounded through the first capacitor C1, the second end of the first resistor R1 is further connected to the anode of the diode D2 and the first end of the switching tube Q1, the second end of the switching tube Q1 is grounded, the third end of the switching tube Q1 is connected to the input end of the shaping circuit, and the third end of the switching tube Q1 is further connected to the power supply through the third resistor R3, which is schematically illustrated in fig. 4. When the CPLD does not need to load new firmware, the first reset signal is at a low level, the first terminal of C1 or Q1 is clamped at 0V through D1, at this time, Q1 is in an off state, the voltage at the third terminal of Q1 is 3.3V, after the CPLD receives a shutdown signal sent by the processor, the first reset signal is changed from a low level to a high level, C1 and R1 form a loop and start slow charging for about 23ms, as the current at the first terminal of Q1 increases, when the current at the first terminal of Q1 is greater than the on current, the operating state of Q1 changes from an off region to a saturation region, the voltage at the third terminal of Q1 gradually changes from 3.3V to 0V, and the rising edge of the first reset signal is delayed through the RC delay circuit, so as to obtain a signal that changes slowly from a high level to a low level.

In an alternative embodiment, the switching transistor Q1 is an NPN transistor, and accordingly, the first terminal of Q1 is a base, the second terminal of Q1 is an emitter, and the third terminal of Q1 is a collector. Alternatively, an NMOS transistor may be used instead of the NPN transistor, and accordingly, the first terminal of Q1 is a gate, the second terminal of Q1 is a source, and the third terminal of Q1 is a drain.

If the active level of the first reset signal is at a low level and the active level of the second reset signal is at a low level, optionally, as shown in fig. 3, the shaping circuit includes: an inverted schmitt trigger. And the third end of the switch tube is connected with the input end of the reverse-phase Schmitt trigger, and the output end of the reverse-phase Schmitt trigger is connected with the CPLD. When the voltage of the input signal is lower than the negative threshold voltage of the reverse Schmitt trigger, the output of the reverse Schmitt trigger jumps to a high level. After the signal which slowly changes from the low level to the high level is shaped by the inverted Schmitt trigger, a second reset signal which smoothly changes from the high level to the low level is obtained.

If the active level of the first reset signal is high level and the active level of the second reset signal is low level, optionally, as shown in fig. 4, the shaping circuit includes: a positive phase schmitt trigger. The third end of the switch tube is connected with the input end of the normal phase Schmitt trigger, and the output end of the normal phase Schmitt trigger is connected with the CPLD. When the voltage of the input signal is higher than the positive threshold voltage of the positive-phase schmitt trigger, the output of the positive-phase schmitt trigger jumps to a high level, and when the voltage of the input signal is lower than the negative threshold voltage of the positive-phase schmitt trigger, the output of the positive-phase schmitt trigger jumps to a low level. And shaping the signal slowly changing from the high level to the low level through a positive phase Schmitt trigger to obtain a second reset signal smoothly changing from the high level to the low level.

It should be noted that, besides using the schmitt trigger, the shaping circuit may also use a processor to implement functions similar to the schmitt trigger, for example, by detecting a voltage (a voltage output by the RC delay circuit) input to the processor, when the input voltage is higher than a positive threshold voltage, the output jumps to a low level, and when the voltage of the input signal is lower than a negative threshold voltage, the output jumps to a high level, or, when the voltage of the input signal is higher than the positive threshold voltage, the output jumps to a high level, and when the voltage of the input signal is lower than the negative threshold voltage, the output jumps to a low level.

For easy understanding, the relationship between the first reset signal, the signal obtained by delaying the first reset signal by the RC delay circuit, and the second reset signal will be described below with reference to schematic diagrams shown in fig. 5 and 6.

If the active level of the first reset signal is low, the relationship between the first reset signal, the signal obtained by delaying the first reset signal by the RC delay circuit, and the second reset signal is shown in fig. 5. When the CPLD does not need to load new firmware, the first reset signal is at a high level, and the voltage at the third terminal of Q1 in the RC delay circuit is 0V; when the CPLD receives a shutdown signal sent by the processor, the first reset signal is changed from a high level to a low level, the third end of the Q1 in the RC delay circuit is gradually changed from 0V to 3.3V, and the first reset signal passes through the RC delay circuit to obtain a signal which is slowly changed from the low level to the high level; after the signal which slowly changes from the low level to the high level is shaped by the shaping circuit, a second reset signal which smoothly changes from the high level to the low level is output.

If the active level of the first reset signal is high, the relationship between the first reset signal, the signal obtained by delaying the first reset signal by the RC delay circuit, and the second reset signal is shown in fig. 6. When the CPLD does not need to load new firmware, the first reset signal is at a low level, and the voltage at the third terminal of Q1 in the RC delay circuit is 3.3V at this time; when the CPLD receives a shutdown signal sent by the processor, the first reset signal is changed from low level to high level, the third end of the Q1 in the RC delay circuit is gradually changed from 3.3V to 0V, and the first reset signal passes through the RC delay circuit to obtain a signal which is slowly changed from high level to low level; after the signal which slowly changes from the high level to the low level is shaped by the shaping circuit, a second reset signal which smoothly changes from the high level to the low level is output.

Besides the active level of the first reset signal may be a high level or a low level, the active level of the shutdown signal may also be a high level or a low level. In one embodiment, the logic control may be performed by firmware burned in the CLPD, for example, after receiving the shutdown signal, the CPLD sends a first reset signal to the reset delay circuit, that is, the level of the first reset signal is switched from a high level to a low level, or from a low level to a high level. In addition, in addition to the logic switching of the level by the firmware, the logic switching of the level may be realized by a logic gate circuit. In this embodiment, the CPLD includes: the logic gate circuit is respectively connected with the IO control unit, the processor and the reset delay circuit.

And the IO control unit is used for determining that the firmware version in the CPLD is refreshed, and respectively sending a reset request signal to the processor and the logic gate circuit. And the logic gate circuit is used for performing logic operation on the reset request signal and the shutdown signal and outputting a first reset signal.

In one embodiment, if the active level of the shutdown signal is low and the active level of the first reset signal is low, as shown in fig. 7, the logic gate circuit includes: a first NAND gate and a second NAND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving a shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the second NAND gate, the second input end of the second NAND gate is connected with the IO control unit, the second input end of the second NAND gate is used for receiving the reset request signal, and the output end of the second NAND gate is connected with the reset delay circuit. When the CPLD does not need to load new firmware, the shutdown signal is a high-level signal, the first nand gate outputs a low-level signal, and the second nand gate outputs a high-level signal, that is, the first reset signal is a high-level signal. When the processor receives a reset request signal (default to high level), the shutdown signal is switched from high level to low level, the first NAND gate outputs a high level signal, the second NAND gate outputs low level at the moment, namely the first reset signal is switched from high level to low level, and the second reset signal is smoothly changed from high level to low level after delay pretreatment of the reset delay circuit.

In one embodiment, the active level of the shutdown signal is low, and the active level of the first reset signal is high; then, as shown in fig. 8, the logic gate circuit includes: a first NAND gate and a first AND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving a shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the first AND gate, the second input end of the first AND gate is connected with the IO control unit, the second input end of the first AND gate is used for receiving a reset request signal, and the output end of the first AND gate is connected with the reset delay circuit. When the CPLD does not need to load new firmware, the shutdown signal is a high-level signal, the first nand gate outputs a low-level signal, and the first and gate outputs a low level, that is, the first reset signal is a low-level signal. When the processor receives a reset request signal (default to high level), the shutdown signal is switched from high level to low level, the first NAND gate outputs a high level signal, at the moment, the first AND gate outputs high level, namely, the first reset signal is switched from low level to high level, and after the first NAND gate is subjected to delay preprocessing by the reset delay circuit, the second reset signal smoothly changes from high level to low level.

In one embodiment, the active level of the shutdown signal is high, and the active level of the first reset signal is high; then, as shown in fig. 9, the logic gate circuit includes: a first AND gate and a second AND gate; the first input end of the first AND gate is connected with the processor, the first input end of the first AND gate is used for receiving a shutdown signal, and the second input end of the first AND gate is used for combining a high-level signal; the output end of the first AND gate is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with the IO control unit, the second input end of the second AND gate is used for receiving the reset request signal, and the output end of the second AND gate is connected with the reset delay circuit. When the CPLD does not need to load new firmware, the shutdown signal is a low level signal, the first and gate outputs a low level signal, and the second and gate outputs a low level signal, that is, the first reset signal is a low level signal. When the processor receives a reset request signal (default to high level), the shutdown signal is switched from low level to high level, the first AND gate outputs a high level signal, the second AND gate outputs high level at the moment, namely the first reset signal is switched from low level to high level, and the second reset signal is smoothly changed from high level to low level after delay pretreatment of the reset delay circuit.

To facilitate understanding of the entire process of loading the CPLD firmware, the following description is provided. The BMC records Flash (Flash memory) built in the CPLD in a JTAG mode, so that the new version firmware is preloaded into the Flash, after the preloading is finished, the BMC sets a preset identification position of an internal register of the CPLD through I2C, and the character in the preset identification position is set to be 1. When detecting that the character in the preset identification bit of the register is 1, the IO control unit sends a reset request signal to the processor, and may set the priority of the reset request signal to a lower priority, and after receiving the reset request signal, the IO control unit waits for the end of processing of other events with higher priorities before responding. The processor is used for responding to the reset request signal to generate a shutdown signal, the CPLD sends a first reset signal to the reset delay circuit after receiving the shutdown signal, the CPLD obtains a second reset signal after delaying the preprocessing through the reset delay circuit, the CPLD starts to reset after receiving the second reset signal, and the updated firmware version is loaded and operated after the resetting, so that the upgrading of the new version firmware is completed. After the CPLD is reset, the CPLD will automatically set the character in the preset flag bit of the register to 0.

Different logic gates may be combined with different reset delay circuits to obtain different schemes, and therefore the illustration of the above example is not to be construed as limiting the present application.

Based on the same inventive concept, the embodiment of the application also provides a CPLD firmware loading method, which is applied to a CPLD in electronic equipment, and the electronic equipment further comprises a processor and a reset delay circuit. The process thereof will be described below with reference to fig. 10.

Step S101: and determining that the firmware version in the CPLD is refreshed, and sending a reset request signal to the processor.

In an optional implementation manner, whether the firmware version in the CPLD is refreshed may be determined by judging whether a character in the preset identification bit of the register in the CPLD is a preset character, when the character in the preset identification bit of the register is the preset character, it is determined that the firmware version in the CPLD is refreshed, and if the character in the preset identification bit is 1, it is determined that the firmware version in the CPLD is refreshed.

Step S102: and receiving a shutdown signal sent by the processor in response to the reset request signal, and sending a first reset signal to the reset delay circuit.

The processor responds to a shutdown signal sent to the CPLD by the reset request signal after receiving the reset request signal sent by the CPLD, and sends a first reset signal to the reset delay circuit after receiving the shutdown signal.

Step S103: and receiving a second reset signal generated by the reset delay circuit in response to the first reset signal, and resetting.

After receiving the first reset signal, the reset delay circuit responds to a second reset signal generated by the first reset signal, that is, the first reset signal is subjected to delay preprocessing by the reset delay circuit to obtain a second reset signal. And resetting the CPLD when receiving the second reset signal.

Step S104: after reset, the updated firmware version is loaded and run.

The CPLD firmware loading method provided in the embodiment of the present application has the same implementation principle and technical effect as those of the foregoing device embodiment, and for brief description, reference may be made to corresponding contents in the foregoing device embodiment for the part of the method embodiment that is not mentioned.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An electronic device, comprising: the device comprises a processor, a reset delay circuit and a CPLD, wherein the CPLD is respectively connected with the processor and the reset delay circuit;

the CPLD is used for determining that the firmware version in the CPLD is refreshed and sending a reset request signal to the processor;

the processor is used for responding to the reset request signal to generate a shutdown signal;

the CPLD is also used for receiving the shutdown signal and sending a first reset signal to the reset delay circuit;

the reset delay circuit is used for carrying out delay preprocessing on the first reset signal to obtain a second reset signal;

and the CPLD is also used for receiving the second reset signal, resetting and loading and running the updated firmware version after resetting.

2. The electronic device according to claim 1, wherein the CPLD includes a register and an IO control unit, the register being preset with an identification bit for characterizing whether a firmware version in the CPLD is refreshed or not;

the IO control unit is used for determining whether the firmware version in the CPLD is refreshed or not by judging whether the characters in the preset identification bits of the register are preset characters or not; and when the character in the preset identification bit of the register is the preset character, determining that the firmware version in the CPLD is refreshed.

3. The electronic device of claim 1, wherein the reset delay circuit comprises: the RC delay circuit and the shaping circuit are both connected with the CPLD, and the RC delay circuit is also connected with the shaping circuit; the RC delay circuit is used for delaying the first reset signal to obtain a signal which slowly changes from a low level to a high level or obtain a signal which slowly changes from a high level to a low level; the shaping circuit is used for shaping a signal which slowly changes from a low level to a high level or a signal which slowly changes from a high level to a low level to obtain a second reset signal which smoothly changes from a high level to a low level.

4. The electronic device according to claim 3, wherein an active level of the first reset signal is a low level, and an active level of the second reset signal is a low level; the RC delay circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a diode and a switching tube; the shaping circuit includes: a reverse phase schmitt trigger;

the first end of the first resistor is connected with the CPLD, the first end of the first resistor is further connected with a power supply through a second resistor, the first end of the first resistor is further connected with an anode end of a diode, the second end of the first resistor is grounded through the first capacitor, the second end of the first resistor is further connected with a cathode end of the diode and the first end of the switch tube respectively, the second end of the switch tube is grounded, the third end of the switch tube is connected with the input end of the reverse Schmitt trigger, the third end of the switch tube is further connected with the power supply through a third resistor, and the output end of the reverse Schmitt trigger is connected with the CPLD.

5. The electronic device according to claim 3, wherein an active level of the first reset signal is a high level, and an active level of the second reset signal is a low level; the RC delay circuit includes: the circuit comprises a first resistor, a second resistor, a third resistor, a first capacitor, a diode and a switching tube; the shaping circuit includes: a positive phase schmitt trigger;

the first end of the first resistor is connected with the CPLD, the first end of the first resistor is further connected with a power supply through a second resistor, the first end of the first resistor is further connected with the cathode end of a diode, the second end of the first resistor is grounded through the first capacitor, the second end of the first resistor is further connected with the anode end of the diode and the first end of the switch tube respectively, the second end of the switch tube is grounded, the third end of the switch tube is connected with the input end of the normal phase Schmitt trigger, the third end of the switch tube is further connected with the power supply through a third resistor, and the output end of the normal phase Schmitt trigger is connected with the CPLD.

6. The electronic device of claim 1, wherein the CPLD comprises: the logic gate circuit is respectively connected with the IO control unit, the processor and the reset delay circuit;

the IO control unit is configured to determine that the firmware version in the CPLD has been refreshed, and send the reset request signal to the processor and the logic gate circuit, respectively;

and the logic gate circuit is used for performing logic operation on the reset request signal and the shutdown signal and outputting the first reset signal.

7. The electronic device according to claim 6, wherein an active level of the shutdown signal is a low level, an active level of the first reset signal is a low level, and the logic gate circuit includes: a first NAND gate and a second NAND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving the shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the second NAND gate, the second input end of the second NAND gate is connected with the IO control unit, the second input end of the second NAND gate is used for receiving the reset request signal, and the output end of the second NAND gate is connected with the reset delay circuit.

8. The electronic device according to claim 6, wherein an active level of the shutdown signal is a low level, and an active level of the first reset signal is a high level; the logic gate circuit comprises: a first NAND gate and a first AND gate; the first input end of the first NAND gate is connected with the processor, the first input end of the first NAND gate is used for receiving the shutdown signal, and the second input end of the first NAND gate is used for receiving a high-level signal; the output end of the first NAND gate is connected with the first input end of the first AND gate, the second input end of the first AND gate is connected with the IO control unit, the second input end of the first AND gate is used for receiving the reset request signal, and the output end of the first AND gate is connected with the reset delay circuit.

9. The electronic device according to claim 6, wherein an active level of the shutdown signal is a high level, and an active level of the first reset signal is a high level; the logic gate circuit comprises: a first AND gate and a second AND gate; the first input end of the first AND gate is connected with the processor, the first input end of the first AND gate is used for receiving the shutdown signal, and the second input end of the first AND gate is used for combining a high-level signal; the output end of the first AND gate is connected with the first input end of the second AND gate, the second input end of the second AND gate is connected with the IO control unit, the second input end of the second AND gate is used for receiving the reset request signal, and the output end of the second AND gate is connected with the reset delay circuit.

10. A CPLD firmware loading method is characterized in that the method is applied to a CPLD in electronic equipment, and the electronic equipment further comprises a processor and a reset delay circuit; the CPLD is respectively connected with the processor and the reset delay circuit; the method comprises the following steps:

determining that the firmware version in the CPLD has been refreshed, and sending a reset request signal to the processor;

receiving a shutdown signal sent by the processor in response to the reset request signal, and sending a first reset signal to the reset delay circuit;

receiving a second reset signal generated by the reset delay circuit in response to the first reset signal, and resetting;

after reset, the updated firmware version is loaded and run.

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