TWI768769B - Server motherboard for single-processor system - Google Patents

Abstract

A server motherboard for a single-processor system includes a plurality of PCIe connection ports, a CPLD, a CPU, a BMC and an isolation circuit. The CPLD is electrically connected to the PCIe port through a plurality of PCIe channels. The central processing unit CPU is used for sending at least one PCIe reset signal to the CPLD through a plurality of PCIe reset pins, so that the CPLD resets the PCIe channel according to the PCIe reset signal. The BMC is used to control the update of CPLD. The isolation circuit is set between the CPLD and the BMC to prevent the CPLD from accidentally triggering the reset operation of the BMC when the CPLD is updating.

Description

Server motherboard for single processor system

The present invention relates to a server motherboard, in particular to a server motherboard of a single processor system.

Please refer to the first figure. The first figure is a schematic diagram of the system structure of the dual-processor system of the prior art. As shown in the first figure, a dual-processor system PA100 includes two processors (CPU) PA1a and PA1b, a complex programmable logic device (CPLD) PA2, and a plurality of buffers (Buffer) PA3 (only one is marked in the figure) And a plurality of PCIe ports PA4 (only one is marked in the figure).

As mentioned above, the early dual-processor system PA100 is mostly based on Intel's dual-processor system, so the server motherboard will reserve a channel between the two processors PA1a and PA1b in the design, so as to connect to the The complex programmable logic device PA2 has limited channels, and the complex programmable logic device PA2 also needs to be connected to a plurality of PCIe ports PA4 through the buffer PA3.

In recent years, AMD's high-performance processors for the server market can replace Intel's dual processors with one processor, so it is widely favored by various manufacturers. However, because the early server systems were mainly for Intel's dual processors Therefore, if AMD processors are used in an existing dual-processor system, not only will they not be able to effectively play their due performance, but also because dual-processor motherboards require two processors, resulting in poor performance. Waste, so in order to effectively use AMD's processors, it is bound to introduce a new single-processor operating system to match with AMD's processors.

In addition, in the existing dual-processor system PA100, the complex programmable logic device PA2 is also used to control the reset operation of the board management controller (not shown in the figure). However, when the complex programmable logic device PA2 runs the firmware When updating, it is easy to trigger the reset operation of the board management controller by mistake, thus causing the dual-processor system PA100 to fail to operate normally.

In view of the fact that in the prior art, most of the existing servers are based on Intel's dual-processor operating system, but when AMD's processor can replace Intel's dual-processor, the existing server motherboards are mainly in response to Intel's It is designed for a dual-processor system, so AMD's processors cannot be used effectively, and the existing dual-processor system also has complex programmable logic devices that can easily trigger the board management controller by mistake when updating the firmware. Therefore, the main purpose of the present invention is to provide a single-processor system server motherboard, which can be effectively matched with the single-processor operating system.

In order to solve the problem of the prior art, the necessary technical means adopted by the present invention is to provide a server motherboard of a single processor system, comprising a plurality of PCIe (Peripheral Component Interconnect Express) ports, a Complex Programmable Logic Device (Complex Programmable Logic Device) Logic Device, CPLD), a central processing unit, a baseboard management controller (Board Management Controller, BMC) and an isolation circuit.

The plurality of PCIe ports are used to install at least one PCIe device. The complex programmable logic device is electrically connected to the PCIe ports through a plurality of PCIe lanes. The central processing unit is electrically connected to the complex programmable logic device by a plurality of PCIe reset pins, and is used for sending at least one PCIe reset signal to the complex programmable logic device through the PCIe reset pins, so that the The complex programmable logic device resets at least one of the PCIe channels according to the PCIe reset signal.

The baseboard management controller is electrically connected to the complex programmable logic device for controlling the update operation of the complex programmable logic device. The isolation circuit is arranged between the complex programmable logic device and the baseboard management controller to prevent the complex programmable logic device from accidentally triggering the baseboard management controller when the complex programmable logic device performs an update operation homework.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the complex programmable logic device further includes a reset module, which is electrically connected to the PCIe reset pins of the central processing unit, so as to receive the The at least one PCIe reset signal resets at least one of the PCIe channels. Preferably, the baseboard management controller further includes a PCIe channel reset state monitoring module for detecting whether the reset module controls the PCIe channel reset.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the isolation circuit includes a logic gate unit, a first MOS transistor and a second MOS transistor. The logic gate unit is electrically connected to the BMC Reset pin of the complex programmable logic device. The first MOS transistor system is electrically connected to the logic gate unit. The second MOS transistor system is electrically connected to the first MOS transistor and the Reset pin of the baseboard management controller.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the central processing unit is an AMD processor.

As described above, in the present invention, the isolation circuit is arranged between the complex programmable logic device and the baseboard management controller, so when the complex programmable logic device is updated, the isolation circuit can be used to prevent the complex programmable logic device. The program logic device erroneously triggers the reset operation of the baseboard management controller, so that the server motherboard of the single processor system of the present invention can still operate normally when the complex programmable logic device is updating the firmware.

The specific embodiments adopted by the present invention will be further described by the following embodiments and drawings.

Please refer to the second figure. The second figure is a signal transmission circuit diagram of the server motherboard of the uniprocessor system provided by the preferred embodiment of the present invention. As shown in the second figure, a single processor system server motherboard 100 includes eight PCIe (Peripheral Component Interconnect Express) ports 1a (only one is marked in the figure), six PCIe ports 1b (only one is marked in the figure) a), a PCIe port 1c, a Complex Programmable Logic Device (CPLD) 2, a Central Processing Unit (CPU) 3, a Baseboard Management Controller (BMC) 4. An isolation circuit 5 and a buffer 6 .

The PCIe ports 1a, 1b, and 1c are used to install at least one PCIe device; wherein, the PCIe ports 1a, 1b in this embodiment are PCIe slots, and the PCIe port 1c is a network card port (OCP 3.0 ).

Please continue to refer to the third figure, which is a schematic diagram of the circuit system of the server motherboard of the uniprocessor system provided by the preferred embodiment of the present invention. As shown in the second and third figures, the complex programmable logic device 2 is electrically connected to the PCIe ports 1a, 1b and 1c by a plurality of PCIe lanes, and the complex programmable logic device 2 further includes a multiple The reset module 21 resets at least one of the PCIe channels when receiving at least one PCIe reset signal.

The CPU 3 is electrically connected to the reset module 21 of the complex programmable logic device 2 through eight PCIe reset pins (Plinkreset0-Plinkreset3 and Glinkreset0-Glinkreset3 in the CPU 3 in the third figure). It is used for sending at least one PCIe reset signal to the reset module 21 of the complex programmable logic device 2 through the PCIe reset pin, so that the complex programmable logic device 2 resets the connection to the PCIe port 1a, At least one of the PCIe lanes of 1b and 1c.

The baseboard management controller 4 is electrically connected to the complex programmable logic device 2 to control the update operation of the complex programmable logic device 2 ; wherein the baseboard management controller 4 further includes a PCIe channel reset state monitoring module 41 , It is used to detect whether the reset module 21 controls PCIe channel reset. The isolation circuit 5 is arranged between the complex programmable logic device 2 and the baseboard management controller 4 to prevent the complex programmable logic device 2 from accidentally triggering the baseboard management controller 4 when the complex programmable logic device 2 performs an update operation. Reset the job.

Please continue to refer to FIG. 4 , which is a schematic circuit diagram of the isolation circuit of the server motherboard of the single-processor system provided by the preferred embodiment of the present invention. As shown in FIGS. 2 to 4 , the isolation circuit 5 includes a logic gate unit 51 , a first MOS transistor 52 and a second MOS transistor 53 . The logic gate unit 51 has a first input pin, a The second input pin and an output pin, the first input pin is electrically connected to the BMC Reset pin of the complex programmable logic device 2 , and the second input pin is grounded and electrically connected to the baseboard management controller 4 The BMC Ready pin, the output pin of the logic gate unit 51 is electrically connected to the first MOS transistor 52 , and the second MOS transistor 53 is electrically connected to the connection between the first MOS transistor 52 and the baseboard management controller 4 . Reset pin.

As mentioned above, before the baseboard management controller 4 has not loaded the firmware, the BMC Ready pin of the baseboard management controller 4 will be kept at a low voltage. The BMC Reset signal is sent to the first input pin, the logic gate unit 51 will perform a logic operation because the second input pin is grounded and the BMC Ready pin of the connected baseboard management controller 4 is low voltage, so that the output pin outputs a The intermediate signal is sent to the first MOS transistor 52, and then controlled by the power supply voltage of the first MOS transistor 52 and the power supply voltage of the second MOS transistor 53 to generate a reset signal to the Reset pin of the baseboard management controller 4 . However, after the baseboard management controller 4 has loaded the firmware, the baseboard management controller 4 will control, and the BMC Ready pin of the baseboard management controller 4 is kept at a high level. Therefore, if the complex programmable logic device 2 is updated due to When the BMC reset signal is sent to the first input pin by mistake, the logic gate unit 51 will also keep the BMC Ready pin connected to the second input pin at a high level, so that the logic operation of the logic gate unit 51 will not be output. The intermediate signal is sent to the first MOS transistor 52 to prevent the complex programmable logic device 2 from accidentally triggering the reset operation of the baseboard management controller 4 .

Please continue to refer to the second figure. As shown in the second figure, the buffer 6 is electrically connected to the baseboard management controller 4 and the PCIe port 1b, and is used to bufferly store the data sent by the baseboard management controller 4 to the PCIe port 1b. 1b data, and the baseboard management controller 4 is used to control the reset operation of the buffer 6 . The buffer 6 in this embodiment is a clock buffer for controlling timing.

To sum up, since most of the existing servers are based on Intel's dual-processor operating system, and the existing server motherboards are designed for Intel's dual-processor system, even if AMD has introduced a system that can replace Intel's dual-processor system, When a dual-processor single processor is used, the AMD processor cannot effectively play its due performance because the existing server motherboard cannot effectively support it, and the existing dual-processor system still has complex programmable logic. When the device is updating the firmware, it is easy to trigger the reset operation of the board management controller by mistake. In contrast to this, in the present invention, by disposing an isolation circuit between the complex programmable logic device and the baseboard management controller, when the complex programmable logic device performs an update operation, the complex programmable logic device can be prevented by the isolation circuit The reset operation of the baseboard management controller is triggered by mistake, so that the server motherboard of the single-processor system of the present invention can still operate normally when the complex programmable logic device performs firmware update.

Based on the above, since the present invention not only retains the original complex programmable logic device, the reset function between the baseboard management controller and the central processing unit, but also increases the reset control of the buffer by the baseboard management controller. These buffers for timing control can be turned on according to the user's required time, and can also be reset by initiating reset when the buffers fail. In addition, because the present invention also utilizes the complex programmable logic device to directly control the reset of multiple PCIe lanes, compared with the existing complex programmable logic device, it needs a lot of input and output pins (I/O pins) The method of IO Buffer, the present invention not only reduces costs, but also effectively saves space, and can directly control the reset of PCIe devices installed in the PCIe connection port through complex programmable logic devices, thereby satisfying the PCIe reset of AMD's central processing unit. The requirements for one-to-one mapping with clock.

Through the detailed description of the preferred embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the claimed scope of the present invention.

PA100: Dual Processor System PA1a,Pa1b: Processor PA2: Complex Programmable Logic Device PA3: Buffer PA4: PCIe port 100: Server motherboard for single processor system 1a: PCIe port 1b: PCIe port 1c: PCIe port 2: Complex Programmable Logic Device 21: Reset Mods 3: CPU 4: Baseboard Management Controller 41: PCIe channel reset status monitoring module 5: Isolation circuit 51: Logic gate unit 52: The first MOS transistor 53: The second MOS transistor 6: Buffer

The first figure is a schematic diagram showing the system architecture of the dual-processor system of the prior art; The second figure shows the signal transmission circuit diagram of the server motherboard of the single processor system provided by the preferred embodiment of the present invention FIG. 3 is a schematic diagram showing the circuit system of the server motherboard of the uniprocessor system provided by the preferred embodiment of the present invention; and FIG. 4 is a schematic circuit diagram showing the isolation circuit of the server motherboard of the uniprocessor system provided by the preferred embodiment of the present invention.

100: Server motherboard for single processor system

1a: PCIe port

1b: PCIe port

1c: PCIe port

2: Complex Programmable Logic Device

3: CPU

4: Baseboard Management Controller

5: Isolation circuit

6: Buffer

Claims (5)

A server motherboard for a single processor system, comprising: a plurality of PCIe (Peripheral Component Interconnect Express) ports for installing at least one PCIe device; a Complex Programmable Logic Device (CPLD) electrically connected to the PCIe ports through a plurality of PCIe lanes; a central processing unit electrically connected to the complex programmable logic device through a plurality of PCIe reset pins for sending at least one PCIe reset signal to the complex programmable logic device through the PCIe reset pins, causing the complex programmable logic device to reset at least one of the PCIe channels according to the PCIe reset signal; a baseboard management controller (BMC) electrically connected to the complex programmable logic device for controlling the update operation of the complex programmable logic device; and An isolation circuit is arranged between the complex programmable logic device and the baseboard management controller to prevent the complex programmable logic device from accidentally triggering the baseboard management controller when the complex programmable logic device performs an update operation the reset operation. The server motherboard of a single processor system according to claim 1, wherein the complex programmable logic device further comprises a reset module electrically connected to the PCIe reset pins of the central processing unit , so as to reset at least one of the PCIe channels when the at least one PCIe reset signal is received. The server motherboard of a single processor system according to claim 2, wherein the baseboard management controller further comprises a PCIe channel reset state monitoring module for detecting whether the reset module controls the PCIe lane reset. The server motherboard of a single-processor system as claimed in claim 1, wherein the isolation circuit comprises: a logic gate unit electrically connected to the BMC Reset pin of the complex programmable logic device; a first MOS transistor electrically connected to the logic gate unit; and A second MOS transistor is electrically connected to the first MOS transistor and the Reset pin of the baseboard management controller. The server motherboard of a single-processor system according to claim 1, wherein the central processing unit is an AMD processor.

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