CN109491491A - A kind of server timing control and signal monitoring board - Google Patents
A kind of server timing control and signal monitoring board Download PDFInfo
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- CN109491491A CN109491491A CN201811293210.9A CN201811293210A CN109491491A CN 109491491 A CN109491491 A CN 109491491A CN 201811293210 A CN201811293210 A CN 201811293210A CN 109491491 A CN109491491 A CN 109491491A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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Abstract
The invention discloses a kind of server timing control and signal monitoring board, comprising: controller has multiple connection pins, the enable signal of the power-on and power-off timing and monitoring server for control server simultaneously in operation；Connector, for establishing signal connection between multiple connection pin and mainboards；Register is connected to controller, for receive and/or storage control monitoring enable signal state.Technical solution of the present invention can work for different server or different types of server to carry out timing control and signal monitoring simultaneously, and reduction designs and develops complexity, reduces board occupied space and compression work period.
Description
Technical field
The present invention relates to computer fields, and more specifically, more particularly to a kind of server timing control and signal
Monitor board.
Background technique
During server design, timing Design is particularly important, directly influences whether system can work normally, existing
Having design is typically all to use onboard CPLD (Complex Programmable Logic Devices) or FPGA (field programmable gate array) Lai Shixian
The power-on and power-off timing control of system.In this case, it when other server products of every secondary design, requires to redesign up and down
Electric timing；And it needs just to can be carried out timing debugging verifying until board returns plate in debugging.Timing control and signal monitoring are all
The necessary function of server, but the timing control of existing design and signal monitoring be it is discrete, this design and development is answered
Miscellaneous degree is higher, and occupied space is big, and the duty cycle is long, is unfavorable for update and debugging efforts.
Lead to the complexity designed and developed height, occupied space for timing control in the prior art and signal monitoring are discrete
Greatly, the problem of duty cycle length, there has been no effective solution schemes at present.
Summary of the invention
In view of this, the purpose of the embodiment of the present invention is to propose a kind of server timing control and signal monitoring board,
It can work for different server or different types of server to carry out timing control and signal monitoring simultaneously, reduce design
It develops complexity, reduce board occupied space and compression work period.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of server timing control and signal monitoring plate
Card, comprising:
Controller has multiple connection pins, exists for the power-on and power-off timing of control server and monitoring server simultaneously
Running enable signal；
Connector, for establishing signal connection between multiple connection pin and mainboards；
Register is connected to controller, for receive and/or storage control monitoring enable signal state.
In some embodiments, power-on and power-off timing includes machine open/close signal, multiple power supply enable signals, multiple power supplys
Indication signal and machine open/close complete signal；Wherein, starting-up signal and off signal share a connection pin, and letter is completed in booting
Number and shutdown complete signal share a connection pin.
In some embodiments, controller receives starting-up signal by connector, successively sends out when controlling electrifying timing sequence
Sending makes the raised multiple power supply enable signals of each level for electrical connection pins and respectively receives to indicate each for electrical connection pins
The multiple power indication signals and send booting completion signal that level has built up.
In some embodiments, controller under control electric timing when, off signal is received by connector, is successively sent out
Sending the multiple power supply enable signals for reducing each level for electrical connection pins and receiving respectively indicates each for electrical connection pins
Signal is completed in the decreased multiple power indication signals of level and transmission shutdown.
In some embodiments, enable signal includes timing control signal and universal input output signal.
In some embodiments, board further includes the clock module for exporting real-time time；Register is connected to outer
Memory and clock module, register is by the state of the enable signal of controller monitoring and corresponding time for being provided by clock module
It stores in external memory.
In some embodiments, register is connected to reading interface, and register is by the key signal of controller monitoring
State is exported in real time by reading interface.
In some embodiments, board further includes the interactive module for being connected to controller and connector, and interactive module is logical
It crosses connector and is connected to the interactive modules of other boards and multiple boards are cooperated.
The another aspect of the embodiment of the present invention additionally provides a kind of server, comprising:
Mainboard；
Enabled module, is connected to mainboard, and enabled module generates enable signal when server is run；
Above-mentioned server timing control and signal monitoring board, the connection of server timing control and signal monitoring board
Device is connected to mainboard.
The another aspect of the embodiment of the present invention additionally provides a kind of server timing control and signal monitoring method, including
Following steps:
When powering on, the electrifying timing sequence of control server；
The key signal of monitoring server in operation；
The state of the key signal of reception and/or storage control monitoring；
In lower electricity, the lower electric timing of control server.
The present invention has following advantageous effects: server timing control provided in an embodiment of the present invention and signal monitoring
Board, by the power-on and power-off timing of the control server when needing power-on and power-off, the enable signal of monitoring server in operation is simultaneously
The technical solution of the state of the enable signal of reception and/or storage control monitoring, can be directed to different server or inhomogeneity
The server of type comes while carrying out timing control and signal monitoring work, and complexity is designed and developed in reduction, diminution board occupies sky
Between, and compression work period.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other embodiments are obtained according to these attached drawings.
Fig. 1 is the architecture logic schematic diagram of server timing control provided by the invention and signal monitoring board；
Fig. 2 is the detailed block diagram of server timing control and signal monitoring board provided by the invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
It should be noted that all statements for using " first " and " second " are for differentiation two in the embodiment of the present invention
The non-equal entity of a same names or non-equal parameter, it is seen that " first ", " second " do not answer only for the convenience of statement
It is interpreted as the restriction to the embodiment of the present invention, subsequent embodiment no longer illustrates this one by one.
Based on above-mentioned purpose, the first aspect of the embodiment of the present invention, propose one kind can for different server or
Different types of server carrys out while carrying out the embodiment of the board of timing control and signal monitoring work.Shown in fig. 1 is this
The structural schematic diagram of the embodiment of the server timing control and signal monitoring board that provide is provided.
The server timing control includes: with signal monitoring board
Controller 11 has multiple connection pins, the power-on and power-off timing and monitoring server for control server simultaneously
Enable signal in operation；
Connector 12, for establishing signal connection between multiple connection pin and mainboards；
Register 13 is connected to controller 11, for receive and/or storage control 11 monitor key signal shape
State.
Controller 11 is the main chip for realizing timing control and signal monitoring, controller 11 can be used CPLD,
The chips such as FPGA, PSoC (programmable systemonchip) are realized.Connector 12 (is can be implemented with the interconnecting interface of mainboard
For such as golden finger).Register 13 can be arranged in controller 11 according to the demand of those skilled in the art or controller
Outside 11.
The various exemplary means in conjunction with described in disclosure herein may be implemented as electronic hardware, computer software or
The combination of the two.In order to clearly demonstrate this interchangeability of hardware and software, with regard to the function of various schematic devices
General description has been carried out to it.This function be implemented as software be also implemented as hardware depending on concrete application with
And it is applied to the design constraint of whole system.Those skilled in the art can realize in various ways for every kind of concrete application
The function, but this realization decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
As shown in Fig. 2, the key signal monitored mainly includes enable signal (Pwren 1, Pwren of power module
2 ..., Pwren n), power module be used to indicate power on completion indication signal (Pwrgd1, Pwrgd 2 ..., Pwrgd n),
And a part of customized GPIO (universal input output) signal (GPIO 1, GPIO 2 ..., GPIO n), I2C (inside collection
At circuit) management signal etc..Controller 11 takes electricity, initiation signal of the switching on and shutting down signal as power-on and power-off from mainboard, and Pwren x makees
For the control signal of power-on and power-off, indication signal of the Pwrgd x as power supply status, when booting completion signal is used to indicate power-on and power-off
Sequence execution terminates, and GPIO x can carry custom feature (interactive signal etc. of the key signal, module-cascade that need to monitor), I2C
Signal is used for 13 value of register of Read Controller 11.
In some embodiments, controller 11 controls power-on and power-off timing and makes including control machine open/close signal, multiple power supplys
It can signal, multiple power indication signals and machine open/close completion signal；Wherein, starting-up signal and off signal share a connection
Pin, signal is completed in booting and shutdown completes signal and shares a connection pin.
In some embodiments, controller 11 is when controlling electrifying timing sequence, by connector 12 receive starting-up signal, according to
It is secondary transmission make the raised multiple power supply enable signals of each level for electrical connection pins and respectively receive indicate it is each for electrical connection draw
The multiple power indication signals and send booting completion signal that the level of foot has built up.
In some embodiments, controller 11 under control electric timing when, by connector 12 receive off signal, according to
Multiple power supply enable signals that secondary transmission reduces each level for electrical connection pins simultaneously receive respectively and indicate each and draw for electrical connection
Signal is completed in the decreased multiple power indication signals of the level of foot and transmission shutdown.
Specifically, when powering on, controller 11 receives starting-up signal (switching on and shutting down signal sets height), and Pwren 1 is set height,
The enable signal of enabled power supply 1, power supply 1, which powers on completion, can set Pwrgd 1 height, and controller 11 receives Pwrgd 1 as height
Level indicates that power supply 1 powers on completion, then Pwren 2 is set height, enables the enable signal of power supply 2, and power supply 2 powers on completion and can incite somebody to action
Pwrgd 2 sets height, and it is that high level indicates that power supply 2 powers on completion that controller 11, which receives Pwrgd 2, so until power supply n is powered on
It completes, booting completion signal is set high expression electrifying timing sequence and completed by controller 11, system boot.
Correspondingly, in lower electricity, controller 11 receives off signal (switching on and shutting down signal is set low), and Pwren n is set low,
The enable signal of inactive power sources n, electricity completes that Pwrgd n can be set low under power supply n, and it is low that controller 11, which receives Pwrgd n,
Level indicates that electricity is completed under power supply n, then Pwren n-1 is set low, the enable signal of inactive power sources n-1, and electricity is complete under power supply n-1
At that can set low Pwrgd n-1, it is that low level indicates that electricity is completed under power supply n-1 that controller 11, which receives Pwrgd n-1, so straight
It is completed to the lower electricity of power supply 1, booting completion signal is set low the lower electric timing of expression and completed by controller 11, system closedown.
Computer readable storage medium (such as memory) as described herein can be volatile memory or non-volatile
Memory, or may include both volatile memory and nonvolatile memory.As an example and not restrictive, it is non-easy
The property lost memory may include read-only memory (ROM), programming ROM (PROM), electrically programmable ROM (EPROM), electrically-erasable
Programming ROM (EEPROM) or flash memory.Volatile memory may include random access memory (RAM), which can
To serve as external cache.As an example and not restrictive, RAM can be obtained in a variety of forms, such as synchronous
RAM (DRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate SDRAM (DDR SDRAM), enhancing SDRAM
(ESDRAM), synchronization link DRAM (SLDRAM) and directly Rambus RAM (DRRAM).The storage of disclosed aspect is set
The standby memory for being intended to including but not limited to these and other suitable type.
In some embodiments, the key signal of 11 monitoring server of controller in operation includes monitoring timing control
Signal and universal input output signal.
Controller 11 monitors all timing control signals (signal is completed in switching on and shutting down signal, Pwren x, Pwrgd x, booting)
And the customized GPIO signal in part (GPIO x of key signal for needing to monitor can be defined as), whenever having letter in these signals
Change information (0, which becomes 1 or 1, becomes 0) and current time (are just read into) write-in SD from RTC block when the variation of number generating state
In card, while also the real-time status of all monitoring signals is written in the register 13 of oneself for controller 11, when event occurs for system
When barrier, current signal condition can be read by I2C.In an alternate embodiments, can not also grafting SD card, directly
The state change information that all signals occurred are read by interface, enables maintenance personnel's quick positioning question and is directed to
Property goes to solve the problems, such as.
In some embodiments, board further includes the clock module for exporting real-time time；Register 13 is connected to
External memory and clock module, register 13 is by the state for the enable signal that controller 11 monitors and the phase that is provided by clock module
Storage is into external memory between seasonable.
Clock module (RTC) can be set, acquisition time information, avoid being by installing additional independent battery power supply
System power-off causes temporal information to be lost.External memory can be the SD card slot of installation SD card, and SD card stores power supply signal and key
The information of signal stores the change information and changed time to SD card when the signal condition monitored changes
In.
In some embodiments, register 13 is connected to reading interface, and register 13 monitors controller 11 enabled
The state of signal is exported in real time by reading interface.
In some embodiments, board further includes the interactive module for being connected to controller 11 and connector 12, interaction mould
Block makes multiple boards cooperate by the interactive module that connector 12 is connected to other boards.Pass through customized GPIO conduct
Interactive signal, it can be achieved that the multiple timing control and signal monitoring module of multi node server collaborative work, realize simultaneously on
Lower electricity, guarantees the normal operation of system.
Extraly, board can also include the burning interface for updating 11 firmware of controller, and be used to indicate in real time
The debugging indicator light (Debug LED) of lower electricity process.
In one or more exemplary designs, the function can be real in hardware, software, firmware or any combination thereof
It is existing.If realized in software, can be stored in using the function as one or more instruction or code computer-readable
It is transmitted on medium or by computer-readable medium.Computer-readable medium includes computer storage media and communication media,
The communication media includes any medium for helping for computer program to be transmitted to another position from a position.Storage medium
It can be any usable medium that can be accessed by a general purpose or special purpose computer.As an example and not restrictive, the computer
Readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc memory apparatus, disk storage equipment or other magnetic
Property storage equipment, or can be used for carry or storage form be instruct or data structure required program code and can
Any other medium accessed by general or specialized computer or general or specialized processor.In addition, any connection is ok
It is properly termed as computer-readable medium.For example, if using coaxial cable, optical fiber cable, twisted pair, digital subscriber line
(DSL) or such as wireless technology of infrared ray, radio and microwave to send software from website, server or other remote sources,
Then above-mentioned coaxial cable, optical fiber cable, twisted pair, DSL or such as wireless technology of infrared ray, radio and microwave are included in
The definition of medium.As used herein, disk and CD include compact disk (CD), laser disk, CD, digital versatile disc
(DVD), floppy disk, Blu-ray disc, wherein disk usually magnetically reproduce data, and CD using laser optics reproduce data.On
The combination for stating content should also be as being included in the range of computer-readable medium.
From above-described embodiment as can be seen that server timing control provided in an embodiment of the present invention and signal monitoring board,
By the power-on and power-off timing of the control server when needing power-on and power-off, monitoring server key signal in operation and reception
And/or the technical solution of the state of the key signal of the monitoring of storage control 11, different server or different type can be directed to
Server to carry out timing control and signal monitoring simultaneously to work, reduction design and develop complexity, diminution board occupied space,
And the compression work period.
It is important to note that each device in each embodiment of above-mentioned board can be according to art technology
The demand of personnel and be exchanged with each other, change position, increase, deleting, therefore, these reasonable permutation and combination transformation in board
Protection scope of the present invention should belong to, and protection scope of the present invention should not be confined on the embodiment.
Based on above-mentioned purpose, the second aspect of the embodiment of the present invention, timing control can be carried out simultaneously by proposing one kind
With the embodiment of the server of signal monitoring work.The server includes:
Mainboard；
Enabled module, is connected to mainboard, and enabled module generates enable signal when server is run；
Above-mentioned server timing control and signal monitoring board, the connection of server timing control and signal monitoring board
Device is connected to mainboard.
It can be various electric terminal equipments, such as mobile phone, a number that the embodiment of the present invention, which discloses described device, equipment etc.,
Word assistant (PDA), tablet computer (PAD), smart television etc., are also possible to large-scale terminal device, such as server, therefore this hair
Protection scope disclosed in bright embodiment should not limit as certain certain types of device, equipment.The embodiment of the present invention discloses described
Client can be with the combining form of electronic hardware, computer software or both be applied to any one of the above electric terminal
In equipment.
Based on above-mentioned purpose, in terms of the third of the embodiment of the present invention, propose one kind can for different server or
Different types of server carrys out while carrying out the embodiment of the method for timing control and signal monitoring work.The method includes with
Lower step:
When powering on, the electrifying timing sequence of control server；
The enable signal of monitoring server in operation；
The state for the enable signal that reception and/or storage control 11 monitor；
In lower electricity, the lower electric timing of control server.
Various exemplary heterogeneous mixing memory systems, which can use, in conjunction with described in disclosure herein is designed to
The following component of function described here is executed to realize or execute: general processor, digital signal processor (DSP), dedicated collection
At circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, divide
Any combination of vertical hardware component or these components.General processor can be microprocessor, but alternatively, processing
Device can be any conventional processors, controller 11, microcontroller 11 or state machine.Processor also may be implemented as calculating and set
Standby combination, for example, the combination of DSP and microprocessor, multi-microprocessor, one or more microprocessors combination DSP and/or
Any other this configuration.
From above-described embodiment as can be seen that server provided in an embodiment of the present invention and timing control and signal monitoring side
Method, by the power-on and power-off timing of the control server when needing power-on and power-off, monitoring server enable signal in operation is simultaneously connect
The technical solution of the state for the enable signal that receipts and/or storage control 11 monitor, can be directed to different server or inhomogeneity
The server of type comes while carrying out timing control and signal monitoring work, and complexity is designed and developed in reduction, diminution board occupies sky
Between, and compression work period.
It is important to note that above-mentioned server and timing control and the embodiment of signal monitoring method use board
Embodiment illustrate the course of work of each module and step, those skilled in the art can be it is readily conceivable that by these
Technical characteristic is applied in the other embodiments of board.Certainly, since each device in board embodiment can be handed over mutually
It changes, changes position, increases, deleting, therefore, these reasonable permutation and combination transformation are supervised in server and timing control and signal
Prosecutor method should also be as belonging to the scope of protection of the present invention, and protection scope of the present invention should not be confined to the embodiment it
On.
It is exemplary embodiment disclosed by the invention above, it should be noted that in the sheet limited without departing substantially from claim
Under the premise of inventive embodiments scope of disclosure, it may be many modifications and modify.According to open embodiment described herein
The function of claim to a method, step and/or movement be not required to the execution of any particular order.In addition, although the present invention is implemented
Element disclosed in example can be described or be required in the form of individual, but be unless explicitly limited odd number, it is understood that be multiple.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.The embodiment of the present invention discloses embodiment sequence number
Description, does not represent the advantages or disadvantages of the embodiments.
It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, not
It is intended to imply that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；In the think of of the embodiment of the present invention
Under road, it can also be combined between the technical characteristic in above embodiments or different embodiments, and exist as described above
Many other variations of the different aspect of the embodiment of the present invention, for simplicity, they are not provided in details.Therefore, all at this
Within the spirit and principle of inventive embodiments, any omission, modification, equivalent replacement, improvement for being made etc. should be included in this hair
Within the protection scope of bright embodiment.
Claims (10)
1. a kind of server timing control and signal monitoring board characterized by comprising
Controller has multiple connection pins, is running for the power-on and power-off timing of control server and monitoring server simultaneously
In enable signal；
Connector, for establishing signal connection between the multiple connection pin and mainboard；
Register is connected to the controller, the shape of the enable signal for receiving and/or storing the controller monitoring
State.
2. server timing control according to claim 1 and signal monitoring board, which is characterized in that when the power-on and power-off
Sequence includes that machine open/close signal, multiple power supply enable signals, multiple power indication signals and machine open/close complete signal；Wherein, it opens
Machine signal and off signal share a connection pin, and signal is completed in booting and shutdown completes signal and shares a connection pin.
3. server timing control according to claim 2 and signal monitoring board, which is characterized in that the controller exists
When controlling electrifying timing sequence, by connector reception starting-up signal, successively transmission increases each level for electrical connection pins
Multiple power supply enable signals and receive the multiple power supply instructions letter for indicating that each level for electrical connection pins has built up respectively
Number and send booting complete signal.
4. server timing control according to claim 2 and signal monitoring board, which is characterized in that the controller exists
Under control when electric timing, by connector reception off signal, successively transmission reduces each level for electrical connection pins
Multiple power supply enable signals and receive the multiple power supply instructions letter for indicating that each level for electrical connection pins is decreased respectively
Number and send shutdown complete signal.
5. server timing control according to claim 1 and signal monitoring board, which is characterized in that the enable signal
Including timing control signal and universal input output signal.
6. server timing control according to claim 1 and signal monitoring board, which is characterized in that further include for defeated
The clock module of real-time time out；The register is connected to external memory and the clock module, and the register will be described
The state of the key signal of controller monitoring is stored to the corresponding time provided by the clock module to the external storage
In device.
7. server timing control according to claim 1 and signal monitoring board, which is characterized in that the register connects
It is connected to reading interface, the register is real by the reading interface by the state of the key signal of the controller monitoring
When export.
8. server timing control according to claim 1 and signal monitoring board, which is characterized in that further include being connected to
The interactive module of the controller and the connector, the interactive module are connected to the friendship of other boards by the connector
Mutual module makes multiple boards cooperate.
9. a kind of server characterized by comprising
Mainboard；
Enabled module, is connected to the mainboard, and the enabled module generates enable signal when server is run；
Server timing control and signal monitoring board as described in any one of claim 1-8, the server timing
Control and the connector of signal monitoring board are connected to the mainboard.
10. a kind of server timing control and signal monitoring method, which comprises the following steps:
When powering on, the electrifying timing sequence of control server；
The key signal of monitoring server in operation；
Receive and/or store the state of the key signal of the controller monitoring；
In lower electricity, the lower electric timing of control server.
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| CN109992082A (en) * | 2019-04-10 | 2019-07-09 | 苏州浪潮智能科技有限公司 | A kind of server method of supplying power to and device |
| CN110299941A (en) * | 2019-05-23 | 2019-10-01 | 广东瑞谷光网通信股份有限公司 | The accurate test method of optical module IIC Ready Time, electronic equipment and computer readable storage medium |
| CN114168393A (en) * | 2021-10-31 | 2022-03-11 | 苏州浪潮智能科技有限公司 | Server testing method, system, equipment and medium |
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Application publication date: 20190319 |