CN113127302B - Board GPIO monitoring method and device - Google Patents
Board GPIO monitoring method and device Download PDFInfo
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- CN113127302B CN113127302B CN202110412788.7A CN202110412788A CN113127302B CN 113127302 B CN113127302 B CN 113127302B CN 202110412788 A CN202110412788 A CN 202110412788A CN 113127302 B CN113127302 B CN 113127302B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method and a device for monitoring GPIO of a board, wherein the method comprises the following steps: the GPIO bus is connected to the GPIO pin of the board card to acquire and monitor the GPIO state; buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes; in response to receiving an I2C read command from the baseboard management controller, the GPIO state in the register is fed back to the I2C interface of the baseboard management controller via the I2C bus. The invention can reduce the monitoring pin requirement of the BMC, release the space of the main board and reduce the hardware cost.
Description
Technical Field
The invention relates to the field of computers, in particular to a method and a device for monitoring GPIO of a board card.
Background
Many GPIO (general purpose input output) pins are often used on the hardware board of the server to control logic and to monitor the status of the system, whether it is the overall system status, IC (integrated circuit chip) to IC, system board to system board, IC to system board, these are almost individually monitored using GPIO pins, even when the server is mostly handed over to the BMC (baseboard management controller) to monitor the individual IC and system board status. However, the BMC needs to manage all information and control system logic on the monitor board, which may cause insufficient use of the pins in the server.
In order to solve this problem, a plurality of IO expanders (I/o expansion chips) are often added, and the BMC controls the plurality of I/o expansion chips in an I2C (internal integrated circuit bus) manner to complement the GPIO pins insufficient for the BMC. At the same time, some similar monitoring status is removed, for example, if there are many small system boards on the board, each system board has a plurality of monitoring signals, and when many pins are needed to be used and insufficient, and when the space on the board is insufficient to put the input/output expansion chip, the situation often needs to be replaced. Another is to alter the design on the simplified system board, assuming that a certain signal on the system board takes 10 pins, but if these 10 pins need to be monitored individually, the BMC needs 10 GPIO pins. The design on the system board is simplified, and the 10 pins are pulled to the BMC in a wire and mode to monitor, so that when signals change, the BMC can only know the problem on the system card but cannot know which pin is.
Aiming at the problems that GPIO pins of a BMC in the prior art are insufficient in number and an input/output expansion chip occupies too large main board space, no effective solution exists at present.
Disclosure of Invention
Therefore, an objective of the embodiments of the present invention is to provide a method and a device for monitoring GPIO of a board, which can reduce the monitoring pin requirement of the BMC, release the motherboard space and reduce the hardware cost.
Based on the above object, a first aspect of the embodiments of the present invention provides a method for monitoring GPIO of a board, including using a complex programmable logic device to perform the following steps:
the GPIO bus is connected to the GPIO pin of the board card to acquire and monitor the GPIO state;
buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes;
in response to receiving an I2C read command from the baseboard management controller, the GPIO state in the register is fed back to the I2C interface of the baseboard management controller via the I2C bus.
In some implementations, the complex programmable logic device includes a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: the local GPIO pins of the complex programmable logic device are respectively connected to the GPIO pins of a plurality of boards which need to be monitored by the baseboard management controller.
In some embodiments, after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs a logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
In some embodiments, the I2C interface of the baseboard management controller is fed back with the GPIO status in the register through the I2C bus, and the preprocessing result is fed back together.
In some embodiments, the I2C interface that feeds back the GPIO status in the register to the baseboard management controller over the I2C bus includes: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device and the GPIO read instruction is used to access a register to read the GPIO state.
A second aspect of an embodiment of the present invention provides an apparatus, comprising:
a baseboard management controller and a board; and
a complex programmable logic device connected to the baseboard management controller and the board, storing executable program code, the complex programmable logic device performing the following steps when the program code is executed:
the GPIO bus is connected to the GPIO pin of the board card to acquire and monitor the GPIO state;
buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes;
in response to receiving an I2C read command from the baseboard management controller, the GPIO state in the register is fed back to the I2C interface of the baseboard management controller via the I2C bus.
In some implementations, the complex programmable logic device includes a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: the local GPIO pins of the complex programmable logic device are respectively connected to the GPIO pins of a plurality of boards which need to be monitored by the baseboard management controller.
In some embodiments, after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs a logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
In some embodiments, the I2C interface of the baseboard management controller is fed back with the GPIO status in the register through the I2C bus, and the preprocessing result is fed back together.
In some embodiments, the I2C interface that feeds back the GPIO status in the register to the baseboard management controller over the I2C bus includes: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device and the GPIO read instruction is used to access a register to read the GPIO state.
The invention has the following beneficial technical effects: the monitoring method and the device for the GPIO of the board card are connected to the GPIO pin of the board card through the GPIO bus to acquire and monitor the GPIO state; buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes; in response to receiving the I2C reading instruction of the baseboard management controller, the technical scheme of feeding back the GPIO state in the register to the I2C interface of the baseboard management controller through the I2C bus can reduce the monitoring pin requirement of the BMC, release the main board space and reduce the hardware cost.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a method for monitoring board GPIO provided by the present invention;
fig. 2 is a schematic diagram of connection relation of a board GPIO monitoring method provided by the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
Based on the above objective, the first aspect of the embodiments of the present invention provides an embodiment of a board GPIO monitoring method that reduces the monitor pin requirement of the BMC, frees the motherboard space and reduces the hardware cost. Fig. 1 is a schematic flow chart of a monitoring method of a board GPIO.
The board GPIO monitoring method, as shown in FIG. 1, comprises the following steps performed by using a complex programmable logic device:
step S101, connecting to GPIO pins of the board card through a GPIO bus to acquire and monitor the GPIO state;
step S103, in response to the acquisition or monitoring of the change of the GPIO state, buffering the GPIO state into a register corresponding to the GPIO pin;
in step S105, in response to receiving the I2C read command of the baseboard management controller, the GPIO status in the register is fed back to the I2C interface of the baseboard management controller through the I2C bus.
The invention does not use a plurality of IO expanders, but connects GPIO pins of a System card to GPIO of a CPLD (complex programmable logic device), and the BMC monitors the GPIO of the card in an I2C mode. After the GPIO of the boards is pulled to the CPLD, the signals can be analyzed and preprocessed through the CPLD, for example, the GPIO of the boards is determined to be triggered several times or used for performing other logic control in the CPLD and the like, so that not only is the space and the cost saved, but also the state monitoring beyond the pretreatment of the CPLD can be achieved.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by a computer program for instructing relevant hardware, where the program may be stored on a computer readable storage medium, and where the program, when executed, may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the method embodiments previously described.
In some implementations, the complex programmable logic device includes a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: the local GPIO pins of the complex programmable logic device are respectively connected to the GPIO pins of a plurality of boards which need to be monitored by the baseboard management controller.
In some embodiments, after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs a logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
In some embodiments, the I2C interface of the baseboard management controller is fed back with the GPIO status in the register through the I2C bus, and the preprocessing result is fed back together.
In some embodiments, the I2C interface that feeds back the GPIO status in the register to the baseboard management controller over the I2C bus includes: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device and the GPIO read instruction is used to access a register to read the GPIO state.
The following describes a specific embodiment of the present invention further with reference to the specific embodiment shown in fig. 2. Referring to fig. 2, 1 is a BMC for monitoring, 4 is a CPLD that switches over GPIO pins, and the BMC and the CPLD are connected through an I2C bus. 2 and 3 are boards (not limited to two boards, but more) that are all connected to the same CPLD using GPIO buses, the CPLD having enough GPIO pins and having a volume much smaller than the volume of multiple input-output expansion chips.
After the power-on time sequence of the BMC and the board card is completed, the BMC starts to monitor the CPLD by using an I2C mode, the GPIO state of the board card can be changed at any time and transmitted to the CPLD, the BMC can know the GPIO state of the board card through the I2C mode, in addition, the CPLD can also analyze the GPIO condition in addition, for example, the GPIO of the board card is triggered several times and the like, and the BMC can also know the GPIO state of the board card after the CPLD processes. The CPLD can store the GPIO of the board card in a register, and generates I2C to GPIO by using the firmware of the CPLD, so that the BMC can directly know the state of the register in the CPLD through the I2C mode, and then can know the GPIO state of the board card.
As can be seen from the above embodiments, in the method for monitoring a GPIO of a board card provided by the embodiments of the present invention, a complex programmable logic device is used to connect a GPIO bus to a GPIO pin of the board card, so as to obtain and monitor a GPIO state; buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes; in response to receiving the I2C reading instruction of the baseboard management controller, the technical scheme of feeding back the GPIO state in the register to the I2C interface of the baseboard management controller through the I2C bus can reduce the monitoring pin requirement of the BMC, release the main board space and reduce the hardware cost.
It should be noted that, in the foregoing embodiments of the board GPIO monitoring method, the steps may be intersected, replaced, added and deleted, so that the board GPIO monitoring method according to the reasonable permutation and combination should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiments.
Based on the above objective, a second aspect of the embodiments of the present invention provides an embodiment of a board GPIO monitoring device that reduces the monitor pin requirements of the BMC, frees up the motherboard space and reduces the hardware cost. The device comprises:
a baseboard management controller and a board; and
a complex programmable logic device connected to the baseboard management controller and the board, storing executable program code, the complex programmable logic device performing the following steps when the program code is executed:
the GPIO bus is connected to the GPIO pin of the board card to acquire and monitor the GPIO state;
buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes;
in response to receiving an I2C read command from the baseboard management controller, the GPIO state in the register is fed back to the I2C interface of the baseboard management controller via the I2C bus.
In some implementations, the complex programmable logic device includes a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: the local GPIO pins of the complex programmable logic device are respectively connected to the GPIO pins of a plurality of boards which need to be monitored by the baseboard management controller.
In some embodiments, after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs a logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
In some embodiments, the I2C interface of the baseboard management controller is fed back with the GPIO status in the register through the I2C bus, and the preprocessing result is fed back together.
In some embodiments, the I2C interface that feeds back the GPIO status in the register to the baseboard management controller over the I2C bus includes: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device and the GPIO read instruction is used to access a register to read the GPIO state.
As can be seen from the above embodiments, the monitoring device for board GPIO provided by the embodiments of the present invention uses a complex programmable logic device to connect a GPIO bus to a GPIO pin of a board card, so as to obtain and monitor a GPIO state; buffering the GPIO state into a register corresponding to the GPIO pin in response to acquiring or monitoring that the GPIO state changes; in response to receiving the I2C reading instruction of the baseboard management controller, the technical scheme of feeding back the GPIO state in the register to the I2C interface of the baseboard management controller through the I2C bus can reduce the monitoring pin requirement of the BMC, release the main board space and reduce the hardware cost.
It should be noted that, in the embodiment of the device, the embodiment of the monitoring method of the board GPIO is used to specifically describe the working process of each module, and those skilled in the art can easily think that these modules are applied to other embodiments of the monitoring method of the board GPIO. Of course, since the steps in the embodiment of the board GPIO monitoring method may be intersected, replaced, added and subtracted, the reasonable arrangement and combination of the devices should also belong to the protection scope of the present invention, and the protection scope of the present invention should not be limited to the embodiment.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (8)
1. The board GPIO monitoring method is characterized by comprising the following steps of using a complex programmable logic device to execute:
connecting the complex programmable logic device to a GPIO pin of a board card through a GPIO bus to acquire and monitor the GPIO state;
in response to acquiring or monitoring that the GPIO state changes, buffering the GPIO state in a register corresponding to the GPIO pin;
in response to receiving an I2C read instruction from a baseboard management controller, feeding back the GPIO state in the register to an I2C interface of the baseboard management controller through an I2C bus,
wherein the complex programmable logic device comprises a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: and respectively connecting the local GPIO pins of the complex programmable logic device to the GPIO pins of the board card to be monitored by the baseboard management controller one by one.
2. The method of claim 1, wherein after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs a logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
3. The method of claim 2, wherein the GPIO status in the register is fed back to the I2C interface of the baseboard management controller via an I2C bus, and the preprocessing result is fed back together.
4. The method of claim 1, wherein feeding back the GPIO status in the register to the I2C interface of the baseboard management controller via an I2C bus comprises: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device, and the register is accessed using the GPIO read instruction to read the GPIO state.
5. Monitoring device of board GPIO, its characterized in that includes:
the baseboard management controller and the board card; and
a complex programmable logic device coupled to the baseboard management controller and the board card, storing executable program code, the complex programmable logic device performing the following steps when the program code is executed:
the GPIO bus is connected to the GPIO pin of the board card to acquire and monitor the GPIO state;
in response to acquiring or monitoring that the GPIO state changes, buffering the GPIO state in a register corresponding to the GPIO pin;
in response to receiving an I2C read instruction from a baseboard management controller, feeding back the GPIO state in the register to an I2C interface of the baseboard management controller through an I2C bus,
wherein the complex programmable logic device comprises a plurality of local GPIO pins; GPIO pins connected to the board card through the GPIO bus include: and respectively connecting the local GPIO pins of the complex programmable logic device to the GPIO pins of the board card to be monitored by the baseboard management controller one by one.
6. The apparatus of claim 5, wherein after buffering the GPIO state in a register corresponding to the GPIO pin, the complex programmable logic device further performs logic decision-based preprocessing on the GPIO state to obtain a preprocessing result.
7. The apparatus of claim 6, wherein the GPIO status in the register is fed back to the I2C interface of the baseboard management controller via an I2C bus, and wherein the preprocessing result is fed back together.
8. The apparatus of claim 5, wherein feeding back the GPIO status in the register to the I2C interface of the baseboard management controller via an I2C bus comprises: the I2C read instruction is converted to a GPIO read instruction using firmware within the complex programmable logic device, and the register is accessed using the GPIO read instruction to read the GPIO state.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113468027B (en) * | 2021-09-03 | 2021-11-19 | 北京壁仞科技开发有限公司 | Monitoring device address management method and device, substrate management controller and equipment |
| CN114562473A (en) * | 2022-01-28 | 2022-05-31 | 山东云海国创云计算装备产业创新中心有限公司 | Fan control method, device, equipment and medium |
| CN114721900B (en) * | 2022-03-18 | 2022-11-25 | 北京百度网讯科技有限公司 | Connection relation establishing method, mainboard, device, equipment and storage medium |
| CN114860635B (en) * | 2022-07-07 | 2022-09-23 | 北京智芯半导体科技有限公司 | General input/output interface control method, device, storage medium and circuit board |
| CN116149957B (en) * | 2023-04-19 | 2023-06-20 | 湖南博匠信息科技有限公司 | Method for saving server power-on and power-off records through BMC |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1987835A (en) * | 2005-12-22 | 2007-06-27 | 上海贝尔阿尔卡特股份有限公司 | System for realizing multiple FPGA image file serial unload and its relative computer |
| CN102236631A (en) * | 2010-04-21 | 2011-11-09 | 英业达股份有限公司 | Calculator system |
| CN103500148A (en) * | 2013-10-18 | 2014-01-08 | 深圳市新格林耐特通信技术有限公司 | Device and method for enabling master control card to read type of service line card |
| CN104375923A (en) * | 2014-11-24 | 2015-02-25 | 英业达科技有限公司 | Hard disk drive (HDD) running state detection system |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| CN110098965A (en) * | 2019-05-07 | 2019-08-06 | 苏州浪潮智能科技有限公司 | A kind of server management system and method |
| CN111966567A (en) * | 2020-08-11 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Error indicator and assembly of central processing unit |
| CN111984471A (en) * | 2020-08-14 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Cabinet power BMC redundancy management system and method |
| CN112463502A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Method, device and system for detecting pin state of programmable logic device |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104375915A (en) * | 2014-12-16 | 2015-02-25 | 浪潮电子信息产业股份有限公司 | Method for interactively and quickly diagnosing mainboard time sequence by utilizing BMC (baseboard management controller) and CPLD (complex programmable logic device) |
| CN106970866A (en) * | 2017-03-13 | 2017-07-21 | 郑州云海信息技术有限公司 | A kind of disk monitor system and method |
| CN107832199A (en) * | 2017-10-10 | 2018-03-23 | 曙光信息产业(北京)有限公司 | Hard disk monitoring system based on CPLD |
| CN108089964A (en) * | 2017-12-07 | 2018-05-29 | 郑州云海信息技术有限公司 | A kind of device and method by BMC monitoring server CPLD states |
| US20190286590A1 (en) * | 2018-03-14 | 2019-09-19 | Quanta Computer Inc. | Cpld cache application in a multi-master topology system |
| CN109508279A (en) * | 2018-11-28 | 2019-03-22 | 郑州云海信息技术有限公司 | A kind of server monitoring device, method and its system |
| CN109766248A (en) * | 2019-01-04 | 2019-05-17 | 浪潮商用机器有限公司 | System failure signal acquiring method, device, server and readable storage medium storing program for executing |
| CN110162499B (en) * | 2019-05-29 | 2021-03-02 | 苏州浪潮智能科技有限公司 | PECI bus switching device, method and system |
| CN110399328B (en) * | 2019-06-28 | 2022-07-26 | 苏州浪潮智能科技有限公司 | Control method and device for board-mounted graphics processor |
| CN110515801A (en) * | 2019-08-23 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of OLED shows equipment, the monitoring method of server state and server |
| CN110659233A (en) * | 2019-09-11 | 2020-01-07 | 苏州浪潮智能科技有限公司 | Serial port information switching device and server |
| CN110825204A (en) * | 2019-11-06 | 2020-02-21 | 深圳宝龙达信创科技股份有限公司 | Mainboard of electronic equipment and power supply information management method |
| CN111858411B (en) * | 2020-06-12 | 2022-10-18 | 苏州浪潮智能科技有限公司 | System and method for realizing out-of-band interaction of server Expander cards |
| CN112463493A (en) * | 2020-12-03 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Board card position detection device and method |
| CN112463538A (en) * | 2020-12-10 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Liquid leakage detection and alarm system, method, device and equipment |
-
2021
- 2021-04-16 CN CN202110412788.7A patent/CN113127302B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1987835A (en) * | 2005-12-22 | 2007-06-27 | 上海贝尔阿尔卡特股份有限公司 | System for realizing multiple FPGA image file serial unload and its relative computer |
| CN102236631A (en) * | 2010-04-21 | 2011-11-09 | 英业达股份有限公司 | Calculator system |
| CN103500148A (en) * | 2013-10-18 | 2014-01-08 | 深圳市新格林耐特通信技术有限公司 | Device and method for enabling master control card to read type of service line card |
| CN104375923A (en) * | 2014-11-24 | 2015-02-25 | 英业达科技有限公司 | Hard disk drive (HDD) running state detection system |
| CN109491946A (en) * | 2018-11-12 | 2019-03-19 | 郑州云海信息技术有限公司 | A kind of chip and method for I2C bus extension |
| CN110098965A (en) * | 2019-05-07 | 2019-08-06 | 苏州浪潮智能科技有限公司 | A kind of server management system and method |
| CN111966567A (en) * | 2020-08-11 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Error indicator and assembly of central processing unit |
| CN111984471A (en) * | 2020-08-14 | 2020-11-24 | 苏州浪潮智能科技有限公司 | Cabinet power BMC redundancy management system and method |
| CN112463502A (en) * | 2020-12-11 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Method, device and system for detecting pin state of programmable logic device |
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