CN114860635B - General input/output interface control method, device, storage medium and circuit board - Google Patents
General input/output interface control method, device, storage medium and circuit board Download PDFInfo
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- CN114860635B CN114860635B CN202210792431.0A CN202210792431A CN114860635B CN 114860635 B CN114860635 B CN 114860635B CN 202210792431 A CN202210792431 A CN 202210792431A CN 114860635 B CN114860635 B CN 114860635B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method and a device for controlling a universal input/output interface, a storage medium and a circuit board. The general input and output interface control method comprises the following steps: firstly, calling a driving interface of a virtual device node through a protocol analysis service to inquire the state of a GPIO pin in a first circuit board to obtain a GPIO state; and secondly, the GPIO state is sent to the second circuit board through the protocol analysis service, so that the second circuit board synchronizes the GPIO state to the corresponding GPIO pin in the second circuit board. The control method of the universal input/output interface can reduce the electromagnetic compatibility risk and the equipment cost.
Description
Technical Field
The present invention relates to the field of circuit communication technologies, and in particular, to a method and an apparatus for controlling a General Purpose Input/Output interface GPIO (General Purpose Input/Output interface), a storage medium, and a circuit board.
Background
With the increasing data processing requirements of power terminal equipment, the increase of the main frequency of the main controller causes the increase of heat accumulated in the terminal, so that higher requirements are provided for the heat dissipation performance of the equipment. The internal structure of the terminal device is usually limited, and the design that a plurality of circuit boards exist in the terminal is common, so that the requirement of multi-path GPIO state synchronization function between different circuit boards is more urgent in order to adapt to the structural design and the heat dissipation requirement.
Because inter-board connection may increase the risk of the electromagnetic compatibility problem during the communication process and reduce the communication stability, most methods for ensuring the electromagnetic compatibility performance during the multi-path GPIO communication between two boards in the related art are realized by increasing shielding through the inter-board connection or optimizing the layout of the circuit board and reducing the connection, but in order to solve the electromagnetic compatibility problem, the inter-board connection with a shielding function is used, which may increase the equipment cost, and the method for changing the layout may generally increase the difficulty of the circuit board layout and wiring and may cause the reduction of the heat dissipation performance. Most methods for realizing control functions among multiple boards based on GPIO states in related technologies cannot reduce electromagnetic compatibility risks and equipment cost caused by a large number of connecting wires among the boards.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the first purpose of the present invention is to provide a GPIO control method for general purpose input output interfaces to reduce the risk of electromagnetic compatibility and the cost of the device.
The second purpose of the present invention is to provide a GPIO control device for general purpose input output interface.
A third object of the invention is to propose a computer-readable storage medium.
A fourth object of the present invention is to provide a circuit board.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a method for controlling a general purpose input output interface GPIO, where the method includes: calling a driving interface of a virtual device node through a protocol analysis service to inquire the state of a GPIO pin in a first circuit board to obtain a GPIO state; and sending the GPIO state to a second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
According to the general input/output interface GPIO control method provided by the embodiment of the invention, firstly, the driving interface of the virtual device node is called by the protocol analysis service to inquire the state of the GPIO pin in the first circuit board to obtain the GPIO state, and secondly, the GPIO state is sent to the second circuit board by the protocol analysis service so that the second circuit board synchronizes the GPIO state to the corresponding GPIO pin in the second circuit board. Therefore, the synchronization of the GPIO state between the two circuit boards can be realized, the number of connecting wires between the boards is reduced, and the risk of electromagnetic compatibility and the equipment cost are reduced.
In addition, the GPIO control method for a general purpose input/output interface proposed in the above embodiment of the present invention may also have the following additional technical features:
in an embodiment of the present invention, when the driver interface of the first circuit board is called, an operation instruction is synchronized to a shared register, where the driver interface of the virtual device node obtains the operation instruction from the shared register and converts the operation instruction into the GPIO state.
In an embodiment of the present invention, the sending, by the protocol parsing service, the GPIO state to a second circuit board includes: and packaging the GPIO state into frames according to a functional module interface protocol through the protocol analysis service, and sending the frames to the second circuit board.
In one embodiment of the invention, the first circuit board and the second circuit board communicate through a USB analog serial port.
In one embodiment of the present invention, the GPIO states comprise output signal states comprising functions and data of an output signal.
In an embodiment of the present invention, the first circuit board is a Linux system function board, and the second circuit board is a single chip microcomputer function board.
In order to achieve the above object, a second embodiment of the present invention provides a GPIO control apparatus, including: the calling module is used for calling a driving interface of the virtual device node through the protocol analysis service to inquire the state of a GPIO pin in the first circuit board so as to obtain a GPIO state; and the sending module is used for sending the GPIO state to a second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
The general input/output interface GPIO control device comprises a calling module and a sending module. The calling module is used for calling a driving interface of the virtual device node through the protocol analysis service to inquire the state of a GPIO pin in the first circuit board to obtain a GPIO state; and the sending module is used for sending the GPIO state to the second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to the corresponding GPIO pin in the second circuit board. Therefore, the general input/output interface GPIO control device can realize the synchronization of GPIO states between two circuit boards, reduce the number of connecting wires between the boards and reduce the risk of electromagnetic compatibility and the equipment cost.
In addition, the GPIO control device provided in the above embodiments of the present invention may also have the following additional technical features:
in an embodiment of the present invention, when the driving interface of the first circuit board is called, an operation instruction is synchronized to a shared register, where the driving interface of the virtual device node obtains the operation instruction from the shared register and converts the operation instruction into the GPIO state.
In an embodiment of the present invention, the sending module is specifically configured to: and packaging the GPIO state into frames according to a functional module interface protocol through the protocol analysis service, and sending the frames to the second circuit board.
In order to achieve the above object, a third embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the GPIO control method as described above.
According to the computer readable storage medium of the embodiment of the invention, when a computer program on the computer readable storage medium is executed by a processor, by implementing the general input/output interface GPIO control method, firstly, a driving interface of a virtual device node is called by a protocol analysis service to inquire the state of a GPIO pin in a first circuit board to obtain a GPIO state, and then, the GPIO state is sent to a second circuit board by the protocol analysis service, so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board. Therefore, the GPIO control method can realize the synchronization of GPIO states between two circuit boards, reduce the number of connecting wires between the boards, and reduce the risk of electromagnetic compatibility problems and equipment cost.
In order to achieve the above object, a fourth embodiment of the present invention provides a circuit board, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the GPIO control method is implemented as described above.
According to the circuit board provided by the embodiment of the invention, through the GPIO control method, the state of the GPIO pin in the first circuit board is inquired by calling the driving interface of the virtual device node through the protocol analysis service to obtain the GPIO state, and then the GPIO state is sent to the second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to the corresponding GPIO pin in the second circuit board. Therefore, the circuit board can realize the synchronization of GPIO states between the two circuit boards through a general input/output interface GPIO control method, reduce the number of connecting wires between the boards, and reduce the risk of electromagnetic compatibility problems and the equipment cost.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a flowchart of a general purpose input output interface GPIO control method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a frame structure of one example of the present invention;
FIG. 3 is a schematic diagram of a protocol conversion module information class definition according to an example of the present invention;
FIG. 4 is a schematic diagram illustrating an exemplary GPIO control method of the present invention;
fig. 5 is a flowchart of another example general purpose input output interface GPIO control method of the present invention;
fig. 6 is a block diagram of a general purpose input/output interface GPIO control apparatus according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
The following describes a general purpose input/output interface GPIO control method, apparatus, storage medium, and circuit board according to an embodiment of the present invention with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for controlling a GPIO according to an embodiment of the present invention.
As shown in fig. 1, the method for controlling a general purpose input output interface GPIO includes:
s101, calling a driving interface of a virtual device node through a protocol analysis service to inquire the state of a GPIO pin in a first circuit board to obtain the GPIO state.
The virtual device node is a virtual device integrated on the first circuit board, and provides a driving interface of the virtual device node. The driving interface of the virtual device node is positioned in a hardware abstraction layer, is an intermediate implementation process additionally added for realizing a standard hardware abstraction layer interface, and has the functions of defining a plurality of GPIO operation instruction sets defined by specifications, supporting the acquisition of GPIO states and the like. The GPIO operation instruction set comprises a corresponding relation between operation instructions and GPIO states.
The application program A is a protocol analysis service on the first circuit board and used for interacting with the virtual device node to realize synchronization of the GPIO state on the first circuit board to the second circuit board. Similarly, the second circuit board is also provided with an application program B, and the application program B is a second protocol analysis service on the second circuit board.
The first circuit board further includes an application layer, the application layer software operates in a user mode, a program in the user mode is an application program a, the application program a can call the virtual device node through the driving interface of the virtual device node, and the application layer is an application layer corresponding to a system where the first circuit board is located, for example, if the first circuit board is a Linux system function board, the application layer is an application layer corresponding to a Linux system.
The first circuit board comprises a driving interface of the first circuit board, and the driving interface is a driving interface defined by a specification and can be used for controlling the state of the GPIO pin.
Specifically, when the control system on the first circuit board determines that a certain function needs to be implemented, the control system may send an operation instruction corresponding to the function, and the protocol analysis service on the first circuit board calls the driving interface of the first circuit board to operate, so as to synchronize the operation instruction through the driving interface of the first circuit board, and convert the operation instruction into a GPIO state through a plurality of GPIO operation instruction sets defined by the query specification.
When the driving interface of the first circuit board is called, the operation instruction is synchronized to the shared register, and the protocol analysis service calls the driving interface of the virtual device node, so that the driving interface of the virtual device node obtains the operation instruction from the shared register and converts the operation instruction into a GPIO state. The shared register is a group of registers in the kernel space of the first circuit board.
In addition, when the hardware abstraction layer and the application layer are designed and developed, the hardware abstraction layer and the application layer need to be designed and developed according to technical specifications.
And S102, sending the GPIO state to a second circuit board through a protocol analysis service so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
Specifically, after the protocol analysis service calls a driving interface of the virtual device node to read the shared register, the acquired GPIO state can be packaged into frames through the protocol analysis service according to a functional module interface protocol, and then the first circuit board communicates with the second circuit board through the USB analog serial port and sends the packaged GPIO state to the second circuit board through the USB analog serial port. And the second circuit board analyzes the received frame to obtain the GPIO state and outputs the GPIO state to the corresponding GPIO pin.
The GPIO state sent by the first circuit board to the second circuit board comprises an output signal state, and the output signal state comprises the function and data of an output signal. Since the GPIO control in this application is bi-directional, i.e., the first circuit board can read and write the GPIO state of the GPIO pin of the second circuit board, and the second circuit board can also read and write the GPIO state of the first circuit board, if the second circuit board sends the GPIO state to the first circuit board, the GPIO state includes an input signal state, which includes the function and data of the input signal. The input signal is in a GPIO state sent by the second circuit board to the first circuit board, and the output signal is in a GPIO state sent by the first circuit board to the second circuit board. When the second circuit board needs to send the GPIO state to the first circuit board, the specific control method may refer to the specific control method when the first circuit board needs to send the GPIO state to the second circuit board, which is not described herein again.
It should be noted that, the first circuit board further includes a protocol conversion module, and after the GPIO state is obtained, the protocol analysis service calls the protocol conversion module to package the GPIO state into a frame, so that the frame can be transmitted on the USB analog serial port. The protocol parsing service of the first circuit board encapsulates the GPIO state into frames using a functional module interface protocol, and the specific frame structure is shown in fig. 2. The protocol conversion module information class defines the format of an application layer data unit of an input signal state and an output signal state, the application layer data unit is a data packet transmitted by an application layer, GPIO state information is packaged into frames according to a specific marking rule and a coding rule, the marking rule can follow the abstract syntax of ASN.1, and the coding rule can follow A-XDR. The protocol conversion module information class definition may be as shown in fig. 3, where the protocol conversion module information class defines an application layer data unit format of an input signal state and an output signal state, the input signal state includes an input signal function enum and input signal data signed, the output signal state includes an output signal function enum and output signal data signed, the input signal state is represented by a symbol F000, the output signal state is represented by a symbol F200, and the symbols representing the input signal state and the output signal state are represented by a symbol DT, and further includes array, structure of the input signal, array, and structure of the output signal. The protocol conversion module information class definition is a part of a data field in a functional module interface protocol frame structure, and the array and the structure are specific structures defined by the protocol conversion module information class.
In order to better understand the GPIO control method of the general purpose input output interface according to the embodiment of the present invention, the embodiment of the present invention is described in detail with reference to the specific example shown in fig. 4. In this specific example, the first circuit board is a Linux system function board, and the second circuit board is a single chip microcomputer function board.
Specifically, a USB analog serial port is used between the Linux system function board and the singlechip function board for communication. The virtual device node of the Linux system function board realizes a plurality of GPIO operation instruction sets defined by specifications and provides a uniform driving interface. The Linux system function board comprises a plurality of drive interfaces defined by specifications, such as a drive A defined by the specifications, a drive B defined by the specifications, and the like.
When calling a drive interface defined by a specification, the application program A can write specific data of an operation instruction into a shared register corresponding to a virtual device node, then a protocol analysis service in a Linux system function board calls the drive interface of the virtual device node, queries the operation instruction corresponding to the drive A in a shared register list, encodes and packages the acquired GPIO state of the drive A into frames according to a functional module protocol format, and sends the encoded and packaged GPIO state into a single chip microcomputer function board through a USB analog serial port, a single chip Microcomputer (MCU) of the single chip microcomputer function board analyzes contents in the protocol frames, outputs the state of the drive A to corresponding GPIO pins, and completes synchronization of GPIO states between two circuit boards.
Therefore, the operation instruction is synchronized to the shared register, the virtual device node is used for converting the operation instruction into the GPIO state, the GPIO state is integrated and synchronized to the other circuit board, the shared register operated by the virtual device node does not correspond to a specific GPIO pin on the first circuit board running the virtual device node, and when the state of the GPIO device changes, the pin level on the first circuit board does not change.
In an embodiment of the present invention, referring to fig. 5, the second circuit board may obtain a GPIO state set of a plurality of GPIO pins in the first circuit board, and further obtain a GPIO state list according to states of the plurality of GPIO pins, and output the GPIO state list to the corresponding GPIO pin. Similarly, the first circuit board may also obtain a GPIO state set of a plurality of GPIO pins in the second circuit board, and further obtain a GPIO transition list according to the states of the plurality of GPIO pins and output the GPIO transition list to the corresponding GPIO pins.
To sum up, the GPIO control method according to the embodiment of the present invention first calls a driver interface of a virtual device node to query states of GPIO pins in a first circuit board through a protocol parsing service to obtain GPIO states, and then sends the GPIO states to a second circuit board through the protocol parsing service, so that the second circuit board synchronizes the GPIO states to corresponding GPIO pins in the second circuit board. Therefore, the synchronization of the GPIO state between the two circuit boards can be realized, the number of connecting wires between the boards is reduced, the risk of electromagnetic compatibility problems and the equipment cost are reduced, and the driving interface defined by the original specification does not need to be changed while the technical effect is realized.
Furthermore, the invention provides a general purpose input/output interface GPIO control device.
Fig. 6 is a block diagram of a general purpose input/output interface GPIO control device according to an embodiment of the present invention.
As shown in fig. 6, the GPIO control device 100 includes a calling module 10 and a sending module 20.
Specifically, the calling module 10 is configured to call a driving interface of the virtual device node through the protocol parsing service to query a state of a GPIO pin in the first circuit board, so as to obtain a GPIO state; and the sending module 20 is configured to send the GPIO state to the second circuit board through the protocol parsing service, so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
In an embodiment of the present invention, when the driving interface of the first circuit board is called, the operation instruction is synchronized to the shared register, wherein the driving interface of the virtual device node obtains the operation instruction from the shared register and converts the operation instruction into the GPIO state.
In an embodiment of the present invention, the sending module 20 is specifically configured to: and packaging the GPIO state into frames according to a functional module interface protocol through a protocol analysis service, and sending the frames to the second circuit board.
It should be noted that, for other specific implementations of the GPIO control device according to the embodiment of the present invention, reference may be made to the above-mentioned GPIO control method for the GPIO interface.
The general input/output interface GPIO control device of the embodiment of the invention firstly calls the driving interface of the virtual device node to inquire the state of the GPIO pin in the first circuit board through the protocol analysis service to obtain the GPIO state, and then sends the GPIO state to the second circuit board through the protocol analysis service to enable the second circuit board to synchronize the GPIO state to the corresponding GPIO pin in the second circuit board. Therefore, the synchronization of the GPIO state between the two circuit boards can be realized, the number of connecting wires between the boards is reduced, and the risk of electromagnetic compatibility and the equipment cost are reduced.
Further, the present invention proposes a computer-readable storage medium.
In the embodiment of the present invention, a computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, the method for controlling a general purpose input output interface GPIO is implemented.
When the computer program on the computer readable storage medium is executed by the processor, the state of the GPIO pin in the first circuit board is firstly inquired through a driving interface of the protocol analysis service calling virtual device node to obtain the GPIO state, and then the GPIO state is sent to the second circuit board through the protocol analysis service, so that the GPIO state is synchronized to the corresponding GPIO pin in the second circuit board by the second circuit board. Therefore, the synchronization of the GPIO state between the two circuit boards can be realized, the number of connecting wires between the boards is reduced, and the risk of electromagnetic compatibility and the equipment cost are reduced.
Furthermore, the invention provides a circuit board.
In the embodiment of the present invention, the electronic device includes a memory, a processor, and a computer program stored on the memory, and when the computer program is executed by the processor, the above-mentioned GPIO control method is implemented.
According to the circuit board provided by the embodiment of the invention, by implementing the GPIO control method for the general input/output interface, firstly, the driving interface of the virtual device node is called by the protocol analysis service to inquire the state of the GPIO pin in the first circuit board to obtain the GPIO state, and secondly, the GPIO state is sent to the second circuit board by the protocol analysis service, so that the second circuit board synchronizes the GPIO state to the corresponding GPIO pin in the second circuit board. Therefore, the synchronization of the GPIO state between the two circuit boards can be realized, the number of connecting wires between the boards is reduced, and the risk of electromagnetic compatibility and the equipment cost are reduced.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein may be considered as a sequential list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description herein, the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like refer to orientations and positional relationships based on the orientation shown in the drawings, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description of the present specification, unless otherwise specified, the terms "mounted", "connected", "fixed", and the like are to be understood broadly, and may be, for example, fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are exemplary and not to be construed as limiting the present invention, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. A general purpose input/output interface (GPIO) control method is characterized by comprising the following steps:
calling a driving interface of a virtual device node through a protocol analysis service to obtain an operation instruction from a shared register, and converting the operation instruction into a state of a GPIO pin in a first circuit board to obtain a GPIO state, wherein the first circuit board comprises a plurality of driving interfaces defined by specifications, and when one or more driving interfaces defined by the specifications are called, the operation instruction corresponding to the one or more driving interfaces defined by the specifications is synchronized to the shared register;
and sending the GPIO state to a second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
2. The GPIO control method of claim 1, wherein the sending the GPIO state to a second circuit board via the protocol resolution service comprises:
and packaging the GPIO state into frames according to a functional module interface protocol through the protocol analysis service, and sending the frames to the second circuit board.
3. The GPIO control method according to claim 1, wherein the first circuit board communicates with the second circuit board via a USB analog serial port.
4. The GPIO control method of claim 1, wherein the GPIO state comprises an output signal state comprising function and data of an output signal.
5. The GPIO control method according to any one of claims 1-4, wherein the first circuit board is a Linux system function board and the second circuit board is a single chip microcomputer function board.
6. A general purpose input output interface, GPIO, control apparatus, the apparatus comprising:
the device comprises a calling module, a sharing register and a switching module, wherein the calling module is used for calling a driving interface of a virtual device node through a protocol analysis service to obtain an operation instruction from the sharing register and converting the operation instruction into a state of a GPIO pin in a first circuit board to obtain a GPIO state, the first circuit board comprises a plurality of driving interfaces defined by specifications, and when one or more driving interfaces defined by the specifications are called, the operation instruction corresponding to the one or more driving interfaces defined by the specifications is synchronized to the sharing register;
and the sending module is used for sending the GPIO state to a second circuit board through the protocol analysis service so that the second circuit board synchronizes the GPIO state to a corresponding GPIO pin in the second circuit board.
7. The GPIO control device as claimed in claim 6, wherein the transmitter module is specifically configured to:
and packaging the GPIO state into frames according to a functional module interface protocol through the protocol analysis service, and sending the frames to the second circuit board.
8. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the GPIO control method according to any one of claims 1 to 5.
9. A circuit board, characterized by comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the GPIO control method as claimed in any one of claims 1-5 when executing the computer program.
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