CN104049704A - Chip power supply regulating system and method - Google Patents
Chip power supply regulating system and method Download PDFInfo
- Publication number
- CN104049704A CN104049704A CN201310077941.0A CN201310077941A CN104049704A CN 104049704 A CN104049704 A CN 104049704A CN 201310077941 A CN201310077941 A CN 201310077941A CN 104049704 A CN104049704 A CN 104049704A
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- Prior art keywords
- chip
- frequency
- microprocessor
- power supply
- communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
Abstract
The invention relates to a chip power supply regulating system which comprises a frequency tracking circuit, a microprocessor and a voltage regulating module, wherein the frequency tracking circuit is used for outputting a trigger signal containing the information of the communication frequency corresponding to a working frequency of a chip when the chip enters into an over-frequency mode; the microprocessor is used for receiving the trigger signal outputted by the frequency tracking circuit; when the trigger signal is received by the microprocessor, the own clock frequency is correspondingly regulated by the microprocessor according to the information of the communication frequency contained in the trigger signal; the communication data transmitted by the chip is analyzed by the microprocessor, so that a corresponding control command is acquired; the microprocessor is also used for outputting the control command; the voltage regulating module comprises a PWM (Pulse Width Modulation) controller; the PWM controller is used for receiving the control command outputted by the microprocessor and outputting a corresponding voltage to the chip according to the control command. The chip power supply regulating system provided by the invention can ensure the smooth communication of the chip working in the over-frequency mode. The invention also provides a chip power supply regulating method.
Description
Technical field
The present invention relates to a kind of chip power supply regulating system and method.
Background technology
Existing CPU(Central Processing Unit, central processing unit) all by a VRM(Voltage Regulator Module, Voltage Regulator Module) operating voltage is provided.As shown in Figure 1, CPU 10 communicates by PMBus (Power Manager Bus, power management bus) and VRM 20, and wherein PMBus is comprised of a clock cable SCL, a data signal line SDA and a cue line ALTER.VRM 20 need be consistent with the communication frequency of CPU 10, if the frequency of operation as CPU 10 is 100 MHz(rated frequencies) time, the communication frequency of CPU 10 is 25MHz, now VRM 20 communication frequencys must be also 25MHz.Yet (as CPU 10 overclocking work) are likely because VRM 20 communication frequencys and the inconsistent CPU of causing 10 of CPU 10 communication frequency cannot communicate with VRM 20 in some situation.As the frequency of operation overclocking as CPU 10, during to 167 MHz, the communication frequency of CPU 10 should be 25*(1+167/100)=41.67 MHz.Now, if VRM 20 communication frequencys or 25 MHz, and then may cause the communication disruption between CPU 10 and VRM 20 or make mistakes.
Summary of the invention
In view of above content, be necessary to provide a kind of guarantee chip overclocking situation still can with chip power supply regulating system and the method for Voltage Regulator Module proper communication.
A chip power supply regulating system, comprising:
One frequency tracking circuit, the trigger pip of the information of the corresponding communication frequency of frequency of operation of this chip while entering overclocking pattern for output packet containing a chip;
One microprocessor, for receiving the trigger pip of this frequency tracking circuit output, when this microprocessor receives this trigger pip, the corresponding clock frequency that regulates self of information of the communication frequency that this microprocessor comprises according to this trigger pip, this microprocessor is also resolved the communication data of this chip transmission, to obtain corresponding steering order, this microprocessor is also for exporting this steering order; And
One Voltage Regulator Module, comprises a PWM controller, the steering order that this PWM controller is exported for receiving this microprocessor, and export corresponding voltage to this chip according to this steering order.
A chip power supply control method, comprises the steps:
Judge whether a chip enters overclocking pattern;
When this chip enters overclocking pattern, transmission package is containing the trigger pip of the information of the communication frequency corresponding with this chip frequency of operation now;
The clock frequency of the corresponding MCU of adjusting of frequency information comprising according to this trigger pip;
Receive the communication data of this chip transmission, and this communication data is resolved, to obtain corresponding steering order;
The PWM controller of steering order to one VRM that transmission acquires; And
According to this instruction, export corresponding pwm signal, think that this chip provides operating voltage.
Said chip power supply regulating system and method are conducive to avoid when this chip enters overclocking pattern, the inconsistent deficiency that causes this chip and this VRM communication disruption of the communication frequency due to this chip and this VRM that may occur.
Accompanying drawing explanation
Fig. 1 is the block scheme of existing CPU electric power system.
Fig. 2 is the block scheme of the first better embodiment of chip power supply regulating system of the present invention.
Fig. 3 is the block scheme of the concrete function of MCU in Fig. 2.
Fig. 4 is the block scheme of the second better embodiment of chip power supply regulating system of the present invention.
Fig. 5 is the process flow diagram of the better embodiment of chip power supply control method of the present invention.
Main element symbol description
| VRM | 30 |
| CPU | 40 |
| Phase-locked loop circuit | 50 |
| MCU | 60 |
| Trigger receiving element | 600 |
| Protocol analysis unit | 602 |
| Control output unit | 604 |
| Frequency adjustment unit | 606 |
| PWM controller | 300 |
Following embodiment further illustrates the present invention in connection with above-mentioned accompanying drawing.
Embodiment
Please refer to Fig. 2, the present invention comprises that for the first better embodiment of chip power supply regulating system a CPU 40, provides VRM 30, a phase-locked loop circuit 50 being connected with this CPU 40 and a MCU(Micro Processor Unit who is all connected with this VRM 30 and this phase-locked loop circuit 50 of operating voltage, microprocessor according to the steering order of these CPU 40 outputs for this CPU 40) 60.In other embodiments, this MCU 60 can have data-handling capacity by other element, equipment or functional module are replaced.
In present embodiment, this CPU 40 communicates by a PMBus bus and this VRM 30, and wherein this PMBus bus comprises clock signal wire SCL, a data signal line SDA and a cue line ALTER for the moment.This MCU 60 is by GPIO(General Purpose Input output, universal input output) signal wire and this VRM 30 carry out data transmission.In other embodiments, this MCU 60 also can communicate by other buses and this VRM 30, as I2C bus.
This VRM 30 comprises a PWM controller 300.The steering order that this VRM 30 transmits for receiving this CPU 40, and control pwm signal corresponding to this PWM controller 300 output, think that this CPU 40 provides corresponding operating voltage.
This phase-locked loop circuit 50 is for following the tracks of the frequency of operation of this CPU 40, with when these CPU 40 overclockings are worked, these phase-locked loop circuit 50 output one trigger pips are to this MCU 60, and wherein this trigger pip comprises the information of this CPU 40 corresponding communication frequency of frequency of operation now.In other embodiments, this phase-locked loop circuit 50 also can have identical function by other frequency-tracking element or module replace.
Please refer to Fig. 3, when this CPU 40 overclocking work, this MCU 60 obtains the communication data between this CPU 40 and this VRM 30, and data are resolved.Particularly, this MCU 60 comprises a triggering receiving element 600, a protocol analysis unit 602, control output unit 604 and a frequency adjustment unit 606.
This triggering receiving element 600 is for receiving the trigger pip of these phase-locked loop circuit 50 outputs.When this triggering receiving element 600 receives the trigger pip of these phase-locked loop circuit 50 outputs, represent that this CPU 40 enters overclocking mode of operation.Now, for avoiding occurring the inconsistent situation of communication frequency of communication frequency and this VRM 40 of this CPU 40, when this triggering receiving element 600 receives this trigger pip, this frequency adjustment unit 606 obtains the communication frequency of this CPU 40 according to the trigger pip that comprises frequency information, and the corresponding clock frequency of adjusting self, with with these CPU 40 overclockings after communication frequency be consistent, and then this MCU 60 after this CPU 40 enters overclocking mode of operation still can be communicated with this CPU 40.If the communication frequency as this CPU 40 is when 25MHz becomes 41.67MHz, the clock frequency that this frequency adjustment unit 606 is also adjusted this MCU 60 is 41.67MHz.Afterwards, this protocol analysis unit 602 receives the communication data between this CPU 40 and this VRM 30 according to the clock frequency after adjusting, and the data message acquiring is resolved, to obtain the information such as instruction that this CPU 30 communicates by letter with this VRM 40, data.
604 of this control output units are corresponding control signal by information codings such as the instruction being obtained by these protocol analysis unit 602 parsings, data, and this control signal are transferred to the PWM controller 300 of this VRM 30 by GPIO signal wire.
This PWM controller 300 is for receiving the control signal of these MCU 60 transmission, and this control signal is resolved, to obtain the information such as corresponding instruction, data, and then export corresponding voltage, so make this PWM controller 300 to communicate with this CPU 40 by this MCU 60.
In other embodiments, this frequency adjustment unit 606 also can export the information of communication frequency corresponding to the frequency of operation of CPU 40 to by GPIO signal wire the PWM controller 300 of this VRM 30, so that this VRM 30 adjusts the communication frequency of self automatically according to the information of the communication frequency receiving, and then make this VRM 30 directly to keep communicating by letter with this CPU 40.
Please refer to Fig. 4, the block scheme of its second better embodiment that is chip power supply regulating system of the present invention.This second better embodiment is compared with the first better embodiment, and 60 of this MCU are integrated in this VRM 30.The function of each element is identical with the function of element corresponding in the first embodiment.
When this triggering receiving element 600 receives the trigger pip of these phase-locked loop circuit 50 outputs, this frequency adjustment unit 606 obtains the communication frequency of this CPU 40 according to the trigger pip that comprises frequency information, and the corresponding clock frequency of adjusting self, with consistent with the communication frequency after these CPU 40 overclockings, and then this MCU 60 after this CPU 40 enters overclocking mode of operation still can be communicated with this CPU 40.Afterwards, this protocol analysis unit 602 receives the communication data of these CPU 40 transmission according to the clock frequency after adjusting, and the communication data acquiring is resolved, to obtain the information such as corresponding instruction, data.
604 of this control output units are corresponding control signal by information codings such as the instruction being obtained by these protocol analysis unit 602 parsings, data, and this control signal is transferred to this PWM controller 300.This PWM controller 300 is for receiving the control signal of these MCU 60 transmission, and this control signal is resolved, to obtain the information such as corresponding instruction, data, and then export corresponding voltage, so make this PWM controller 300 to communicate with this CPU 40 by this MCU 60.
Please refer to Fig. 5, the better embodiment of chip power supply control method of the present invention comprises the steps:
Step S1, this phase-locked loop circuit 50 judges that whether this CPU 40 enters overclocking pattern, when this CPU 40 enters overclocking pattern, enters step S2; When this CPU 40 does not enter overclocking pattern, continue to judge whether this CPU 40 enters overclocking pattern.
Step S2, these phase-locked loop circuit 50 transmission package are containing the trigger pip of the information with this CPU 40 corresponding communication frequency of frequency of operation now.
Step S3, frequency information that this MCU 60 comprises according to this trigger pip is corresponding regulates the clock frequency of this MCU 60 self.
Step S4, this MCU 60 receives the data message of these CPU 40 transmission, and this data message is resolved, to obtain corresponding instruction.
Step S5, the instruction that these MCU 60 transmission acquire is to the PWM controller 300 of this VRM 30.
Step S6, this PWM controller 300 is exported corresponding pwm signal according to this instruction, thinks that this CPU 40 provides operating voltage.
The frequency of operation that said chip power supply regulating system and method are followed the tracks of this CPU 40 by this phase-locked loop circuit 50, to enter overclocking when work at this CPU 40, export corresponding trigger pip, this MCU 60 receives after this trigger pip according to the corresponding clock frequency that regulates self of this trigger pip, and by the instruction of these CPU 40 transmission, the information such as data export this PWM controller 300 to, so that voltage corresponding to this PWM controller 300 output, think this CPU 40 power supplies, so effectively avoided when this CPU 40 enters overclocking pattern, may there is the inconsistent deficiency that causes this CPU 40 and these VRM 30 communication disruption of communication frequency with this VRM 30 due to this CPU 40.
Claims (9)
1. a chip power supply regulating system, comprising:
One frequency tracking circuit, the trigger pip of the information of the corresponding communication frequency of frequency of operation of this chip while entering overclocking pattern for output packet containing a chip;
One microprocessor, for receiving the trigger pip of this frequency tracking circuit output, when this microprocessor receives this trigger pip, the corresponding clock frequency that regulates self of information of the communication frequency that this microprocessor comprises according to this trigger pip, this microprocessor is also resolved the communication data of this chip transmission, to obtain corresponding steering order, this microprocessor is also for exporting this steering order; And
One Voltage Regulator Module, comprises a PWM controller, the steering order that this PWM controller is exported for receiving this microprocessor, and export corresponding voltage to this chip according to this steering order.
2. chip power supply regulating system as claimed in claim 1, is characterized in that: this microprocessor comprises:
One triggers receiving element, for receiving this trigger pip;
One frequency adjustment unit, for the clock frequency of this microprocessor of adjusting corresponding to the information of the communication frequency that comprises according to this trigger pip;
One protocol analysis unit, receives according to the clock frequency after adjusting the communication data that this chip transmits, and also this communication data is resolved, to obtain corresponding steering order; And
One controls output unit, for exporting this steering order to this PWM controller.
3. chip power supply regulating system as claimed in claim 1, it is characterized in that: this microprocessor is this Voltage Regulator Module that controls signal to containing the communication frequency of this chip for transmission package also, this Voltage Regulator Module is according to the corresponding communication frequency that regulates self of the control signal receiving.
4. chip power supply regulating system as claimed in claim 3, is characterized in that: this microprocessor is exported this control signal by a GPIO signal wire.
5. chip power supply regulating system as claimed in claim 1, is characterized in that: this chip is CPU.
6. a chip power supply control method, comprises the steps:
Judge whether a chip enters overclocking pattern;
When this chip enters overclocking pattern, transmission package is containing the trigger pip of the information of the communication frequency corresponding with this chip frequency of operation now;
The clock frequency of the corresponding MCU of adjusting of frequency information comprising according to this trigger pip;
Receive the communication data of this chip transmission, and this communication data is resolved, to obtain corresponding steering order;
The PWM controller of steering order to one VRM that transmission acquires; And
According to this instruction, export corresponding pwm signal, think that this chip provides operating voltage.
7. chip power supply control method as claimed in claim 6, is characterized in that: this trigger pip is exported by a phase-locked loop circuit.
8. chip power supply control method as claimed in claim 6, is characterized in that: this MCU exports this steering order by a GPIO signal wire.
9. chip power supply control method as claimed in claim 6, is characterized in that: this chip is CPU.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310077941.0A CN104049704A (en) | 2013-03-12 | 2013-03-12 | Chip power supply regulating system and method |
| US14/207,415 US20140281596A1 (en) | 2013-03-12 | 2014-03-12 | Frequency adjustment system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310077941.0A CN104049704A (en) | 2013-03-12 | 2013-03-12 | Chip power supply regulating system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104049704A true CN104049704A (en) | 2014-09-17 |
Family
ID=51502694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310077941.0A Pending CN104049704A (en) | 2013-03-12 | 2013-03-12 | Chip power supply regulating system and method |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20140281596A1 (en) |
| CN (1) | CN104049704A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857856A (en) * | 2019-04-22 | 2020-10-30 | 迈普通信技术股份有限公司 | CPU frequency configuration method, chip and system |
| CN114860635A (en) * | 2022-07-07 | 2022-08-05 | 北京智芯半导体科技有限公司 | General input/output interface control method, device, storage medium and circuit board |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI277859B (en) * | 2005-05-13 | 2007-04-01 | Via Tech Inc | Method for adjusting memory frequency |
| JP5173751B2 (en) * | 2008-11-10 | 2013-04-03 | パナソニック株式会社 | Computer system having synchronous / asynchronous control unit |
| JP5568491B2 (en) * | 2011-01-31 | 2014-08-06 | ルネサスエレクトロニクス株式会社 | Multiprocessor device |
| US9043625B2 (en) * | 2012-04-13 | 2015-05-26 | Advanced Micro Devices, Inc. | Processor bridge power management |
| TWI443495B (en) * | 2011-09-08 | 2014-07-01 | Asustek Comp Inc | Computer device and frequency adjusting method for central processing unit |
| KR20130100557A (en) * | 2012-03-02 | 2013-09-11 | 삼성전자주식회사 | Apparatus and method for controlling memory clock frequency in wireless communication system |
-
2013
- 2013-03-12 CN CN201310077941.0A patent/CN104049704A/en active Pending
-
2014
- 2014-03-12 US US14/207,415 patent/US20140281596A1/en not_active Abandoned
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111857856A (en) * | 2019-04-22 | 2020-10-30 | 迈普通信技术股份有限公司 | CPU frequency configuration method, chip and system |
| CN114860635A (en) * | 2022-07-07 | 2022-08-05 | 北京智芯半导体科技有限公司 | General input/output interface control method, device, storage medium and circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| US20140281596A1 (en) | 2014-09-18 |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140917 |