CN102236631A - Calculator system - Google Patents

Calculator system Download PDF

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CN102236631A
CN102236631A CN 201010153053 CN201010153053A CN102236631A CN 102236631 A CN102236631 A CN 102236631A CN 201010153053 CN201010153053 CN 201010153053 CN 201010153053 A CN201010153053 A CN 201010153053A CN 102236631 A CN102236631 A CN 102236631A
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port
data
programmable logic
logic device
complex programmable
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CN 201010153053
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Chinese (zh)
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邓印
邱国书
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英业达股份有限公司
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Abstract

The invention provides a calculator system, comprising: a CPU, a north bridge chip, a BIOS, a plurality of hardware modules, a south bridge chip and a complex programmable logic device. The north bridge chip is coupled to the CPU, and the south bridge chip is electrically connected with the BIOS and the north bridge chip. The south bridge chip comprises a serial signal interface including four universal input/output ports as follows: a clock pulse signal port for providing pulse signals; a data input port for transmitting hardware module state information to the BIOS; a data output port for transmitting control instructions from the BIOS; and a data latching port for starting or closing the data input port and the data output port. The complex programmable logic device is electrically connected with the serial signal interface. With the calculator system, a control function of the south bridge chip for the hardware modules can be expanded by fewer universal input/output ports, and control circuits of the hardware modules can be conveniently increased or reduced and modified through the complex programmable logic device.

Description

一种计算器系统 A computer system

技术领域 FIELD

[0001] 本发明涉及电脑中的计算器系统,尤其涉及计算器系统中与南桥芯片相关的电路设计。 [0001] The present invention relates to a computer in the computer system, and particularly to the circuit design associated with the computer system Southbridge.

背景技术 Background technique

[0002] 对于电脑来说,其上安装的主板,也称为主机板(mainboard)、系统板(systemboard)和母板(motherboard),是电脑中最基本也最为重要的部件之一。 [0002] for a computer, which is mounted on the motherboard, the motherboard is also known as (Mainboard), the system board (systemboard) and the motherboard (Motherboard), is also one of the most important basic computer components. 例如,主板一般为矩形电路板,通常包括基本输入输出系统(Base Input Output System,BIOS)、I/ 0控制芯片、键盘和面板控制开关接口、指示灯接插件、扩充插槽、主板及插卡的直流电源供电接插件等。 For example, the board generally rectangular circuit board, typically include a basic input output system (Base Input Output System, BIOS), I / 0 controller chip, a keyboard and a control switch panel connectors, LEDs, connectors, expansion slots, card board and DC power supply connectors like.

[0003] 具体来说,电脑主板的控制芯片通常成组地使用,一般分为北桥芯片和南桥芯片。 [0003] Specifically, the control computer motherboard chip typically used in groups, are generally divided into Northbridge and Southbridge. 其中,北桥芯片主要决定主板的规格、对硬件的支持、以及系统的性能,提供对CPU的类型和主频、内存的类型和最大容量、ISA/PCI/AGP插槽、ECC纠错等支持;南桥芯片主要决定主板的功能,控制主板上的各种接口(如串口、并口、USB)、PCI总线(接驳电视卡、内部modem、声卡等)、IDE (接硬盘、光驱)以及主板上的其它芯片(如集成声卡、集成RAID卡、 集成网卡等)。 Wherein Northbridge chip board is mainly determined specifications, performance hardware support, and system to provide the type and frequency of the CPU, memory type and maximum capacity, ISA / PCI / AGP slots, ECC error correction support; Southbridge chip board is mainly determined function, controls various interfaces (e.g., serial port, parallel port, the USB) on the motherboard (connected hard drive, CD-ROM) on the motherboard and the PCI bus (connected to TV card, internal modem, sound card, etc.), the IDE other chip (such as integrated sound card, integrated RAID card, integrated network card, etc.).

[0004] 然而,在现有技术中,需要对南桥芯片的通用输入/输出端口逐一地定义各自的控制功能,这样不仅会大量占用接脚资源,还造成了电路板布线时的局限性,因为每个通用输入/输出端口的控制功能在设计电路布线时已经由走线连接唯一地确定,对主板硬件功能的每一次增加或修改都需要重新修改电路设计并重新制作电路板。 [0004] However, in the prior art, it is necessary to Southbridge universal input / output ports individually define the respective control function, which will not only take up a lot of resources pins, causing further limitations when a wiring circuit board, since the control function of each general-purpose input / output port when designing the circuit wiring has been connected is uniquely determined by the traces, each increase or changes need to revise and re-create the circuit design of the circuit board on the motherboard hardware features. 此外,有限的接脚资源使得BIOS芯片与各硬件模块通信时可能顾此失彼。 In addition, the limited resources such pin BIOS chip and communications hardware modules may be at a loss when.

发明内容 SUMMARY

[0005] 针对现有技术中所存在的上述技术缺陷,本发明提供了一种计算器系统,以轻松地扩展南桥芯片的通用输入输出端口数量。 [0005] In view of the above technical defects present in the prior art, the present invention provides a computer system to easily extend Southbridge GPIO port number.

[0006] 依据本发明的一个方面,提供了一种计算器系统。 [0006] According to an aspect of the present invention, there is provided a computer system. 此计算器系统至少包括:一中央处理单元、一北桥芯片、一基本输入输出系统、多个硬件模块、一南桥芯片和一复杂可编程逻辑器件。 This computer system comprises at least: a central processing unit, a north bridge chip, a basic input output system, a plurality of hardware modules, a south bridge chip and a complex programmable logic device. 北桥芯片耦接至中央处理单元。 Northbridge is coupled to the central processing unit. 南桥芯片电性连接基本输入输出系统和北桥芯片,并且南桥芯片具有一串行信号接口,该串行信号接口包括四个通用输入输出端口,分别为:用来提供脉冲信号的时钟脉冲信号端口;用来向基本输入输出系统发送硬件模块状态信息的数据输入端口;用来发送来自基本输入输出系统的控制指令的数据输出端口;以及用来开启或关闭数据输入端口和数据输出端口的数据锁存端口。 South bridge chip electrically connected to the basic input output system and Northbridge and Southbridge chip having a serial signal interface, the serial signal interface comprises four general purpose input and output ports, respectively: means for providing a pulse signal of the clock signal port; data input port used to send status information to the hardware module basic input output system; a data output port for transmitting a control command from the basic input output system; and to enable or disable the data input port and data output port latch port. 复杂可编程逻辑器件电性连接至串行信号接口,并且复杂可编程逻辑器件包括多个输入/输出端口,分别电性连接至多个硬件模块,复杂可编程逻辑器件通过数据输出端口接收基本输入输出系统的控制指令,并传送至多个硬件模块;以及接收来自硬件模块的硬件模块状态信息,并通过数据输入端口传送至基本输入输出系统。 Complex programmable logic device is electrically connected to the serial signal interface, and a complex programmable logic device comprising a plurality of input / output ports, respectively, electrically connected to the plurality of hardware modules, complex programmable logic device through the data output port of the basic input output control command system, and transmitted to the plurality of hardware module; and receiving hardware status information from the module hardware modules, and to the BIOS through the data input port transfer. [0007] 优选地,复杂可编程逻辑器件还具有一缓存单元,用来暂存来自基本输入输出系统的控制指令,以及暂存来自硬件模块的硬件模块状态信息。 [0007] Preferably, the complex programmable logic device further comprises a buffer unit for temporarily storing a control instruction from the Basic Input Output System, and the temporary status information from the hardware module in the hardware module. 在一实施例中,复杂可编程逻辑器件对接收到的硬件模块状态信息进行编码处理,然后暂存于缓存单元中,并通过串行信号接口传送至基本输入输出系统。 In one embodiment, a hardware module status information received complex programmable logic device performs encoding processing, and then temporarily stored in the cache unit, and the interface to the BIOS transmits the serial signal. 在另一实施例中,基本输入输出系统通过串行信号接口发送对硬件模块的控制指令至复杂可编程逻辑器件,此复杂可编程逻辑器件将控制指令暂存于缓存单元中,然后进行解码处理后传送至多个硬件模块。 In another embodiment, the basic input output system via the serial interface to send a signal to the control instructions to the hardware modules complex programmable logic device, a complex programmable logic device this will be temporarily stored in the instruction cache control unit, and the decoding process It is delivered to a plurality of hardware modules.

[0008] 优选地,多个硬件模块可以是CPU供电模块、内存供电模块、风扇供电模块、电源控制模块、板载网卡控制模块和端口侦错模块中的一个或多个。 [0008] Preferably, the plurality of modules may be hardware modules CPU power, memory power supply module, the fan power supply module, the power control module, control module and the onboard NIC port debug one or more modules.

[0009] 优选地,数据锁存端口为一第一电平时,开启数据输入端口和数据输出端口;数据锁存端口为一第二电平时,关闭数据输入端口和数据输出端口。 [0009] Preferably, the data latch port is a first level, and open the data input port data output port; a second data latch port level data input port and close the data output port. 在一实施例中,当数据锁存端口为一第一电平,且脉冲信号为上升沿时,基本输入输出系统通过数据输出端口发送对硬件模块的控制指令至复杂可编程逻辑器件。 In one embodiment, when the port is a data latch first level, and a pulse signal is rising, the basic input output system via the data output port to send commands to the hardware control module to the complex programmable logic device. 在另一实施例中,当数据锁存端口为一第一电平,且脉冲信号为下降沿时,复杂可编程逻辑器件通过数据输入端口发送硬件模块状态信息至基本输入输出系统。 In another embodiment, when the port is a data latch first level, and a pulse signal is falling, complex programmable logic device to the BIOS through the data input port to send the hardware module status information.

[0010] 采用本发明,不仅可以利用较少的通用输入输出端口来扩展南桥芯片对于硬件模块的控制功能,还可以通过复杂可编程逻辑器件便捷地增减和修改硬件模块的控制电路。 [0010] According to the present invention, not only can be extended to the south bridge chip control circuit control the functional hardware modules, and may also be easily increased or decreased by modification of the hardware modules of complex programmable logic devices with less general-purpose input and output ports. 此外,基本输入输出系统可以实时地了解更多硬件模块的状态信息,提高了产品的利用率。 In addition, the basic input output system can understand the real-time status information more hardware modules, to improve the utilization of the product.

附图说明 BRIEF DESCRIPTION

[0011] 读者在参照附图阅读了本发明的具体实施方式以后,将会更清楚地了解本发明的各个方面。 [0011] with reference to the accompanying drawings reader specific embodiments of the present invention later, it will be more clearly understood the various aspects of the present invention. 其中, among them,

[0012] 图1示出本发明的计算器系统的一个示意性实施例的结构框图; A block diagram of an exemplary embodiment [0012] FIG 1 illustrates a computer system according to the present invention;

[0013] 图2示出如图1所示的计算器系统中基本输入输出系统、南桥芯片和复杂可编程逻辑器件之间的数据传输示意图; [0013] Figure 2 illustrates the computer system shown in FIG. 1 the basic input output system, data transmission between the south bridge chip and a complex programmable logic device schematic;

[0014] 图3进一步示出如图2所示的复杂可编程逻辑器件与多个硬件模块之间的电路连接示意图;以及 [0014] Figure 3 further shows a circuit between a complex programmable logic device and a plurality of hardware modules shown in FIG. 2 is a schematic view of the connection; and

[0015] 图4示出根据本发明的计算器系统,从基本输入输出系统向各硬件模块发出控制指令以及将硬件模块的状态信息反馈给基本输入输出系统的时序图。 [0015] FIG. 4 illustrates a computer system according to the present invention, each hardware module control command issued from the basic input output system and the hardware module status information back to the timing chart of the basic input output system.

具体实施方式 Detailed ways

[0016] 下面参照附图,对本发明的具体实施方式进行详细描述。 [0016] Referring to the drawings, specific embodiments of the present invention will be described in detail.

[0017] 图1示出本发明的计算器系统的一个示意性实施例的结构框图。 [0017] FIG 1 illustrates a computer system according to the present invention is a configuration block diagram of a schematic exemplary embodiment. 参照图1,计算器系统至少包括基本输入输出系统100、中央处理单元102、北桥芯片104、南桥芯片106、复杂可编程逻辑器件108和多个硬件模块110。 Referring to FIG. 1, the computer system comprising at least a basic input output system 100, a central processing unit 102, 104 Northbridge, Southbridge 106, a complex programmable logic device 108 and a plurality of hardware modules 110. 其中,北桥芯片104耦接至中央处理单元102。 Wherein the Northbridge 104 is coupled to the central processing unit 102. 南桥芯片106电性连接基本输入输出系统100和北桥芯片104。 South bridge chip 106 is electrically connected to a basic input output system 100 and north bridge chip 104. 而且,南桥芯片106具有一串行信号接口112。 Further, the south bridge chip 106 having a signal serial interface 112. 复杂可编程逻辑器件108通过串行信号接口112电性连接至南桥芯片106。 Complex programmable logic device 108 is connected to Southbridge 106 via the serial signal interface 112 electrically. 此外,复杂可编程逻辑器件108还电性连接多个硬件模块110,从而接收来自基本输入输出系统100的控制指令至多个硬件模块110中对应的硬件模块,以及接收来自多个硬件模块110的硬件模块状态信息并反馈给基本输入输出系统100。 In addition, 108 is also electrically connected to the plurality of complex programmable logic device hardware module 110 to receive the control command from BIOS 100 to the hardware module 110 corresponding to the plurality of hardware modules, hardware and receiving from a plurality of hardware modules 110 module status information and feedback to the basic input output system 100. 本领域的普通技术人员应当理解,计算器系统还可以包括其他的功能芯片,在图1中没有示出的芯片元件并不意味着本发明的计算器系统明确地将这些芯片元件排除在外。 Those skilled in the art will appreciate, the computer system may also include other functions, chip elements are not shown in FIG. 1 does not mean that the computer system of the present invention explicitly exclude these chip components. 恰恰相反,现有技术中计算器系统上的其它芯片元件也可以包含在本发明的计算器系统的内部。 On the contrary, the prior art on the other chip elements may be included in the computer system inside the computer system of the present invention.

[0018] 图2示出如图1所示的计算器系统中基本输入输出系统100、南桥芯片106(串行信号接口11¾和复杂可编程逻辑器件108之间的数据传输示意图。基本输入输出系统100 与南桥芯片106中的串行信号接口112采用双向通信连接,例如,基本输入输出系统100将具体的控制指令通过串行信号接口112的某一通用端口发送至复杂可编程逻辑器件108, 再通过复杂可编程逻辑器件108的输出端口发送至硬件模块,另一方面,多个硬件模块110 的状态信息经由复杂可编程逻辑器件108的输入端口传送至南桥芯片106的串行信号接口112,再通过串行信号接口112反馈至基本输入输出系统100依据本发明的一实施例,南桥芯片106的串行信号接口112包括四个通用输入/输出端口,S卩,图2中的GPIOl接脚、 GPI02接脚、GPI03接脚和GPI04接脚,例如,GPIOl表示时钟脉冲信号端口,提供若干个时钟脉冲信号 [0018] FIG. 2 shows a 100, a south bridge chip 106 (a schematic diagram of data transfer between the computer system 108 shown in Figure 1. Basic Input Output System Interface 11¾ serial signal and complex programmable logic device. Basic Input Output system 100 and the south bridge chip 106 interface to the serial signal in the bidirectional communication link 112, e.g., a basic input output system 100 to a specific control command sent through a universal serial port interface 112 a signal of complex programmable logic device 108 , and then sent to the hardware module via the output port 108 of complex programmable logic devices, on the other hand, the state information of the plurality of hardware modules 110 to the input port transfer complex programmable logic device 108 to the south bridge chip 106 via the serial signal interface 112, then back through the serial interface 112 to signal the BIOS 100 according to an embodiment of the present invention, the serial signal Southbridge 106 general purpose interface 112 includes four input / output ports, S Jie, FIG. 2 GPIOl pin, pin GPIO2, and GPIO3 pin pin GPI04, e.g., clock signals represents GPIOl port, providing a plurality of clock signals ,以将来自复杂可编程逻辑器件108的数据输入至串行信号接口或者将来自基本输入输出系统100对多个硬件模块110的控制指令输出至复杂可编程逻辑器件108 ;GPI02 表示数据输入端口,其数据流向为自复杂可编程逻辑器件108至基本输入输出系统100,用于向基本输入输出系统100发送多个硬件模块110的硬件模块状态信息;GPI03表示数据输出端口,其数据流向为自基本输入输出系统100至复杂可编程逻辑器件108,用于发送来自基本输入输出系统100的控制指令;以及GPI04表示数据锁存端口,用来开启或关闭数据输入端口GPI02和数据输出端口GPI03。例如,当数据锁存端口GPI04处于高电平状态时, 关闭数据输入端口GPI02和数据输出端口GPI03,来自复杂可编程逻辑器件108的硬件模块状态信息或者来自基本输入输出系统100的控制指令均无法相应地在GPI02或者GPI03上传送。当数 , The data from the complex programmable logic device 108 signal input to the serial interface or from the basic input output system 100 outputs complex programmable logic device 108 to the control command 110 of the plurality of hardware modules; GPIO2 represents a data input port, which data flow is from the complex programmable logic device 108 to the system BIOS 100, 100 for transmitting information to a plurality of hardware modules in the state of the hardware module 110 basic input output system; GPIO3 data indicating the output port of the data flow from the base BIOS 100 to 108 complex programmable logic device, configured to send a control instruction from the basic input output system 100; and a data latch GPI04 represents port, to enable or disable data input port and data output port GPI03 GPI02 e.g.,. when the data latched in the high state port GPI04, GPI02 close the data input port and data output port GPIO3, hardware module status information from a complex programmable logic device 108 or the control instruction from the BIOS 100 are not correspondingly GPI02 or transmitted on GPI03. when the number of 锁存端口GPI04从高电平拉低至低电平时,在提供了时钟脉冲信号的前提下, 数据输入端口GPI02和/或数据输出端口GPI03才开始分别接收和/或发送数据。更为具体地,当数据锁存端口GPI04为低电平,且脉冲信号为上升沿时,基本输入输出系统100通过串行信号接口112的数据输出端口GPI03发送对硬件模块的控制指令至复杂可编程逻辑器件108 ;当数据锁存端口GPI04为低电平,且脉冲信号为下降沿时,复杂可编程逻辑器件108通过串行信号接口112的数据输入端口GPI02发送硬件模块状态信息至基本输入输出系统。 When the latch Port GPI04 down from the high level to the low level, is provided under the premise of the clock pulse signal, and data input port GPI02 / or data output port GPI03 started and / or transmitting data are received. More specifically when the data latch GPI04 port is low, and the pulse signal is the rising edge, the basic input output system 100 transmits the serial data output port GPI03 signal interface 112 of the control instructions to the hardware module 108 complex programmable logic device ; GPI04 port when the data latch is low, and the pulse signal falling edge, complex programmable logic device 108 to the BIOS information through the data input port GPI02 serial transmission status signal interface hardware module 112.

[0019] 图3进一步示出如图2所示的复杂可编程逻辑器件108与多个硬件模块110之间的电路连接示意图。 [0019] FIG. 3 shows a further complex programmable logic devices shown in the circuit between the 108 and the hardware module 110 out of the plurality of connection diagram shown in FIG. 当然,复杂可编程逻辑器件108还电性连接串行信号接口112,该串行信号接口112位于南桥芯片106内,如上文所述。 Of course, 108 is also electrically connected to a complex programmable logic device serial signal interface 112, the serial signal interface 112 located within the south bridge chip 106, as described above. 在本发明的一实施例中,复杂可编程逻辑器件108还具有一缓存单元(图中未示出),用于暂存来自基本输入输出系统100的控制指令,以及暂存来自多个硬件模块110的硬件模块状态信息。 In an embodiment of the present invention, a complex programmable logic device 108 also has a buffer unit (not shown), for temporarily storing a control instruction from the BIOS 100, and the register module from the plurality of hardware 110 is a hardware module status information. 更详细来说,复杂可编程逻辑器件108对接收到的硬件模块状态信息进行编码处理后暂存在缓存单元中,并通过串行信号接口112传送至基本输入输出系统100;此外,当基本输入输出系统100通过串行信号接口112发送对硬件模块的控制指令至复杂可编程逻辑器件108时,复杂可编程逻辑器件108将该控制指令暂存于缓存单元中,然后进行解码处理后传送至多个硬件模块110中对应的硬件模块。 After more detail, the hardware state information module docking complex programmable logic device 108 receives the encoding process is temporarily stored in the cache unit, and to BIOS 100 via the serial interface 112 transmits a signal; Further, when a basic input output the system 112 transmits a signal 100 through the serial interface control commands to the hardware module 108 complex programmable logic device, a complex programmable logic device 108 is temporarily stored in the instruction cache control unit and then transmitted to the plurality of hardware decoding process module 110 corresponding to the hardware modules. 在本发明的一实施例中,这里的多个硬件模块110包括,但并不只局限于,CPU供电模块200、内存供电模块202、风扇供电模块204、电源控制模块206、端口侦错模块208和板载网卡控制模块210。 In an embodiment of the present invention, where the plurality of hardware modules 110 include, but are not limited to, the CPU power supply module 200, the memory power supply module 202, the fan power supply module 204, the power control module 206, a port 208, and debug module onboard LAN control module 210.

[0020] 这里,不妨假定一个二进制代码“ 1,,或者“0”用来控制一个硬件模块,并以此作为基础进行简单对比。在现有技术中,南桥芯片106的四个GPIO端口最多只能控制4个硬件模块,因为每个GPIO端口的控制功能均已经通过电路板上的物理走线固定下来;而依据本发明的计算器系统,基于南桥芯片106的串行信号接口112的四个GPIO端口所定义的传输准则,可以控制不止4个硬件模块,因为串行信号接口112的GPIO端口并未直接电性连接至多个硬件模块110,而是与复杂可编程逻辑器件108进行数据传输,因此,也就扩展了基本输入输出系统100对于硬件模块的控制功能。例如,本发明的计算器系统的基本输入输出系统100可以同时用来控制CPU供电模块200、内存供电模块202、风扇供电模块204、电源控制模块206、端口侦错模块208和板载网卡控制模块210,远远多于所占用GPI [0020] Here, a binary code may be assumed "1 ,, or" 0 "is used to control a hardware module, as a basis for a simple comparison. In the prior art, up to four GPIO port Southbridge 106 4 can only control the hardware modules, since each control line GPIO port are physically fixed gone through the circuit board; and a computer system according to the present invention, based on the serial signal interface 106 Southbridge 112 four transmission criteria defined GPIO port can be controlled more than four hardware modules, since the serial signal GPIO port interface 112 is not directly electrically connected to the plurality of hardware modules 110, but the data and complex programmable logic device 108 transmission, therefore, the control function 100 also extends the basic input output system for a hardware module. for example, a basic input output system of the computer system 100 of the present invention can be simultaneously used to control the CPU power supply module 200, memory power module 202, fan the power supply module 204, the power control module 206, a port 208, and debug module onboard LAN control module 210, far more than occupied GPI O端口的数量。 The number of O ports.

[0021] 仍需指出的是,复杂可编程逻辑器件108的I/O端口不仅可以实现输入属性和输出属性之间的切换,设计者还可以任意增加或者修改硬件模块的功能且不必重新设计电路和制作电路板。 [0021] still be noted that the complex programmable logic device I / O port 108 is not only the switching between the input attributes and output attributes may be implemented, the designer can also increase or modify any of the functions and hardware modules without redesigning the circuit and circuit board production.

[0022] 图4示出根据本发明的计算器系统,从基本输入输出系统100向各硬件模块110 发出控制指令以及将硬件模块的状态信息反馈给基本输入输出系统100的时序图。 [0022] FIG. 4 illustrates a computer system according to the present invention, a control command to each hardware module 100 from the basic input output system 110 and the hardware module status information back to the timing chart of the basic input output system 100. 沿用图2中的标识:GPI04为数据锁存端口,GPI03为数据输出端口,GPIOl为时钟脉冲信号端口, GPI02为数据输入端口。 Identified in FIG. 2 follows: GPI04 port is a data latch, GPI03 data output port, GPIOl clock pulse signal port, GPI02 data input port.

[0023] 以基本输入输出系统100向复杂可编程逻辑器件108发送一条控制指令F15AH(十六进制代码),并且接收来自复杂可编程逻辑器件108的一条状态数据DFFlH(十六进制代码)为例。 [0023] In a basic input output system 100 sends a complex programmable logic device 108 a control instruction F15AH (hexadecimal codes) and complex programmable logic device receiving a data state 108 DFFlH (hexadecimal codes) Example. 当GPI04端口从高电平拉低至低电平时,打开数据输入端口GP102和数据输出端口GPI03,基本输入输出系统100在串行信号接口112的GPI03端口通道上加载控制指令F15AH,通过GPIOl端口所提供的时钟脉冲信号,控制指令F15AH依次串行地逐位发送至复杂可编程逻辑器件108,然后通过复杂可编程逻辑器件108将控制指令传送至多个硬件模块110中对应的硬件模块。 When GPI04 port down from the high level to the low level, to open the data input port and data output port GPIO3 GP102, the basic input output system 100 loads in the control instruction F15AH GPIO3 channel serial port interface 112 a signal through port GPIOl clock signal supplied, the control command F15AH sequentially serially transmitted bit by bit to the CPLD 108, and then transmits the control command to a plurality of hardware modules 110 in the corresponding hardware module 108 by a complex programmable logic device. 与此同时,经由数据输入端口GPI02,来自复杂可编程逻辑器件的状态数据DFFlH也依次串行地逐位输入至基本输入输出系统100。 At the same time, via the data input port GPIO2, state data from DFFlH complex programmable logic device also sequentially inputted serially bit by bit to the BIOS 100. 最后,可以选择将数据锁存端口GPI04重新拉至高电平,以完成基本输入输出系统和多个硬件模块之间基于串行信号接口112和复杂可编程逻辑器件108的一次完整的数据交换。 Finally, the data latch select port GPI04 again pulled high to complete the basic input output system between the hardware modules and the plurality of signals based on the serial interface 112 and a complete data exchange complex programmable logic device 108.

[0024] 更为具体地,在时钟脉冲信号端GPIOl连续地提供16个脉冲信号的时间期间,可以将其分为四个子期间,即,第一期间Si、第二期间S2、第三期间S3和第四期间S4。 During the time [0024] More specifically, there is provided a pulse signal 16 is continuously clock signal terminal GPIOl, can be divided into four sub-period, i.e., a first period Si, S2, S3 of the third period of the second period during the fourth and S4. 如果将十六进制代码F15AH转换为二进制代码1111000101011010H,则参照图4,在第一期间S 1, 将四个bit“llll”依次发送至复杂可编程逻辑器件108 ;在第二期间S2,将四个bit“0001” 依次发送至复杂可编程逻辑器件108 ;在第三期间S3,将四个bit “0101”依次发送至复杂可编程逻辑器件108 ;以及在第四期间S4,将四个bit “1010”依次发送至复杂可编程逻辑器件108。 If the hex code is converted to binary code F15AH 1111000101011010H, referring to FIG. 4, S 1, the four bit "llll" sequentially transmitted to the complex programmable logic device 108 in a first period; the second period S2, the four bit "0001" sequence, to complex programmable logic device 108; S3, the four bit "0101" sequence, to complex programmable logic device 108 in the third period; and during a fourth S4, the four bit "1010" in sequence, to complex programmable logic device 108. 至此,在经历了一次完整的数据传送过程后,控制指令F15AH从基本输入输出系统100发送至复杂可编程逻辑器件108。 Thus, after a complete data transfer process, a control instruction transmitted from F15AH BIOS 100 to 108 complex programmable logic device.

[0025] 在本发明的一实施例中,以端口侦错模块208为例,基本输入输出系统100可以先向复杂可编程逻辑器件108发送二进制数据F155,其中Fl为控制指令,当复杂可编程逻辑器件108接收到Fl后,即表示要向端口侦错模块208传送数据,随后将55这条数据信息输出到端口侦错模块208对应的LED上。 [0025] In an embodiment of the present invention, the debug port module 208 to, for example, the basic input output system 100 may send a binary F155 Xianxiang complex programmable logic device 108, wherein Fl is a control command, as a complex programmable after the logic device 108 receives the Fl, i.e., data transfer port 208 denotes to debug module 55 then outputs this data to the port module 208 corresponding to the debug LED.

[0026] 在本发明的另一实施例中,以CPU供电模块200为例,基本输入输出系统100首先向复杂可编程逻辑器件108发送硬件模块状态信息的查询指令F904,复杂可编程逻辑器件108通过16比特长度的返回值告诉基本输入输出系统100,CPU供电模块200当前所处供电状态,比如BITO表示CPUl三相电供应,BITl表示CPUl四相电供应,BIT2表示CPU2三相电供应,BIT3表示CPU2四相电供应,一般系统刚开机时的电源供电均为四相电,然后基本输入输出系统100可以通过读取CPU寄存器得知当前安装CPU的功耗,并计算出该有几相电,假设为三相电,便向复杂可编程逻辑器件108发送供电模块指令F905,将CPU供电模块200的供电状态更改为三相供电,达到节能的效果。 [0026] In another embodiment of the present invention, the CPU power supply module 200 as an example, a basic input hardware module 100 first sends a status inquiry complex programmable logic device 108 F904 instruction information output system, complex programmable logic device 108 return value tells 16-bit length of the BIOS 100, the current status of the CPU in which the power supply module 200, such as three-phase power supply BITO represents CPUl, Bitl represents four-phase power supply CPUl, CPU2 denotes a three-phase power supply BIT2, BIT3 It represents CPU2 four-phase power supply, power supply system when a general four-phase power are just machines, and the BIOS 100 can learn the currently installed power of the CPU by reading the CPU registers, and calculates the phase electric few is assumed to be three-phase power, it would complex programmable logic device 108 sends a power supply module instruction F905, the CPU changes the state of power supply module 200 is a three-phase power, to save energy.

[0027] 在本发明的又一实施例中,以板载网卡控制模块210为例,基本输入输出系统100 根据用户在SETUP里的设定要求来开启或关闭网卡,假设用户需要开启OTCl关闭NIC2,则在开机阶段,基本输入输出系统100向复杂可编程逻辑器件108发送F6FD命令,即可在进入操作系统前将NIC2关闭,并且NIC 1是开启的。 [0027] In a further embodiment of the present invention to onboard LAN control module 210 as an example, the basic input output system 100 to turn on or off the card set according to user requirements in the SETUP assumed that the user needs to turn off NIC2 OTCl , at power-on stage, the basic input output system 100 sends a command to the F6FD complex programmable logic device 108, to the operating system before entering NIC2 closed and NIC 1 is open. 采用本发明的计算器系统,不仅可以利用较少的通用输入输出端口来扩展南桥芯片对于硬件模块的控制功能,还可以通过复杂可编程逻辑器件便捷地增减和修改硬件模块的控制电路。 Using the computer system of the present invention, not only can be extended to the south bridge chip control circuit control the functional hardware modules, and may also be easily increased or decreased by modification of the hardware modules of complex programmable logic devices with less general-purpose input and output ports. 此外,基本输入输出系统可以实时地了解更多硬件模块的状态信息,提高了产品的利用率和运行效率。 In addition, the basic input output system can understand the real-time status information more hardware modules, improving the utilization and operational efficiency of the product. 上文中,参照附图描述了本发明的具体实施方式。 Hereinabove, the drawings described specific embodiments of the present invention are shown. 但是,本领域中的普通技术人员能够理解,在不偏离本发明的精神和范围的情况下,还可以对本发明的具体实施方式作各种变更和替换。 However, those skilled in the art will appreciate, without departing from the spirit and scope of the present invention, and various modifications may be made to the alternative embodiment of the present invention. 这些变更和替换都落在本发明权利要求书所限定的范围内。 These modifications and variations fall within the claims of the present invention as defined by the scope of the claims.

Claims (8)

  1. 1. 一种计算器系统,其特征在于,所述计算器系统至少包括: 一中央处理单元;一北桥芯片,耦接所述中央处理单元; 一基本输入输出系统; 多个硬件模块;一南桥芯片,电性连接所述基本输入输出系统与所述北桥芯片,所述南桥芯片具有一串行信号接口,所述串行信号接口包括四个通用输入/输出端口,分别为: 一时钟脉冲信号端口,提供脉冲信号;一数据输入端口,用于向所述基本输入输出系统发送硬件模块状态信息; 一数据输出端口,用于发送来自所述基本输入输出系统的控制指令;以及一数据锁存端口,用于开启或关闭所述数据输入端口和所述数据输出端口;以及一复杂可编程逻辑器件,电性连接至所述串行信号接口,所述复杂可编程逻辑器件包括多个输入/输出端口,分别电性连接所述硬件模块,所述复杂可编程逻辑器件通过所述数据 1. A computer system, wherein, said computer system comprising at least: a central processing unit; a north bridge chip, coupled to the central processing unit; a basic input output system; a plurality of hardware modules; a South bridge chip electrically connected to said basic input output system and the north bridge chip, a south bridge chip having an interface to a serial signal, said serial signal interface includes four general purpose input / output ports, respectively: a clock pulse signal port, providing a pulse signal; a data input port, a basic input output system to the hardware module transmitting state information; a data output port for transmitting the control commands from the basic input output system; and a data a latch port for opening or closing the input port and the data output port of the data; and a complex programmable logic device, electrically connected to said serial signal interface, a complex programmable logic device comprising a plurality of input / output ports, respectively, electrically connected to the hardware module, the complex programmable logic device through the data 输出端口接收所述基本输入输出系统的所述控制指令,并传送至所述硬件模块;所述复杂可编程逻辑器件接收来自所述硬件模块的所述硬件模块状态信息,并通过所述数据输入端口传送至所述基本输入输出系统。 The output port of the basic input output system receives the control command, and transmits to the hardware module; a complex programmable logic device receiving the status information of the hardware module from the hardware module, and the data input via transmitting port to said basic input output system.
  2. 2.如权利要求1所述的计算器系统,其特征在于,所述复杂可编程逻辑器件还具有一缓存单元,用于暂存来自所述基本输入输出系统的所述控制指令,以及来自所述硬件模块的所述硬件模块状态信息。 2. A computer system according to claim 1, wherein said complex programmable logic device further comprises a buffer unit for temporarily storing the control instruction from the basic input output system, and from the the hardware module status information said hardware module.
  3. 3.如权利要求2所述的计算器系统,其特征在于,所述复杂可编程逻辑器件对接收到的所述硬件模块状态信息进行编码处理后暂存在所述缓存单元中,并通过所述串行信号接口传送至所述基本输入输出系统。 3. A computer system according to claim 2, wherein said hardware module status information of the received complex programmable logic device after the encoding process is temporarily stored in the cache unit, and by the transmitting the serial signal interface to the BIOS.
  4. 4.如权利要求2所述的计算器系统,其特征在于,所述基本输入输出系统通过所述串行信号接口发送对所述硬件模块的控制指令至所述复杂可编程逻辑器件,所述复杂可编程逻辑器件将所述控制指令暂存在所述缓存单元中,然后进行解码处理后传送至所述硬件模块。 4. A computer system according to claim 2, wherein the basic input output system via the serial interface to send a signal to the control instructions to the hardware module complex programmable logic device, said complex programmable logic device to the control instruction temporarily stored in the cache unit, and then transferred to the hardware module after the decoding process.
  5. 5.如权利要求1所述的计算器系统,其特征在于,所述硬件模块是CPU供电模块、内存供电模块、风扇供电模块、电源控制模块、板载网卡控制模块和端口侦错模块中的一个或者多个。 5. A computer system according to claim 1, wherein said hardware module is a power supply module CPU, the memory module power supply, the fan power supply module, the power control module, control module and the onboard NIC port debug module one or more.
  6. 6.如权利要求1所述的计算器系统,其特征在于,所述数据锁存端口为一第一电平时, 开启所述数据输入端口和所述数据输出端口,所述数据锁存端口为一第二电平时,关闭所述数据输入端口和所述数据输出端口。 6. A computer system according to claim 1, wherein said data latch port is a first level, turning on the data input port and the data output port, said data port is latched a second level, said data input port and closing said output data port.
  7. 7.如权利要求6所述的计算器系统,其特征在于,当所述数据锁存端口为所述第一电平,且所述脉冲信号为上升沿时,所述基本输入输出系统通过所述数据输出端口发送对所述硬件模块的控制指令至所述复杂可编程逻辑器件。 7. A computer system according to claim 6, wherein, when said data port is latched to the first level, the pulse signal and a rising edge, the basic input output system through the said data output port to send commands to the hardware control module to the complex programmable logic device.
  8. 8.如权利要求6所述的计算器系统,其特征在于,当所述数据锁存端口为所述第一电平,且所述脉冲信号为下降沿时,所述复杂可编程逻辑器件通过所述数据输入端口发送所述硬件模块状态信息至所述基本输入输出系统。 8. The computer system according to claim 6, wherein, when said data port is latched to the first level and the pulse signal falling edge, a complex programmable logic device by the data input port transmitting said hardware module status information to the BIOS.
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