CN110825204A - Mainboard of electronic equipment and power supply information management method - Google Patents
Mainboard of electronic equipment and power supply information management method Download PDFInfo
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- CN110825204A CN110825204A CN201911078694.XA CN201911078694A CN110825204A CN 110825204 A CN110825204 A CN 110825204A CN 201911078694 A CN201911078694 A CN 201911078694A CN 110825204 A CN110825204 A CN 110825204A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
Abstract
The invention discloses a mainboard of electronic equipment, which comprises a baseboard management controller; a south bridge chip; the CPLD programmable logic device is provided with a first interface, the first interface is used for being connected with a power supply module of the electronic equipment so as to read the register information of the power supply module, and the CPLD programmable logic device is connected with a south bridge chip and the substrate management controller through a second interface so as to send the read register information to the south bridge chip and the substrate management controller through the second interface. The invention also discloses a power supply information management method, which achieves the effect of delaying the service life of the mainboard of the electronic equipment.
Description
Technical Field
The invention relates to the technical field of electronic appliances, in particular to a mainboard of electronic equipment and a power supply information management method.
Background
Electric energy is the main energy and power for modern industrial production. It is easily converted from other forms of energy, and therefore, the application of electric energy in modern industry and people's life is extremely wide. But in the technical field of electronic appliances, the energy source is rather used as an irreplaceable energy source. For example, electronic products such as computers and servers use electric energy as driving energy when running.
In a conventional server, a PSU (Power supply) generally transmits various operation information of the PSU to a BMC (Baseboard management Controller) and a PCH (south bridge) chip through a PMBUS (Power management bus). This results in a very large number of connection information between the PSU and the motherboard, which is typically physically connected by gold fingers. Therefore, when the number of the connections between the PSUs and the main board is too large, misoperation is easy to occur, and the service life of the main board is shortened.
Disclosure of Invention
The main objective of the present invention is to provide a motherboard of an electronic device and a power information management method, which are used to achieve the effect of prolonging the service life of the motherboard of the electronic device.
In order to achieve the above object, the present invention provides a motherboard of an electronic device, the motherboard of the electronic device comprising:
a baseboard management controller;
a south bridge chip;
the CPLD programmable logic device is provided with a first interface, the first interface is used for being connected with a power supply module of the electronic equipment so as to read the register information of the power supply module, and the CPLD programmable logic device is connected with a south bridge chip and the substrate management controller through a second interface so as to send the read register information to the south bridge chip and the substrate manager through the second interface.
Optionally, the motherboard of the electronic device further includes a power connector connected to the first interface, and the CPLD is connected to the power module through the power connector.
Optionally, the CPLD reads sideband information of the power module through the first interface, and further includes a third interface, and the CPLD sends the sideband information to the baseboard management controller through the third interface.
Optionally, the third interface is electrically connected to the baseboard manager.
Optionally, the first interface is in communication connection with the voltage module through a power management bus, and the second interface is in communication connection with the south bridge chip and the baseboard management controller through a bus.
Optionally, the bus is provided as an I2C bus.
In addition, the present invention also provides a power information management method, which is applied to the motherboard of the electronic device, and the power information management method includes the following steps:
reading register information and sideband information of the power supply module by the CPLD;
outputting the read sideband information through a fourth interface, and storing the register information;
when a register information query instruction sent by a baseboard management controller and/or a south bridge chip is received, reading the stored register information;
and sending the register information to the south bridge chip and/or the baseboard management controller through a second interface.
Optionally, the power information management method further includes:
the CPLD receives a power supply firmware upgrade package sent by the baseboard management controller;
and sending the power firmware upgrading package to the power supply module, wherein the power supply module upgrades the power firmware according to the power firmware upgrading package when receiving the power firmware upgrading package.
Optionally, the step of outputting the read sideband information through a fourth interface and storing the sideband information includes:
and when the register information and the sideband information are read, adjusting the output level value of the pin corresponding to the third interface according to the sideband information, and storing the register information in the CPLD.
The invention provides a mainboard of electronic equipment and a power supply information management method, wherein the mainboard of the electronic equipment comprises the following components: a baseboard management controller; a south bridge chip; the CPLD programmable logic device is provided with a first interface, the first interface is used for being connected with a power module of the electronic equipment to read the register information of the power module, the CPLD programmable logic device is connected with a south bridge chip and the substrate management controller through a second interface to send the read register information to the south bridge chip and the substrate manager through the second interface, so that the purpose of power management can be achieved by only arranging one interface between the CPLD and the power module on the mainboard, the number of connections between the mainboard module and the power supply is reduced, the probability of misoperation in the process of plugging the power module to the mainboard can be effectively reduced, and the effect of delaying the service life of the mainboard is achieved.
Drawings
Fig. 1 is a schematic view of a connection structure between a main board and a power module of an electronic device according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a power information management method according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of another embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As an implementation manner, the present invention provides a motherboard of an electronic device, where the motherboard of the electronic device includes a CPLD programmable logic device, a board management controller, and a south bridge chip; the CPLD is arranged to be connected with a power supply module and read the register information of the power supply module; the CPLD is also respectively connected with the substrate management controller and the south bridge chip and is set to send the memory information of the parasitic power module read by the CPLD to the substrate management controller and the south bridge chip.
Specifically, as shown in fig. 1, the main board 10 of the electronic Device includes a CPLD (Complex programmable logic Device) 11, a BMC (Baseboard Management Controller) 12, and a PCH (south bridge) chip 13; the CPLD11 is configured to be connected to a PSU MODULE (power supply MODULE) 20 through a first interface, and read register information of the power supply MODULE 20; the CPLD11 is also connected to the south bridge chip 13 and the baseboard management controller 12 through a second interface. The CPLD11 is configured to send the register information of the power module 20 read by the CPLD11 to the baseboard management controller 12 and the south bridge chip 13.
Optionally, the main board of the electronic device further includes a power connector 14, and the power connector 14 is disposed between the CPLD11 and the power module 20. That is, the first interface of the CPLD is connected to one end of the power connector 14, and the other end of the power connector 14 is connected to the power module 20, so that the CPLD11 can be connected to the power module 20 through the power connector 14. The CPLD11 and the power supply connector 14, and the power supply connector 14 and the power supply module 20 are connected through a power supply management bus.
As an implementation manner, the power connector 14 includes an insulating body and a plurality of terminals, the insulating body has a plurality of receiving slots, the receiving slots receive the terminals, the insulating body is further provided with at least one tongue piece, the tongue piece isolates the terminals, the terminals respectively have an barb, the terminals respectively extend outwards on first sides of the barbs to form a plurality of contacting portions, and second sides of the barbs fix a plurality of wires; through the structure, the barb of the terminal can be embedded into the insulating body, the terminal is easy to assemble, and the terminal can be pushed into the insulating body only, so that short circuit and other effects between the terminals cannot occur.
Due to the arrangement of the power connector, the power module 20 and the CPLD11 can be plugged, so that the connection step between the power module 20 and the CPLD is simplified.
Further, the CPLD11 and the Power module are connected by a PMbus (Power Management Bus), wherein the PMbus is an open standard digital Power Management protocol. Communication with a power module or other device may be facilitated by defining transport and physical interfaces and command languages. Since the CPLD11 can be programmed and the CPLD11 and the power module 20 are connected through the PMbus, the CPLD11 can read the register information and the Sideband information (Sideband signals) in the power module 20 based on the PMbus when executing a program.
Further, the CPLD11 may store the register information after reading the register information of the power module 20. Since the CPLD11 and the baseboard management controller 12 and the south bridge chip 13 are connected by a bus, the baseboard management controller 12 and the south bridge chip 13 can poll the CLDL 11 for register information that has saved the power module 20. Because the CPLD11 is connected to the baseboard management controller 12 and the south bridge chip 13 through the bus, the baseboard management controller 12 and the south bridge chip 13 can simultaneously issue data requests to the CPLD11, thereby implementing parallel processing of data, improving the processing efficiency of data, and reducing the zero delay of state change.
Specifically, the third interface of the CPLD11 is directly connected to the baseboard management controller 12, and is configured to send the sideband information to the baseboard management controller 12; the second interface of the CPLD11 is connected to the south bridge chip 13 through a bus, and is configured to send the register information to the south bridge chip 13, and the second interface of the CPLD11 is further connected to the baseboard management controller 12 through the two buses, and is configured to send the register information to the baseboard management controller 12; as one implementation, the bus may be an I2C bus.
It should be noted that the sideband signal is low-speed information and is embodied by a high level and a low level, so that the sideband information number output pin corresponding to the third interface of the CPLD11 may be directly electrically connected to the sideband information number input pin of the baseboard management controller 12, so that the baseboard management controller 12 may read a level value on the sideband information number output pin corresponding to the fourth interface of the CPLD11 and determine the sideband information according to the level value.
It should be noted that, after the CPLD11 reads the sideband signal of the power module 20, the level value on the sideband information number output pin corresponding to the third interface can be adjusted in real time according to the sideband information number, so as to achieve the purpose of outputting the sideband information in real time.
In the motherboard of the electronic device disclosed in this embodiment, the CPLD may be used as a transfer station for module information of the power module, and is configured to read register information and sideband information of the power module. The register information is sent to the baseboard management controller and/or the south bridge chip, and the sideband information is sent to the baseboard management controller, so that the purpose of power management can be achieved by only arranging an interface between the CPLD and the power supply module on the mainboard, the connection quantity between the mainboard module and the power supply is reduced, the probability of misoperation in the process of plugging the power supply module to the mainboard can be effectively reduced, and the effect of delaying the service life of the mainboard is achieved.
In a conventional server, the PSU (Power supply) generally transmits various operation information of the PSU to a BMC (Baseboard management Controller) and a PCH (south bridge) chip through a PMBUS (Power management Bus). This results in a very large number of connection information between the PSU and the motherboard, which is typically physically connected by gold fingers. Therefore, when the number of the connections between the PSUs and the main board is too large, misoperation is easy to occur, and the service life of the main board is shortened.
In order to solve the above defect, an embodiment of the present invention further provides a power information management method based on the motherboard of the electronic device, where the power information management method mainly includes the following steps:
reading register information and sideband information of the power supply module by the CPLD;
outputting the read sideband information through a third interface, and storing the register information;
when a register information query instruction sent by a baseboard management controller and/or a south bridge chip is received, reading the stored register information;
and sending the register information to the south bridge chip and/or the baseboard management controller through a second interface.
Further, based on the motherboard of the electronic device, the CPLD further performs the following steps:
the CPLD receives a power supply firmware upgrade package sent by the baseboard management controller;
and sending the power firmware upgrading package to the power supply module, wherein the power supply module upgrades the power firmware according to the power firmware upgrading package when receiving the power firmware upgrading package.
Further, based on the motherboard of the electronic device, the CPLD further performs the following steps:
and when the register information and the sideband information are read, adjusting the output level value of the pin corresponding to the third interface according to the sideband information, and storing the register information in the CPLD.
Referring to fig. 2, in an embodiment of the power information management method of the present invention, the power information management method includes the following steps:
step S10, reading the register information and the sideband information of the power module by the CPLD;
step S20, outputting the read sideband information through the three interfaces, and storing the register information;
step S30, when a register information query instruction sent by the baseboard management controller and/or the south bridge chip is received, the saved register information is read;
and step S40, sending the register information to the south bridge chip and/or the baseboard management controller through a second interface.
In this embodiment, the CPLD and the power module are connected by a power management bus, so that the CPLD can read the module information of the power module based on the voltage management bus protocol. The module information may include register information and sideband information.
For example, the register information may be temperature information detected by a temperature detection sensor of the power module, AC Loss (AC Loss), and the like, and the sideband information may be PSU present (power supply present) and the like.
Specifically, a Power Supply (PSU) directly transmits register information and sideband information of the PSU to a CPLD through a power management bus signal, wherein the CPLD can be used as a host in a power management bus protocol during transmission to continuously read and write the register information and sideband information transmitted by the PSU. And when the register information is read, storing the register information into the CPLD, and when the sideband information is read, adjusting the level value of the pin corresponding to the third interface in real time according to the sideband information. And the pin corresponding to the third interface is directly connected with the baseboard management controller, so that the baseboard management controller can directly read the level value on the pin corresponding to the third interface. Since the sideband information is a low-speed information number, it can be represented by high and low levels. Therefore, the baseboard management controller can determine the sideband information of the power supply module according to the read level value.
It should be noted that the CPLD may be programmed in advance, and different level values may be designed to characterize sideband information according to different requirements of different electronic devices and specific content of the sideband signal.
Further, after receiving the polling instruction sent by the baseboard management controller and/or the south bridge chip, that is, when receiving the register information query instruction sent by the baseboard management controller and/or the south bridge chip, the CPLD may obtain the register information of the power module stored therein according to the polling instruction, and send the register information to the baseboard management controller and/or the south bridge chip through the bus.
In the technical scheme disclosed in this embodiment, the CPLD reads the register information and the sideband information of the power supply module, then outputs the read sideband information through the third interface, stores the register information, and reads the stored register information when receiving a register information query instruction sent by the baseboard management controller and/or the south bridge chip, and the second interface sends the register information to the baseboard management controller and/or sends the register information to the south bridge chip through the second interface. The CPLD can be used as a transfer station of the module information of the power module, so that the purpose of power management can be achieved only by arranging an interface between the CPLD and the power module on the mainboard, the connection quantity between the mainboard module and the power supply is reduced, the probability of misoperation in the process of plugging the power module to the mainboard can be effectively reduced, and the effect of delaying the service life of the mainboard is achieved.
Referring to fig. 3, based on the foregoing embodiment, in another embodiment, the power information management method further includes:
step S50, the CPLD receives a power firmware upgrade package sent by the baseboard management controller;
and step S60, sending the power firmware upgrade package to the power supply module, wherein the power supply module upgrades the power supply firmware according to the power supply firmware upgrade package when receiving the power supply firmware upgrade package.
In this embodiment, the baseboard management controller can be connected to the second interface of the CPLD via the I2C bus. Therefore, the baseboard management controller can upgrade the firmware of the power module online through I2C. In the upgrading process, the CPLD can be used as a slave in an I2C transmission protocol, receives a power supply firmware upgrading packet sent by the substrate management controller, and forwards the power supply firmware upgrading packet to the power supply module. So that the power module can perform firmware upgrade based on the upgrade package.
It should be noted that fig. 3 is not intended to limit the step S50 to be executed after the step S40, and the step execution sequence shown in fig. 3 is only the step execution sequence in one embodiment of the present invention.
In the technical solution disclosed in this embodiment, the CPLD receives a power firmware upgrade package sent by the baseboard management controller, and sends the power firmware upgrade package to the power module, where the power module upgrades the power firmware according to the power firmware upgrade package when receiving the power firmware upgrade package, so as to achieve an effect of upgrading the power module firmware on line.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above and includes several instructions for enabling a terminal device (e.g. a motherboard of an electronic device, etc.) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention in the specification and drawings, or applied to other related technical fields, are also included in the scope of the present invention.
Claims (9)
1. A motherboard of an electronic device, the motherboard comprising:
a baseboard management controller;
a south bridge chip;
the CPLD programmable logic device is provided with a first interface, the first interface is used for being connected with a power supply module of the electronic equipment so as to read the register information of the power supply module, and the CPLD programmable logic device is connected with a south bridge chip and the substrate management controller through a second interface so as to send the read register information to the south bridge chip and the substrate management controller through the second interface.
2. The motherboard of an electronic device as recited in claim 1, further comprising a power connector connected to said first interface, wherein said CPLD is connected to said power module via said power connector.
3. The motherboard of an electronic device as recited in claim 1 wherein said CPLD reads sideband information of said power module through said first interface, said CPLD further comprising a third interface, said CPLD sending said sideband information to said baseboard management controller through said third interface.
4. The motherboard of claim 1, wherein the third interface is electrically connected to the baseboard manager.
5. The motherboard of claim 1, wherein the first interface is communicatively coupled to the voltage module via a power management bus, and the second interface is communicatively coupled to the south bridge chip and the baseboard management controller via a bus.
6. A motherboard for an electronic device as recited in claim 5, wherein said bus is configured as an I2C bus.
7. A power information management method applied to a main board of an electronic device according to any one of claims 1 to 6, the power information management method comprising the steps of:
reading register information and sideband information of the power supply module by the CPLD;
outputting the read sideband information through a fourth interface, and storing the register information;
when a register information query instruction sent by a baseboard management controller and/or a south bridge chip is received, reading the stored register information;
and sending the register information to the south bridge chip and/or the baseboard management controller through a second interface.
8. The power information management method according to claim 7, wherein the power information management method further comprises:
the CPLD receives a power supply firmware upgrade package sent by the baseboard management controller;
and sending the power firmware upgrading package to the power supply module, wherein the power supply module upgrades the power firmware according to the power firmware upgrading package when receiving the power firmware upgrading package.
9. The power information management method according to claim 7, wherein the step of outputting the read sideband information through a fourth interface and saving the sideband information comprises:
and when the register information and the sideband information are read, adjusting the output level value of the pin corresponding to the third interface according to the sideband information, and storing the register information in the CPLD.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111580887A (en) * | 2020-05-13 | 2020-08-25 | 浪潮商用机器有限公司 | Method, device, equipment and storage medium for acquiring PSU asset information |
| CN112737836A (en) * | 2020-12-26 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Bandwidth allocation method, device and equipment for PCIe external plug-in card and storage medium |
| CN113127302A (en) * | 2021-04-16 | 2021-07-16 | 山东英信计算机技术有限公司 | Method and device for monitoring GPIO (general purpose input/output) of board card |
| CN115102937A (en) * | 2022-06-24 | 2022-09-23 | 苏州浪潮智能科技有限公司 | Server power source self-adaptive communication method, equipment and medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101739319A (en) * | 2008-11-27 | 2010-06-16 | 英业达股份有限公司 | Computer device |
| CN101866304A (en) * | 2010-02-24 | 2010-10-20 | 英业达股份有限公司 | Server capable of detecting state of voltage regulator |
| CN104794033A (en) * | 2015-04-29 | 2015-07-22 | 浪潮电子信息产业股份有限公司 | CPU low-frequency fault positioning method and device based on BMC |
| CN105183509A (en) * | 2015-08-27 | 2015-12-23 | 浪潮集团有限公司 | Apparatus and method for realizing shutdown of system power after soft-off |
| CN109409107A (en) * | 2018-10-09 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of data guard method, system and computer readable storage medium |
-
2019
- 2019-11-06 CN CN201911078694.XA patent/CN110825204A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101739319A (en) * | 2008-11-27 | 2010-06-16 | 英业达股份有限公司 | Computer device |
| CN101866304A (en) * | 2010-02-24 | 2010-10-20 | 英业达股份有限公司 | Server capable of detecting state of voltage regulator |
| CN104794033A (en) * | 2015-04-29 | 2015-07-22 | 浪潮电子信息产业股份有限公司 | CPU low-frequency fault positioning method and device based on BMC |
| CN105183509A (en) * | 2015-08-27 | 2015-12-23 | 浪潮集团有限公司 | Apparatus and method for realizing shutdown of system power after soft-off |
| CN109409107A (en) * | 2018-10-09 | 2019-03-01 | 郑州云海信息技术有限公司 | A kind of data guard method, system and computer readable storage medium |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111580887A (en) * | 2020-05-13 | 2020-08-25 | 浪潮商用机器有限公司 | Method, device, equipment and storage medium for acquiring PSU asset information |
| CN111580887B (en) * | 2020-05-13 | 2023-08-15 | 浪潮商用机器有限公司 | Method, device, equipment and storage medium for acquiring PSU asset information |
| CN112737836A (en) * | 2020-12-26 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Bandwidth allocation method, device and equipment for PCIe external plug-in card and storage medium |
| CN113127302A (en) * | 2021-04-16 | 2021-07-16 | 山东英信计算机技术有限公司 | Method and device for monitoring GPIO (general purpose input/output) of board card |
| CN115102937A (en) * | 2022-06-24 | 2022-09-23 | 苏州浪潮智能科技有限公司 | Server power source self-adaptive communication method, equipment and medium |
| CN115102937B (en) * | 2022-06-24 | 2023-06-16 | 苏州浪潮智能科技有限公司 | Self-adaptive communication method, device and medium for server power supply |
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Address after: 518000 501-2, building a, wisdom Plaza, 4068 Qiaoxiang Road, Gaofa community, Shahe street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Shenzhen baoxinchuang Technology Co.,Ltd. Address before: 518000 floor 6, workshop 7, Tongfu industrial city, No. 351, tangxing Road, Tanglang community, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Applicant before: Shenzhen Baolong Daxin Technology Co.,Ltd. |
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Application publication date: 20200221 |
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