TWI391825B - Processing module, operation system and processing method utilizing the same - Google Patents

Description

Processing module, operating system and processing method

The present invention relates to a processing module, and more particularly to a processing module having a graphics processing unit (GPU).

In current products, a graphics processing unit (GPU) is used for data transmission with a memory unit. The memory unit has an operating frequency of the graphics processor. Therefore, the graphics processor can operate according to the operating frequency stored by the memory unit.

In order to achieve higher performance of the graphics processor, the user may increase the operating frequency stored in the memory unit, that is, overclocking. However, once the overclocking fails, it is very likely that the graphics processor will not function properly.

The present invention provides a processing module including a graphics processing unit (GPU), a first memory unit, a second memory unit, and a control unit. The graphics processor has a register. When the first memory unit is enabled, data transfer can be performed with the graphics processor. When the second memory unit is enabled, data transfer can be performed with the graphics processor. The control unit first enables the first memory unit. The control unit enables the second memory unit when the first memory unit is unable to perform data transfer with the graphics processor.

The invention further provides an operating system comprising a system basic output input system (System BIOS), a graphics processing unit (GPU), a first memory unit, a second memory unit and a control unit. The system basic output input system performs a setting action. The graphics processor has a register. When the first memory unit is enabled, data transfer can be performed with the graphics processor. When the second memory unit is enabled, data transfer can be performed with the graphics processor. The control unit first enables the first memory unit. The control unit enables the second memory unit when the first memory unit is unable to perform data transfer with the graphics processor.

The present invention further provides a processing method, including enabling a first memory unit for data transmission with a graphics processor; determining whether data transmission between the graphics processor and the first memory unit is normal; and when When the graphics processor is unable to perform data transmission with the first memory unit, a second memory unit is enabled to enable the graphics processor to perform data transmission with the second memory unit.

In order to make the features and advantages of the present invention more comprehensible, the preferred embodiments are described below, and are described in detail with reference to the accompanying drawings.

Figure 1 is a schematic illustration of one of the operating systems of the present invention. As shown, the operating system 100 includes a processing module 120 and a system basic input/output system (SBIOS) 130. The invention does not limit the type of operating system 100. In this embodiment, the operating system 100 is a motherboard (MB) 110.

The SBIOS 130 performs a setting action. The SBIOS 130 is stored in a memory, and the set operation is performed as a function of communication between the hardware and the operating system. The operating mode of the system can be set via the SBIOS 130. Since the operation principle of the SBIOS and the setting actions performed by the SBIOS are well known to those skilled in the art, they will not be described again.

In this embodiment, the processing module 120 includes a graphics processing unit (GPU) 121, memory units 122, 123, and a control unit 124. The graphics processor 121 has a register 125. When the memory unit 122 is enabled, the graphics processor 121 can perform data transfer with the memory unit 122. Therefore, the register 125 can store the data from the memory unit 122.

Similarly, when the memory unit 123 is enabled, the graphics processor 121 can perform data transfer with the memory unit 123. At this time, the register 125 stores the material from the memory unit 123. In this embodiment, the memory cells 122 and 123 are not enabled at the same time.

In addition, the graphics processor 121 transmits data to the memory unit 122 or 123 through the transmission bus 126. The invention does not limit the type of transmission bus 126. In one possible embodiment, the transmission bus 126 is an internal integrated circuit (I-squared-C; I ² C) bus.

In a possible embodiment, the register 125 stores the device ID of the graphics processor 121, that is, the identifier of the storage graphics processor 121. In another possible embodiment, the register 125 stores a flag. By reading the flag, it is possible to know which memory unit the drawing processor 121 is performing data transmission with.

For example, when the flag stored in the register 125 is 0, it indicates that the drawing processor 121 performs data transmission with the memory unit 122. When the flag stored in the register 125 is 1, it indicates that the drawing processor 121 performs data transmission with the memory unit 123. In the present embodiment, regardless of whether the register 125 stores the device tag of the graphics processor 121 or stores the flags representing the memory units 122 and 123, the stored contents are provided by the memory units 122 and 123.

In this embodiment, the enabling or disabling of the memory units 122 and 123 is determined by the control unit 124. The control unit 124 activates the memory unit 122 according to a preset setting, wherein the preset setting can be set by the user through a jumper, or the operating system 100 is preset before being shipped from the factory.

For convenience of description, in the embodiments described below, the memory unit 122 is used as the default memory, and the memory unit 123 is the backup memory.

After the memory unit 122 is enabled, the graphics processor 121 can perform data transfer with the memory unit 122. In a possible embodiment, the memory unit 122 stores a device tag or a flag in the register 125, wherein the device tag is an identifier of the graphics processor 121, and the flag is the memory unit 122. Identifier.

When the memory unit 122 cannot perform data transmission with the graphics processor 121, the temporary memory 125 may not be able to continue to temporarily store the identification code of the graphics processor 121 or the identification code of the memory unit 122. Therefore, the control unit 124 enables the memory unit 123 to cause the drawing processor 121 to perform data transfer with the memory unit 123.

Since the memory unit 123 also has the identification code of the graphics processor 121, when the graphics processor 121 and the memory unit 123 perform data transmission, the temporary storage device 125 can continuously store the identification code of the graphics processor 121, or change the memory. The identification code of unit 123.

In this embodiment, by reading the data stored in the register 125, it can be known whether the graphics processor 121 can normally perform data transmission with the memory unit 122. For example, when the memory unit 122 is enabled, the register 125 can store the identification code of the graphics processor 121 or the identification code of the memory unit 122.

However, when the graphics processor 121 cannot perform data transmission with the memory unit 122, the temporary memory 125 cannot store the identification code of the graphics processor 121 or the identification code of the memory unit 122. Therefore, by reading the data stored in the register 125, it can be known whether the graphics processor 121 can normally perform data transmission with the memory unit 122.

The present invention does not limit which of the actions of the read register 125 is performed. In a possible embodiment, the data temporarily stored by the register 125 can be read by the SBIOS 130 or the control unit 124.

If the data temporarily stored by the scratchpad 125 is read by the SBIOS 130, the SBIOS 130 will issue a control signal S _C based on the read result. Control unit 124 enables memory unit 122 or 123 based on control signal S _C . In this example, the SBIOS 130 reads the scratchpad 125 and issues a control signal S _C through the system management bus (SMBus) 140.

If the register 125 is read by the control unit 124, the control unit 124 can enable the memory unit 122 or 123 according to the read result. In this example, the control unit 124 reads the data of the register 125 through a general-purpose input/output (GPIO) 127 or transmits a signal to the graphics processor 121. Further, when the register 125 is read by the control unit 124, the connection between the SBIOS 130 and the control unit 124 in Fig. 1 can be omitted.

In the above embodiment, based on the data stored in the register 125, it is known whether the graphics processor 121 normally performs data transmission with the memory unit 122, but is not intended to limit the present invention. In other embodiments, other manners can be used to know whether the graphics processor 121 is normally transmitting data with the memory unit 122.

Figure 2 is a possible embodiment of one of the control units of the present invention. As shown, the control unit 124 includes a micro-controller 210 and a switch 230. The microcontroller 210 generates a switching signal S _S based on the control signal S _C . In one possible embodiment, the microcontroller 210 utilizes a general purpose input output (GPIO) terminal to transmit the switching signal S _S .

In the present embodiment, the control signal S _C is generated by the SBIOS 130. The SBIOS 130 detects the register 125 and generates a control signal S _C based on the detection result.

The switch 230 transmits the operating voltage V _CC to the memory unit 122 or 123 in accordance with the switching signal S _S . When the switch 230 transmits the operating voltage V _CC to the memory unit 122, the memory unit 122 can be enabled. When the switch 230 transmits the operating voltage V _CC to the memory unit 123, the memory unit 123 can be enabled.

In a possible embodiment, the switch 230 transmits the operating voltage V _CC to the memory unit 122 or 123 according to the level of the switching signal S _S . For example, if the switching signal S _S is at a low level, the switch 230 transmits the operating voltage V _CC to the memory unit 122; if the switching signal S _S is at a high level, the switch 230 transmits the operating voltage V _CC to the memory unit 123.

In other embodiments, control unit 124 further includes a resetter 250. The resetter 250 resets the drawing processor 121 in accordance with the control signal S _C . Both the microcontroller 210 and the resetter 250 are coupled to the SBIOS 130 via the SMBus.

Figure 3 is another possible embodiment of the control unit of the present invention. As shown, the control unit 124 includes a microcontroller 310 and a switch 330. The microcontroller 310 detects the register 125 and generates a switching signal S _S according to the detection result. In a possible embodiment, the microcontroller 310 reads the data temporarily stored by the register 125 through the general purpose input/output (GPIO) terminal. The data temporarily stored in the register 125 may be the identification code of the graphics processor 121 or the identification code of the memory unit 122 or 123.

The switch 330 transmits the operating voltage V _CC to the memory unit 122 or 123 in accordance with the switching signal S _S . When the operating voltage V _CC is transmitted to the memory unit 122, the memory unit 122 is enabled. When the operating voltage V _CC is transmitted to the memory unit 123, the memory unit 123 is enabled.

In the embodiment, the control unit 124 further includes a resetter 350. The resetter 350 resets the graphics processor 121 based on the detection result of the microcontroller 310. In a possible embodiment, the resetter 350 determines whether to reset the graphics processor 121 based on the state of the switching signal S _S . For example, when the switching signal S _S is at a low level, the resetter 350 does not reset the graphics processor 121. The resetter 350 resets the drawing processor 121 when the switching signal S _S is at a high level.

Figure 4 is another possible embodiment of the control unit of the present invention. As shown, the control unit 124 includes a microcontroller 410, a switch 430, a counter 470, and a processor 490. The microcontroller 410 reads the register 125. The processor 490 generates a switching signal S _S based on the count value of the counter 470 and the read result of the microcontroller 410. The switch 430 transmits the operating voltage V _CC to the memory unit 122 or 123 in accordance with the switching signal S _S . Since the characteristics of the switch 430 are similar to those of the switch 230, they will not be described again.

In other embodiments, the control unit 124 further includes a resetter 450. The resetter 450 resets the drawing processor 121 in accordance with the switching signal S _S . In addition, when the counter 470 counts to a predetermined value, a trigger signal S _T can be generated to the processor 490. In the present embodiment, the preset value is related to the time of a set action performed by the SBIOS 130.

For example, the time that the counter 470 counts to the preset value is greater than the time that the SBIOS 130 performs the preset action. That is, when the counter 470 counts up to the preset value, the SBIOS 130 has completed the preset action. Therefore, when the counter 470 generates the trigger signal S _T and the microcontroller 410 cannot read the data stored in the register 125, the switch 430 transfers the operating voltage V _CC to the memory unit 123.

In other embodiments, it is assumed that the preset action performed by the SBIOS 130 is the booting action of the computer device. When the counter 470 does not generate the trigger signal S _T , it indicates that the SBIOS 130 has not completed the preset action. In this case, it may be that the computer device is down. Therefore, the switch 430 does not transfer the operating voltage V _CC to the memory unit 123 to prevent the user from mistakenly thinking that the memory unit 122 is abnormal.

Figure 5 is a possible flow chart of one of the processing methods of the present invention. The processing method of the present invention is applicable to a processing module, wherein the processing module includes a first memory unit, a second memory unit, and a graphics processor.

First, a first memory unit is enabled (step S510), so that the graphics processor and the first memory unit perform data transmission. The invention does not limit the method of enabling the memory unit. In this embodiment, an operating voltage is supplied to the first memory unit for the purpose of enabling the first memory unit.

It is judged whether the data transfer between the drawing processor and the first memory unit is normal (step S530). The present invention does not limit the manner of determination of step S530. In a possible embodiment, it can be determined whether the data transmission between the graphics processor and the first memory unit is normal by determining the data stored in a register of the graphics processor.

For example, when the graphics processor performs data transmission with the first memory unit, since the first memory unit has a first identification code, a temporary memory of the graphics processor can store the first identification code. When the temporary storage device can no longer continue to store the first identification code, it indicates that the graphics processor cannot continue to perform data transmission with the first memory unit.

If the data transmission between the drawing processor and the first memory unit is normal, step S510 is performed to continue enabling the first memory unit. When the graphics processor is unable to perform data transmission with the first memory unit, the second memory unit is enabled (step S550), so that the graphics processor and the second memory unit perform data transmission.

For example, the first and second memory units each have an identification code of the graphics processor. Therefore, when the first memory unit and the graphics processor perform data transmission, the scratchpad of the graphics processor can store the identification code of the graphics processor. When the scratchpad cannot continue to store the identification code of the graphics processor, it indicates that the first memory unit cannot perform normal data transmission with the graphics processor. Therefore, the second memory unit is enabled.

Since the second memory unit also has an identification code of the graphics processor. Therefore, when the second memory unit and the graphics processor perform data transmission, the scratchpad of the graphics processor can continue to store the identification code of the graphics processor.

In another possible embodiment, the first and second memory units respectively store a first flag and a second flag. When the first memory unit and the graphics processor perform data transmission, the scratchpad of the drawing processor can store the first flag (that is, the identification code of the first memory unit).

When the scratchpad cannot continue to store the first flag, it indicates that the first memory unit cannot perform normal data transmission with the graphics processor. Therefore, the second memory unit is enabled. When the second memory unit and the graphics processor perform data transmission, the scratchpad of the graphics processor can store the second flag of the second memory unit.

In other embodiments, when the graphics processor is unable to perform data transfer with the first memory unit, in addition to enabling the second memory unit (step S550), the graphics processor can be reset.

In summary, when the first memory unit cannot perform data transmission with the graphics processor, data transmission may be performed by the second memory unit and the graphics processor to maintain the operation of the graphics processor.

In addition, when the data stored by the first memory unit (such as the operating frequency of the graphics processor) causes the graphics processor to be inoperable, the graphics processor can be individually reset before the second memory unit is enabled. Since the graphics processor can be reset individually, there is no need to restart the operating system.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . operating system

110. . . motherboard

120. . . Processing module

130. . . SBIOS

140. . . System management bus

121. . . Graphics processor

122, 123. . . Memory unit

124. . . control unit

125. . . Register

126. . . Transmission bus

127. . . Universal input and output

210, 310, 410. . . Microcontroller

230, 330, 430. . . Switcher

250, 350, 450. . . Resetter

470. . . counter

490. . . processor

S510~S550. . . step

Figure 1 is a schematic illustration of one of the operating systems of the present invention.

Figure 2 is a possible embodiment of one of the control units of the present invention.

Figures 3 and 4 show other possible embodiments of the control unit of the present invention.

Figure 5 is a possible flow chart of one of the processing methods of the present invention.

S510, S530, S550. . . step

Claims (43)

A processing module includes: a graphics processing unit (GPU) having a temporary memory; a first memory unit configured to perform data transmission with the graphics processor when the first memory unit is enabled; a second memory unit, wherein when the second memory unit is enabled, data can be transmitted with the graphics processor; and a control unit that enables the first memory unit when the first memory unit cannot The control unit enables the second memory unit when the graphics processor performs data transmission. The processing module of claim 1, further comprising: a transmission bus, the transmission bus is coupled between the first memory unit and the graphics processor. The processing module of claim 2, wherein the transmission bus is an internal integrated circuit (I-squared-C; I ² C) bus. The processing module of claim 1, wherein the control unit is coupled to a system basic output input system (System BIOS), wherein the basic output input system detects the register, and according to the detection result, A control signal is generated, and the control unit enables the first or second memory unit according to the control signal. The processing module of claim 4, wherein the control unit comprises: a microcontroller, generating a switching signal according to the control signal; and a switch, according to the switching signal, an operating voltage Transmitting to the first or second memory unit, when the operating voltage is transmitted to the first memory unit, the first memory unit is enabled, and when the operating voltage is transmitted to the second memory unit, The second memory unit is enabled. The processing module of claim 5, wherein the control unit further comprises: a resetter for resetting the graphics processor according to the control signal; and a first system management bus (System Management Bus; SMBus) is coupled between the system basic output input system and the graphics processor; and a second system management bus is coupled between the system basic output input system and the microcontroller. The processing module of claim 5, wherein the microcontroller has a general-purpose input/output (GPIO) terminal for transmitting the switching signal. The processing module of claim 1, wherein the control unit comprises: a microcontroller, detecting the register, and generating a switching signal according to the detection result; and a switch, according to The switching signal transmits an operating voltage to the first or second memory unit, and when the operating voltage is transmitted to the first memory unit, the first memory unit is enabled, when the operating voltage is transmitted to In the second memory unit, the second memory unit is enabled. The processing module of claim 8, wherein the control unit further comprises a resetter for resetting the graphics processor according to the detection result of the microcontroller. The processing module of claim 1, wherein the control unit comprises: a counter; a microcontroller, reading the register; a processor, according to the counter value and the micro control a reading result of the device, generating a switching signal; and a switch, according to the switching signal, transmitting an operating voltage to the first or second memory unit, when the operating voltage is transmitted to the first memory unit, Then the first memory unit is enabled, and when the operating voltage is transmitted to the second memory unit, the second memory unit is enabled. The processing module of claim 10, wherein the control unit further comprises a resetter for resetting the graphics processor according to the switching signal. The processing module of claim 10, wherein when the counter value of the counter is equal to a preset value, and the microcontroller cannot read the data stored by the register, the switch transmits the The operating voltage is applied to the second memory unit. The processing module of claim 12, wherein the preset value is related to a time when a system basic output input system performs a setting action. The processing module of claim 13, wherein the counter counts the preset value for a time greater than a time during which the system basic output input system performs the setting action. The processing module of claim 1, wherein the first memory unit has a first identification code, and the second memory unit has a second identification code, the first identification code being identical to the second identification code. . The processing module of claim 15, wherein when the first memory unit is enabled, the temporary storage unit stores the first identification code, and when the control unit does not detect the temporary storage unit When the first identification code is stored, the control unit enables the second memory unit to cause the temporary storage to store the second identification code. The processing module of claim 1, wherein the first memory unit has a first flag, and the second memory unit has a second flag, the first flag is different from the Second flag. The processing module of claim 17, wherein when the first memory unit is enabled, the register stores the first flag, and when the control unit does not detect the register When the first flag is stored, the control unit enables the second memory unit to cause the register to store the second flag. The processing module of claim 17, wherein the graphics processor has a general-purpose input/output (GPIO) terminal, and the control unit reads the register through the general-purpose input and output terminals. An operating system includes: a system basic output input system (System BIOS) for performing a setting action; a graphics processing unit (GPU) having a register; a first memory unit, when the first memory unit When enabled, data can be transmitted with the graphics processor; a second memory unit, when the second memory unit is enabled, can perform data transmission with the graphics processor; and a control unit, The first memory unit is enabled, and when the first memory unit is unable to perform data transmission with the graphics processor, the control unit enables the second memory unit. The operating system of claim 20, further comprising: a transmission bus, coupled between the first memory unit and the graphics processor. The operating system of claim 21, wherein the first transmission bus is an internal integrated circuit (I-squared-C; I ² C) bus. The operating system of claim 20, wherein the system basic output input system detects the register, and generates a control signal according to the detection result, and the control unit enables the first according to the control signal One or second memory unit. The operating system of claim 23, wherein the control unit comprises: a microcontroller, generating a switching signal according to the control signal; and a switch for transmitting an operating voltage according to the switching signal Up to the first or second memory unit, when the operating voltage is transmitted to the first memory unit, the first memory unit is enabled, and when the operating voltage is transmitted to the second memory unit, The second memory unit is enabled. The operating system of claim 24, wherein the control unit further comprises: a resetter for resetting the graphics processor according to the control signal; and a first system management bus (System Management Bus) SMBus) is coupled between the system basic output input system and the graphics processor; and a second system management bus is coupled between the system basic output input system and the microcontroller. The operating system of claim 24, wherein the microcontroller has a general purpose input/output (GPIO) terminal for transmitting the switching signal. The operating system of claim 20, wherein the control unit comprises: a microcontroller, detecting the register, and generating a switching signal according to the detection result; and a switch, according to the switch Switching a signal to transmit an operating voltage to the first or second memory unit, when the operating voltage is transmitted to the first memory unit, the first memory unit is enabled, when the operating voltage is transmitted to the In the case of the second memory unit, the second memory unit is enabled. The operating system of claim 27, wherein the control unit further comprises a resetter for resetting the graphics processor according to the detection result of the microcontroller. The operating system of claim 20, wherein the control unit comprises: a counter; a microcontroller, reading the register; a processor, according to the counter value of the counter and the microcontroller a reading result, generating a switching signal; and a switch, according to the switching signal, transmitting an operating voltage to the first or second memory unit, when the operating voltage is transmitted to the first memory unit, The first memory unit is enabled, and when the operating voltage is transmitted to the second memory unit, the second memory unit is enabled. The operating system of claim 29, wherein the control unit further comprises a resetter for resetting the graphics processor according to the switching signal. The operating system of claim 29, wherein the switch transmits the operation when the counter is equal to a predetermined value and the microcontroller is unable to read the data stored in the register. The voltage is applied to the second memory unit. The operating system of claim 31, wherein the preset value is related to a time of a setting action performed by a system basic output input system. The operating system of claim 32, wherein the counter counts the preset value for a time greater than a time during which the system basic output input system performs the setting action. The operating system of claim 20, wherein the first memory unit has a first identification code, and the second memory unit has a second identification code, the first identification code being identical to the second identification code. The operating system of claim 34, wherein when the first memory unit is enabled, the temporary storage unit stores the first identification code, and when the control unit does not detect the storage of the temporary storage unit When the first identification code is used, the control unit enables the second memory unit, so that the register stores the second identification code. The operating system of claim 20, wherein the first memory unit has a first flag, and the second memory unit has a second flag, the first flag is different from the first Two flags. The operating system of claim 36, wherein when the first memory unit is enabled, the register stores the first flag, and when the control unit does not detect the storage of the register When the first flag is used, the control unit enables the second memory unit, so that the register stores the second flag. The operating system of claim 36, wherein the graphics processor has a general-purpose input/output (GPIO) terminal, and the control unit reads the register through the general-purpose input and output terminals. A processing method includes: enabling a first memory unit for data transmission with a graphics processor; determining whether data transmission between the graphics processor and the first memory unit is normal; and when the graphics processor When the data transfer cannot be performed with the first memory unit, a second memory unit is enabled, so that the graphics processor and the second memory unit perform data transmission. The processing method of claim 39, wherein the detecting step detects data stored in a register of the graphics processor. The processing method of claim 40, wherein when the graphics processor and the first memory unit perform data transmission, an identification code is stored in the temporary memory. The processing method of claim 40, wherein when the temporary storage device cannot store the identification code, it is determined that the graphics processor cannot perform data transmission with the first memory unit. The processing method of claim 39, further comprising: enabling a second memory unit when the graphics processor is unable to perform data transmission with the first memory unit, and resetting the graphics processor.