CN103728516B - Soc chip clock detection circuit - Google Patents
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- CN103728516B CN103728516B CN201410009296.3A CN201410009296A CN103728516B CN 103728516 B CN103728516 B CN 103728516B CN 201410009296 A CN201410009296 A CN 201410009296A CN 103728516 B CN103728516 B CN 103728516B
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Abstract
The invention provides a kind of clock detection circuit of SOC chip, comprise timing unit, clock signal judging unit, detection computations unit, detection record unit and text contrast unit. Clock signal judging unit judges according to high frequency clock signal whether clock signal to be observed occurs rising edge and/or trailing edge and determine origination point information, the temporal information that detection computations unit produces according to origination point information, timing unit, the configuration information of configuration information cell stores judge the frequency of clock to be observed, dutycycle, off state and whether occur burr, and result of calculation is stored in to detection record unit. Text contrast unit contrasts to export automatic Verification result by the result of calculation of storing in the expectation file of storing in expected result memory cell and detection record unit. Utilize the present invention, solve complicated multi-clock zone SOC chip sampling conventional method in prior art and expend extensive work amount and bring the technical problem of manual detection error.
Description
Technical field
The present invention relates to chip detection technical field, relate in particular to a kind of clock detection circuit of SOC chip.
Background technology
At present, (the use scale of (System-on-a-Chip) chip is increasing, and complexity more and more for SOCHeight, in order to improve performance and to reduce chip power-consumption, in chip, clock zone is more and more, corresponding clock quantityAlso more and more. And traditional clock verification method is common and normal signal checking is similar, be all by pure handWork checks that checking and human eye observation procedure verify the correctness of clock. But, along with clock quantity fastIncrease, conventional method has been difficult to complete fast and accurately time clock feature checking, conventionally need to spend a lot of timeGo clock checking work, be also accompanied by the manual errors risk that manual working brings simultaneously. So, asWhat fast and accurately verifies that the clock in large-scale SOC chip has become a technical problem urgently to be resolved hurrily.
In conventional method, SOC chip being completed after the emulation of a clock test use-case, need to preserve instituteSome wave files are opened simulation document observation waveform in simulation software, need manual finding when allClock signal, and signal is put into simulation waveform, observe simultaneously in each conversion process, whether occurred burr withAnd the clock cycle length of frequency conversion front and back, and whether the frequency values obtaining before and after frequency conversion by manual calculation meetsExpection. In the chip that only has a small amount of clock, conventional method can also be used. But, at complicated multi-clockIn the SOC chip of territory, conventional method can expend the certain manual detection error risk of bringing of extensive work amount.
Summary of the invention
Embodiment of the present invention technical problem to be solved is, a kind of clock detection of SOC chip is providedCircuit, expends extensive work amount to solve complicated multi-clock zone SOC chip sampling conventional method in prior artAnd the technical problem of bringing manual detection to slip up.
For solving the problems of the technologies described above, the invention provides a kind of clock detection circuit of SOC chip, connect oneClock to be observed is inputted so that this clock to be observed is detected, and this clock detection circuit comprises timing listUnit, for generation time information in the time that this clock detection circuit is worked. Also comprise:
Configuration information memory cell, for pre-stored configuration information, this configuration information comprise clock turn-off sentenceDisconnected threshold value and burr decision gate limit value.
Expected result memory cell, pre-stored expectation file, this expectation file comprises clock frequency, dutyRatio and the time of origin turn-offing.
High frequency clock generation unit, for generation of high frequency clock signal.
Whether clock signal judging unit, for judging clock signal to be observed according to this high frequency clock signalThere is rising edge and/or trailing edge, and determine origination point information corresponding while there is rising edge and/or trailing edge.
Detection computations unit, for appearance rising edge and/or the decline definite according to this clock signal judging unitAlong time corresponding origination point information and this timing unit temporal information of producing calculate the frequency of this clock to be observedRate and dutycycle, and during according to the definite appearance rising edge of this clock signal judging unit and/or trailing edge pairIn the origination point information of answering, the temporal information that this timing unit produces, this configuration information memory cell, storeConfiguration information judges that this clock to be observed is whether in off state and whether occur burr.
Detection record unit, for storing the result of calculation of this detection computations unit. And
Text contrast unit, for expectation file and this detection note that this expected result memory cell is storedThe result of calculation of storing in record unit contrasts to export automatic Verification result.
The clock detection circuit of a kind of SOC chip provided by the invention, by the detection computations unit pair arrangingClock signal to be observed is carried out clock frequency, clock duty cycle, whether clock is turned off and clock occursThe parameters such as burr are calculated, and determine final by text contrast unit according to expected result and result of calculationSimulation result. All events are free record all, facilitates between inspection event when sequencing and event occurBetween, and can not need to preserve the wave file of emulation. Thereby, solve complicated multi-clock in prior artTerritory SOC chip sampling conventional method expends extensive work amount and brings the technical problem of manual detection error.
Brief description of the drawings
Fig. 1 is the electrical block diagram of the clock detection circuit of the SOC chip in embodiment of the present invention;
Fig. 2 is the structure chart of the rising edge judge module in the clock detection circuit of the SOC chip shown in Fig. 1;
Fig. 3 is the structure chart of the trailing edge judge module in the clock detection circuit of the SOC chip shown in Fig. 1.
Label declaration:
Clock detection circuit 10
High frequency clock generation unit 11
Clock signal judging unit 12
Rising edge judge module 121
Trailing edge judge module 122
Timing unit 13
Current frequency values memory cell 14
Configuration information memory cell 15
Detection computations unit 16
Frequency computation part module 161
Dutycycle computing module 162
Clock turn-offs detection module 163
Clock bur detection module 164
Expected result memory cell 17
Detection record unit 18
Text contrast unit 19
Detailed description of the invention
By describing technology contents of the present invention, structural feature in detail, being realized object and effect, below in conjunction withEmbodiment also coordinates accompanying drawing to be explained in detail.
Refer to Fig. 1, when the clock detection circuit 10 of the SOC chip in embodiment of the present invention comprises high frequencyClock generation unit 11, clock signal judging unit 12, timing unit 13, current frequency values memory cell 14,Configuration information memory cell 15, detection computations unit 16, expected result memory cell 17, detection record unit18 and text contrast unit 19. Wherein, this high frequency clock generation unit 11, clock signal judging unit12 and detection computations unit 16 connect successively, this current frequency values memory cell 14, configuration information storageUnit 15, timing unit 13 and detection record unit 18 are all connected with this detection computations unit 16, this phaseHope result store unit 17 be connected with text contrast unit 19 with detection record unit 18 simultaneously.
When utilizing before this clock detection circuit 10 starts to carry out clock signal detection validation, need to be to be observedClock input be connected on the clock that needs observation, make clock to be observed can correctly input this clock inspectionSlowdown monitoring circuit 10. Meanwhile, the pre-stored configuration information of this configuration information memory cell 15, this configuration information comprisesClock turn-offs decision gate limit value and burr decision gate limit value. The pre-stored emulation of this expected result memory cell 17The time of origin of desired clock frequency, dutycycle and shutoff in use-case, for the inspection of actual verificationSurvey log file compares.
In the time that this clock detection circuit 10 starts to carry out clock signal detection validation, this high frequency clock generation unit11 for generation of high frequency clock signal and input this high frequency clock signal to this clock signal judging unit 12, shouldClock signal judging unit 12 is for judging whether clock signal to be observed occurs rising edge and/or trailing edge,And when determining while there is rising edge and/or trailing edge, corresponding origination point information is sent to detection computations unit16。
In the present embodiment, this clock signal judging unit 12 comprises rising edge judge module 121 and declinesAlong judge module 122. Please refer to Fig. 2 and Fig. 3, be respectively this rising edge judge module 121 and declineAlong the structural representation of judge module 122. This rising edge judge module 121 comprise first order register D1,Second level register D2 and rising edge determining device D3, this first order register D1 utilizes high frequency clock to produceThe high frequency clock signal that unit 11 produces agitates this clock signal to be observed for twice, if first order register D1Output valve be the output valve of height and second level register D2 while being low, this rising edge determining device D3 determinesThere is rising edge in clock signal now. This trailing edge judge module 122 comprises first order register D4,Secondary register D5 and trailing edge determining device D6, same, this first order register D4 utilizes high frequency clockThe high frequency clock signal that generation unit 11 produces agitates this clock signal to be observed for twice, if first order registerWhen the output valve of D4 is low and the output valve of second level register D5 is high, this trailing edge determining device D6Determine that trailing edge appears in clock signal now.
This timing unit 13 is made up of timer, for generation time in the time that this clock detection circuit 10 is workedInformation. This detection computations unit 16 according to the definite appearance rising edge of this clock signal judging unit 12 and/orThe temporal information that when trailing edge, corresponding origination point information and this timing unit 13 produce calculates this time to be observedThe frequency of clock and dutycycle, and according to the definite appearance rising edge of this clock signal judging unit 12 and/or underFall along time corresponding origination point information, temporal information, this configuration information storage that this timing unit 13 produces singleIn unit 15, the configuration information of storage judges that this clock to be observed is whether in off state and whether occur hairThorn.
In the present embodiment, this detection computations unit 16 comprises frequency computation part module 161, dutycycle calculatingModule 162, clock turn-off detection module 163 and clock bur detection module 164. Wherein, this frequency meterCalculate module 161 according to the definite rising edge origination point information of this rising edge judge module 121 and this timing unit13 temporal informations that produce calculate the frequency of this clock to be observed, and result of calculation is sent to this current frequencyRate value memory cell 14 and this detection record unit 18 are stored. This dutycycle computing module 162 is during according to thisThe rising edge that clock signal judging unit 12 is definite or/and trailing edge origination point information and this timing unit 13 produceTemporal information calculate the dutycycle of this clock to be observed, and result of calculation is sent to this detection record listUnit's 18 storages. This clock turn-offs detection module 163 rising edge definite according to this rising edge judge module 121Temporal information and this configuration information memory cell 15 that origination point information, this timing unit 13 produce are storedClock turn-off decision gate limit value and whether calculate this clock to be observed in off state, and judged resultBeing sent to this detection record unit 18 stores. This clock bur detection module 164 is according to this clock signal judgementTemporal information that the rising edge that unit 12 is definite and/or trailing edge origination point information, this timing unit 13 produce,The frequency of this clock to be observed that this frequency computation part module 161 calculates and this configuration information memory cell 15The burr decision gate limit value of storage calculates this clock to be observed and whether occurs burr, and judged result is sentStore to this detection record unit 18.
Particularly, the computational methods that this frequency computation part module 161 is calculated the frequency of this clock to be observed are: shouldFrequency computation part module 161 comprises a rising time memory (not shown), for storing the last receptionThe time of the rising edge arriving, its initial default value is 0. Export whenever receiving this rising edge judge module 121Rising edge useful signal time store the temporal information that this timing unit 13 was inputted at that time into this rising timeIn memory. When receiving next time after rising edge useful signal, temporal information is at that time deducted to this risingTo obtain the time difference of twice rising edge, then use 1 along the last rising time information in time memoryObtain frequency values divided by the time difference (chronomere be second), simultaneously this time information renovation storageInterior to cover the temporal information of last time to this rising time memory. If this frequency computation part module 161The frequency values calculating is the same with the frequency values of storage in this current frequency values memory cell 14, not to this detectionRecord cell 18 is exported new recorded information, if the frequency values that this frequency computation part module 161 calculates and thisIn current frequency values memory cell 14, the frequency values of storage is different, exports to this detection record unit 18New recorded information is upgraded this current frequency values memory cell 14 simultaneously. Wherein, this frequency computation part module 161The file format that outputs to this detection record unit 18 is the time point of current frequency and change of frequency.
The computational methods that this dutycycle computing module 162 calculates the dutycycle of this clock to be observed are: Mei DangjieReceive after the rising edge useful signal that this rising edge judge module 121 exports, by defeated timing unit at that time 13The temporal information entering stores in this rising time memory. Whenever receiving this trailing edge judge module 122After the trailing edge useful signal of output, the temporal information that timing unit at that time 13 is inputted stores this decline intoAlong in time memory. When receiving next time after rising edge useful signal, temporal information is at that time deductedLast rising time information in this rising time memory is to obtain the time difference of twice rising edge.Then, the temporal information of this rising time memory is deducted to the time letter in this trailing edge time memoryBreath, to obtain the time span of high level, finally uses the time span of high level divided by the time of twice rising edgePoor to obtain the value of clock duty cycle. If it is up-to-date that this dutycycle computing module 162 relatively calculatesWhen clock duty cycle value is the same with value in this current dutyfactor value memory, not to this detection record unitThe new recorded information of 18 output, if the up-to-date clock that this dutycycle computing module 162 relatively calculatesWhen value in dutyfactor value and this current dutyfactor value memory is different, defeated to this detection record unit 18The recorded information making new advances, what upgrade this current dutycycle memory is last look simultaneously. Wherein, this dutycycleThe form that computing module 162 outputs to the file of this detection record unit 18 is current clock duty cycle and accounts forThe empty time point than changing.
This clock turn-offs detection module 163 and calculates the whether computational methods in off state of these clocks to be observedFor: this clock turn-offs detection module 163 and comprises a rising time memory, connects for storing the last timeReceive the time of rising edge, its initial default value is 0. Export whenever receiving this rising edge judge module 121Rising edge useful signal time temporal information that timing unit at that time 13 is inputted store this rising time intoIn memory. Calculate in time of timing unit 13 current inputs and this rising time memory, store timeBetween time difference of value, by the clock shutoff decision gate of storage in this time difference and this configuration information memory cell 15Limit value compares, if when this time difference is greater than this clock shutoff decision gate limit value, judge that this is to be detectedClock is turned off, and outputs to this detection record unit 18 and store. Wherein, this clock turn-offs detection module 163The form that outputs to detection record file is the time point that judges that clock shutoff event occurs and occurs.
This clock bur detection module 164 judges whether this clock to be observed occurs that the computational methods of burr are:This clock bur detection module comprises a rising time memory and a trailing edge time memory, uses respectivelyIn the last time that receives rising edge and trailing edge of storage, its initial default value is 0. Whenever receivingAfter the rising edge useful signal that this rising edge judge module 121 is exported, timing unit at that time 13 is inputted timeBetween information store in this rising time memory. Export whenever receiving this trailing edge judge module 122Trailing edge useful signal after temporal information that timing unit at that time 13 is inputted store this trailing edge time intoIn memory. Calculate the time of the time value of storing in rising time memory and trailing edge time memoryDifference, if this time difference is less than the burr decision gate limit value of storage in this configuration information memory cell 15,Judge that burr appears in this clock to be detected, and this judged result is outputed to this detection record unit 18. ItsIn, this clock bur detection module 164 outputs to the form of file of this detection record unit 18 when judgingThere is the time point that burr event occurs and occurs in clock.
Text contrast unit 19 is by expectation file and this detection of storage in this expected result memory cell 17The detection record file that in record cell 18, this detection computations unit 16 of storage calculates contrasts to exportAutomatic Verification result. Particularly, text contrast unit 19 is according to storage in this detection record unit 18Detection record file judges whether the jagged information that occurs, occurs information if jagged, and the result of exporting isMistake. If do not have burr to occur information, expectation file and detection record file are contrasted, when reallyRegularly hope when file is consistent with detection record file that Output rusults is that emulation is correct, when determine expect file andWhen detection record file is inconsistent, Output rusults is dummy error.
The clock detection circuit of a kind of SOC chip provided by the invention, by the detection computations unit pair arrangingClock signal to be observed is carried out clock frequency, clock duty cycle, whether clock is turned off and clock occursThe parameters such as burr are calculated, and determine final by text contrast unit according to expected result and result of calculationSimulation result. All events are free record all, facilitates between inspection event when sequencing and event occurBetween, and can not need to preserve the wave file of emulation. Thereby, solve complicated multi-clock in prior artTerritory SOC chip sampling conventional method expends extensive work amount and brings the technical problem of manual detection error.
The foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, every profitThe equivalent structure of doing by description of the present invention and accompanying drawing content or the conversion of equivalent flow process, or directly or indirectly transportBe used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (8)
1. a clock detection circuit for SOC chip, connects a clock to be observed and inputs so that described waiting seenThe clock of surveying detects, and described clock detection circuit comprises timing unit, for working as described clock detection electricityGeneration time information while work in road; It is characterized in that, also comprise:
Configuration information memory cell, for pre-stored configuration information, described configuration information comprises that clock turn-offsDecision gate limit value and burr decision gate limit value;
Expected result memory cell, pre-stored expectation file, described expectation file comprises clock frequency, accounts forEmpty ratio and the time of origin turn-offing;
High frequency clock generation unit, for generation of high frequency clock signal;
Clock signal judging unit, for judging that according to described high frequency clock signal clock signal to be observed isNo rising edge and/or the trailing edge of occurring, and determine origination point letter corresponding while there is rising edge and/or trailing edgeBreath;
Detection computations unit, for according to the definite appearance rising edge of described clock signal judging unit and/or underFall along time corresponding origination point information and the described timing unit temporal information that produces calculate described time to be observedThe frequency of clock and dutycycle, and according to the definite appearance rising edge of described clock signal judging unit and/or underFall along time corresponding origination point information, the described timing unit temporal information, the described configuration information storage that produceThe configuration information of storing in unit judges that described clock to be observed is whether in off state and whether occur hairThorn;
Detection record unit, for storing the result of calculation of described detection computations unit; And
Text contrast unit, for expectation file and described inspection that described expected result memory cell is storedSurvey the result of calculation of storing in record cell and contrast to export automatic Verification result.
2. the clock detection circuit of SOC chip as claimed in claim 1, is characterized in that, described clockSignal judging unit comprises rising edge judge module and trailing edge judge module, described rising edge judge module andTrailing edge judge module includes first order register, second level register and determining device;
When the first order register of described rising edge judge module utilizes the high frequency of high frequency clock generation unit generationClock signal agitates described clock signal to be observed for twice, when the first order register of described rising edge judge moduleOutput valve be output valve high, second level register while being low determining device determine that rising edge appears in clock signal;
When the first order register of described trailing edge judge module utilizes the high frequency of high frequency clock generation unit generationClock signal agitates described clock signal to be observed for twice, when the first order register of described trailing edge judge moduleOutput valve be output valve low, second level register while being high determining device determine that trailing edge appears in clock signal.
3. the clock detection circuit of SOC chip as claimed in claim 2, is characterized in that, described clockTesting circuit also comprises current frequency values memory cell, and described detection computations unit comprises:
Frequency computation part module, for according to the definite rising edge origination point information of described rising edge judge module andThe temporal information that described timing unit produces calculates the frequency of described clock to be observed, and result of calculation is sent outDeliver to described current frequency values memory cell and the unit storage of described detection record;
Dutycycle computing module, for what determine according to described rising edge judge module and trailing edge judge moduleRising edge or/and the temporal information that trailing edge origination point information and described timing unit produce wait to see described in calculatingSurvey the dutycycle of clock, and result of calculation is sent to the unit storage of described detection record;
Clock turn-offs detection module, for the rising edge origination point letter definite according to described rising edge judge moduleThe temporal information of breath, the generation of described timing unit and the clock of described configuration information cell stores turn-offWhether decision gate limit value calculates described clock to be observed in off state, and judged result is sent to instituteState the storage of detection record unit; And
Clock bur detection module, for determining according to described rising edge judge module and trailing edge judge moduleRising edge and/or trailing edge origination point information, described the timing unit temporal information, the described frequency meter that produceCalculate the frequency of described clock to be observed and the burr of described configuration information cell stores that module calculatesDecision gate limit value calculates described clock to be observed and whether occurs burr, and judged result is sent to described inspectionThe storage of survey record cell.
4. the clock detection circuit of SOC chip as claimed in claim 3, is characterized in that, described frequencyComputing module comprises a rising time memory, for storing the time of the rising edge that the last time receives,Its initial default value is 0; The frequency that described frequency computation part module is calculated described clock to be observed comprises:
In the time receiving the rising edge useful signal of described rising edge judge module output, incite somebody to action described timing list at that timeThe temporal information of unit's input stores in described rising time memory;
When receiving next time after rising edge useful signal, when temporal information is at that time deducted to described rising edgeBetween last rising time information in memory to obtain the time difference of twice rising edge; And
Obtain frequency values with 1 divided by the time difference, and store this time information renovation into described risingAlong in time memory to cover the temporal information of last time; When described frequency values and described current frequency values storageWhen the frequency values stored in unit is the same, do not export new recorded information to described detection record unit, when describedWhen the frequency values stored in frequency values and described current frequency values memory cell is different to described detection record listThe recorded information that unit's output is new, and upgrade described current frequency values memory cell, wherein, output to described inspectionSurvey the file format of record cell and be the time point of current frequency and change of frequency.
5. the clock detection circuit of SOC chip as claimed in claim 3, is characterized in that, described dutyComprise a rising time memory, a trailing edge time memory and a current dutycycle than computing moduleValue memory, the time and the storage that are respectively used to the last rising edge receiving of storage and trailing edge are worked asFront dutyfactor value, its initial default value is 0; Described dutycycle computing module calculates described clock to be observedDutycycle comprise:
When receiving after the trailing edge useful signal of described trailing edge judge module output, by timing list at that timeThe temporal information of unit's input stores in described trailing edge time memory;
When receiving next time after rising edge useful signal, when temporal information is at that time deducted to described rising edgeBetween last rising time information in memory to obtain the time difference of twice rising edge;
The temporal information of described rising time memory is deducted to the time in described trailing edge time memoryInformation is to obtain the time span of high level; And
By the time span of high level divided by time difference of twice rising edge to obtain the value of clock duty cycle; WillValue in the clock duty cycle value calculating and described current dutyfactor value memory compares, and when trueWhen fixed the same, do not export new recorded information to described detection record unit, when determining when different to described inspectionSurvey record cell and export new recorded information, and to upgrade described current dutyfactor value memory be last look, itsIn, the form that outputs to the file of described detection record unit is current clock duty cycle and change in duty cycleTime point.
6. the clock detection circuit of SOC chip as claimed in claim 3, is characterized in that, described clockTurn-off detection module comprise a rising time memory, for store the last time receive rising edge timeBetween, its initial default value is 0; Described clock turn-offs detection module and whether calculates described clock to be observed in closingDisconnected state comprises:
In the time receiving the rising edge useful signal of described rising edge judge module output by timing unit at that timeThe temporal information of input stores in described rising time memory;
The time of storing in the temporal information of the current input of calculating timing unit and described rising time memoryThe time difference of information; And
The clock of storing in described time difference and described configuration information memory cell is turn-offed to decision gate limit value to carry outRelatively, in the time that being greater than described clock shutoff decision gate limit value, judges definite described time difference described clock to be observedBe turned off, and output to the unit storage of described detection record, wherein, output to detection record unit latticeFormula is the time point that judges that clock shutoff event occurs and occurs.
7. the clock detection circuit of SOC chip as claimed in claim 3, is characterized in that, described clockBurr detection module comprises a rising time memory and a trailing edge time memory, is respectively used to storageThe last time receives the time of rising edge and trailing edge, and its initial default value is 0; Described clock bur detectsModule judges whether described clock to be observed occurs that burr comprises:
When after the rising edge useful signal that receives the output of described rising edge judge module by timing unit at that timeThe temporal information of input stores in described rising time memory;
When after the trailing edge useful signal that receives the output of described trailing edge judge module by timing unit at that timeThe temporal information of input stores in described trailing edge time memory;
Calculate the time difference of the temporal information of storing in rising time memory and trailing edge time memoryValue, and when determining that described time difference is less than the burr of storing in described configuration information memory cell and judges thresholdingWhen value, judge that burr appears in described clock to be observed, and judged result outputed to described detection record unit,Wherein, output to described detection record unit file form for judge clock occur burr event occur withThe time point occurring.
8. the clock detection circuit of SOC chip as claimed in claim 1, is characterized in that, described textContrast unit judges whether the jagged information that occurs according to the result of calculation of storing in this detection record unit, andBe mistake when defining the result of exporting when information appears in burr; When determining while not having burr to occur information instituteState and expect that file and described result of calculation contrast, when definite described expectation file and described result of calculation oneWhile causing, Output rusults is that emulation is correct, when definite described expectation file and the inconsistent time output of described result of calculationResult is dummy error.
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| CN105892559B (en) * | 2016-04-26 | 2018-12-18 | 福州瑞芯微电子股份有限公司 | The circuit and method of clock domain interaction |
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| CN101764594A (en) * | 2009-11-09 | 2010-06-30 | 天津南大强芯半导体芯片设计有限公司 | Clock signal detection circuit and abnormal clock signal detection method |
| CN201859389U (en) * | 2010-05-12 | 2011-06-08 | 华为技术有限公司 | Reset management chip and reset system |
| CN103365757A (en) * | 2013-07-29 | 2013-10-23 | 浙江中控技术股份有限公司 | Clock detecting method and device |
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