CN103729278B - SOC reset signal detection circuit - Google Patents
SOC reset signal detection circuit Download PDFInfo
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- CN103729278B CN103729278B CN201410009276.6A CN201410009276A CN103729278B CN 103729278 B CN103729278 B CN 103729278B CN 201410009276 A CN201410009276 A CN 201410009276A CN 103729278 B CN103729278 B CN 103729278B
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Abstract
The invention provides an SOC reset signal detection circuit. The SOC reset signal detection circuit comprises a first reset signal judgment unit, a reset detection calculation unit, a reset sequence judgment unit and a text comparison unit. The reset detection calculation unit calculates reset effective time, reset canceling time and reset keeping time and determines synchronous information of a synchronous clock according to generation point information, time information and configuration information, wherein the generation point information is generated when a rising edge and/or a falling edge appears, the time information is generated by a timekeeping unit, the configuration information is stored in a configuration information storage unit, and the generation point information, the time information and the configuration information are determined by a first reset information judgment unit. The text comparison unit compares expected files stored in an expected result storage unit with the calculation result stored in a detection recording unit according to the judgment result of the reset sequence judgment unit so as to output the automatic verification result. By means of the SOC reset signal detection circuit, the technical problem that in the prior art, manual detection errors occur due to the fact that a large number of workloads are consumed through a traditional complex multi-clock-domain SOC sampling method is solved.
Description
Technical field
The present invention relates to chip detection technical field, particularly relate to a kind of reset signal testing circuit of SOC.
Background technology
At present, (the use scale of (System-on-a-Chip) chip is increasing, and complexity is more and more higher, in order to improve performance and reduce chip power-consumption for SOC, the control that resets in chip becomes increasingly complex, and corresponding reset signal quantity also gets more and more.And traditional reset verification method is usual and normal signal checking is similar, be all check that checking and human eye observation's method verify the correctness of reset by pure craft.But along with the increasing fast of reset quantity, classic method has been difficult to the functional verification completing reset signal fast and accurately, usually needs to have spent a lot of time reset checking work, simultaneously also along with the human error risks that manual working brings.So the reset signal how verifying in large-scale SOC has become a technical matters urgently to be resolved hurrily fast and accurately.
In classic method, after emulation SOC being completed to a reset test use-case, need to preserve all wave files, simulation document observation waveform is opened in simulation software, need to find all reset signals to be verified by hand, and signal is put into simulation waveform observation window, the waveform of homing action each time dragged and observe each reset with convergent-divergent is pushed away by craft, whether with the synchronous reset signal expected be synchronously cancel relation, observe reset length whether meet minimal reset time requirement simultaneously if to observe in each reseting procedure simultaneously.In the chip only having a small amount of reset signal, classic method can also use.But, in complicated multi-clock zone SOC, classic method can at substantial workload bring certain manual detection error risk.
Summary of the invention
Embodiment of the present invention technical matters to be solved is, there is provided a kind of reset signal testing circuit of SOC, the technical matters bringing manual detection to slip up to solve complicated multi-clock zone SOC sampling classic method at substantial workload in prior art.
For solving the problems of the technologies described above, the invention provides a kind of reset signal testing circuit of SOC, one reset signal to be verified is connected with the input end of this reset signal testing circuit with appointment synchronizing clock signals, this reset signal testing circuit comprises timing unit, for the generation time information when this reset signal testing circuit works.Also comprise:
Configuration information storage unit, for prestoring configuration information, this configuration information comprises rising edge or negative edge effective information, the retention time requires information, reset between coming into force and cancelling precedence relationship requirement.
Expected result storage unit, for prestoring expectation file, this expectation file comprises the reset entry-into-force time and cancels the time.
High frequency clock generation unit, for generation of high frequency clock signal.
First reset signal judging unit, for judging whether reset signal to be verified occurs rising edge and/or negative edge according to this high frequency clock signal, and origination point information corresponding when determining to occur rising edge and/or negative edge.
Second reset signal judging unit, for producing according to the appointment synchronous clock of this input and the origination point information of the rising edge useful signal determined.
Reset detection computing unit, the temporal information produced for corresponding origination point information when the appearance rising edge determined according to this first reset signal judging unit and/or negative edge and this timing unit calculates and resets the entry-into-force time and cancel the time, according to reset entry-into-force time of this calculating with cancel the time, the origination point information of the rising edge useful signal that the configuration information stored in this configuration information storage unit and this second reset signal judging unit are determined judges whether the reset retention time of this reset signal to be verified meets preset value, and judge whether cancelling of this reset signal to be verified be synchronous with this synchronous clock of specifying.
Detection record unit, for storing the result of calculation of this reset detection computing unit.
Reset successively judging unit, for judging that according to entry-into-force time of configuration information and twice reset and the time of cancelling entry-into-force time between twice reset successively and cancel the precedence relationship successively whether meeting configuration.And
Transcription comparison's unit, for being undertaken contrasting to export automatic the result by the result of calculation stored in the expectation file stored in this expected result storage unit and this detection record unit according to the judged result of this reset successively judging unit.
The reset signal testing circuit of a kind of SOC provided by the invention, by the reset detection computing unit that arranges carried out to reset signal to be verified the resets entry-into-force time and cancel time, retention time and calculate with specifying the parameters such as whether clock synchronous, and determine final simulation result by reset successively judging unit and transcription comparison's unit according to expected result and result of calculation, make all free record of all events, facilitate sequencing and Time To Event between inspection event, and the wave file preserving emulation can not be needed.Thus, solve complicated multi-clock zone SOC sampling classic method at substantial workload in prior art and the technical matters of bringing manual detection to slip up.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the reset signal testing circuit of SOC in embodiment of the present invention;
The structural drawing of the rising edge judge module in the reset signal testing circuit that Fig. 2 is the SOC shown in Fig. 1;
The structural drawing of the negative edge judge module in the reset signal testing circuit that Fig. 3 is the SOC shown in Fig. 1.
Label declaration:
Reset signal testing circuit 10
High frequency clock generation unit 11
First reset signal judging unit 12
Rising edge judge module 121
Negative edge judge module 122
Timing unit 13
Reset entry-into-force time and cancel time memory cell 14
Configuration information storage unit 15
Reset detection computing unit 16
Reset comes into force and cancels judge module 161
Reset retention time checking module 162
Synchronous reset inspection unit 163
Expected result storage unit 17
Detection record unit 18
Transcription comparison's unit 19
Second reset signal judging unit 20
Reset successively judging unit 21
Embodiment
By describing technology contents of the present invention, structural attitude in detail, realized object and effect, accompanying drawing is coordinated to be explained in detail below in conjunction with embodiment.
Refer to Fig. 1, the reset signal testing circuit 10 of the SOC in embodiment of the present invention comprises high frequency clock generation unit 11, first reset signal judging unit 12, timing unit 13, reset entry-into-force time and cancel time memory cell 14, configuration information storage unit 15, reset detection computing unit 16, expected result storage unit 17, detection record unit 18, transcription comparison's unit 19, second reset signal judging unit 20 and the successively judging unit 21 that resets.Wherein, this high frequency clock generation unit 11, first reset signal judging unit 12 and reset detection computing unit 16 connect successively, this timing unit 13, reset the entry-into-force time with cancel time memory cell 14, configuration information storage unit 15, detection record unit 18 and the second reset signal judging unit 20 and be all connected with this reset detection computing unit 16, this expected result storage unit 17, detection record unit 18 and the successively judging unit 21 that resets contrast unit 19 with the text simultaneously and are connected.
When utilizing before this reset signal testing circuit 10 starts to carry out reset signal detection validation, need reset signal to be verified and specify synchronizing clock signals to be connected to the input end of this reset signal testing circuit 10, the reset signal making this to be verified can correctly input, and is resetted to come into force by other in other reset automatic Verification circuit having precedence relationship to require with this reset signal to be verified and cancel the input end that time signal is connected to this reset signal testing circuit 10.Meanwhile, this configuration information storage unit 15 prestores configuration information, this configuration information comprises rising edge or negative edge effective information, the retention time requires information, reset between coming into force and cancelling precedence relationship requirement.This expected result storage unit 17 prestores expectation file, and this expectation file comprises the reset entry-into-force time desired in emulation use-case and cancels the time, for comparing with the detection record file in actual verification.
When this reset signal testing circuit 10 starts to carry out reset signal checking, this high frequency clock generation unit 11 is for generation of high frequency clock signal and input this high frequency clock signal to this first reset signal judging unit 12, the origination point information of correspondence for judging whether reset signal to be verified occurs rising edge and/or negative edge, and is sent to reset detection computing unit 16 when determining to occur rising edge and/or negative edge by this first reset signal judging unit 12.
In the present embodiment, this first reset signal judging unit 12 comprises rising edge judge module 121 and negative edge judge module 122.Please refer to Fig. 2 and Fig. 3, be respectively the structural representation of this rising edge judge module 121 and negative edge judge module 122.This rising edge judge module 121 comprises first order register D1, second level register D2 and rising edge determining device D3, the high frequency clock signal that this first order register D1 utilizes high frequency clock generation unit 11 to produce agitates this reset signal to be verified for twice, if the output valve of first order register D1 be high and the output valve of second level register D2 is low time, this rising edge determining device D3 determines that rising edge appears in reset signal now.This negative edge judge module 122 comprises first order register D4, second level register D5 and negative edge determining device D6, equally, the high frequency clock signal that this first order register D4 utilizes high frequency clock generation unit 11 to produce agitates this reset signal to be observed for twice, if the output valve of first order register D4 be low and the output valve of second level register D5 is high time, this negative edge determining device D6 determines that negative edge appears in reset signal now.
This timing unit 13 is made up of timer, for the generation time information when this reset signal testing circuit 10 works.The temporal information that when the appearance rising edge that this reset detection computing unit 16 is determined according to this first reset signal judging unit 12 and/or negative edge, corresponding origination point information and this timing unit 13 produce calculates the reset time of coming into force and the time of cancelling, and be sent to this reset entry-into-force time and cancel time memory cell 14, reset successively judging unit 21 and detection record unit 18 store.For the origination point information of the rising edge useful signal produced according to this appointment synchronous clock with the configuration information and the second reset signal judging unit 29 of cancelling storage in time, this configuration information storage unit 15 according to the reset entry-into-force time determined, this reset detection computing unit 16 also judges whether the reset retention time of this reset signal to be verified meets preset value, and judge that whether cancelling of reset signal be synchronized relation with appointment synchronous clock, and sentence read result is sent to this detection record unit 18 and stores.
In the present embodiment, this reset detection computing unit 16 comprise reset come into force cancel judge module 161, reset retention time checking module 162 and synchronous reset inspection unit 163.
This reset come into force cancel rising edge origination point information that judge module 161 determines according to this rising edge judge module 121, the configuration information that stores in negative edge origination point information that negative edge judge module 122 is determined, this configuration information storage unit 15 judges reset entry-into-force time and the time of cancelling, and result of calculation is sent to this reset entry-into-force time and cancel time memory cell 14, resetting successively stores in judging unit 21 and detection record unit 18.Particularly, this reset comes into force and cancels judge module 161 according to effectively still negative edge effective information judgement the reset time of coming into force and the time of cancelling of the rising edge in configuration information.Such as, when setting negative edge is effective, then reset negative edge effective information arrive time, this reset comes into force and cancels judge module 161 and the action that comes into force of the temporal information of now timing unit 13 and reset can be sent to detection record unit 18 and preserve, and the entry-into-force time is sent to reset the entry-into-force time and cancel time memory cell 14 simultaneously and preserves.When receiving rising edge, illustrating resets is cancelled, now equally the temporal information of timing unit 13 and reset can be cancelled action to be sent to detection record unit 18 and to preserve, the time of cancelling is sent to reset the entry-into-force time and cancel time memory cell 14 simultaneously and preserve.
Reset entry-into-force time that this reset retention time checking module 162 obtained in time memory cell 14 according to this reset entry-into-force time and cancelling and cancel the configuration information stored in time and this configuration information storage unit 15 and judge whether this reset retention time meets preset value, and result of calculation is sent to this detection record unit 18 stores.Particularly, this checking module 162 can check the entry-into-force time and cancel in time memory cell 14 to reset and cancels and the mistiming between coming into force that resets of resetting reset retention time always, when the reset retention time be less than in configuration information when the mistiming requires, the retention time is not met information and time of origin and is sent in detection record unit 18 and preserves.
The origination point information of the rising edge that this synchronous reset checking module 163 produces according to this second reset signal judging unit 20 or negative edge useful signal and from this reset entry-into-force time and cancel the reset time of cancelling obtained time memory cell 14 judge reset signal cancel whether with specify synchronous clock to be synchronous relation, and judged result be sent to this detection record unit 18 store.In the present embodiment, this second reset signal judging unit 20 is rising edge judging unit, for sending the origination point information of rising edge useful signal.Particularly, the rising time of synchronous clock that this synchronous reset checking module 163 can produce according to this second reset signal judging unit 20 and the time of cancelling of reset signal to be verified compare, judging that when time consistency reset is cancelled with synchronous clock is synchronized relation, judging that when both Time Inconsistencies reset is cancelled with synchronous clock is not synchronized relation, then reset to be verified with specify the asynchronous information of clock and time of origin to be sent in detection record unit 18 to store.
This reset successively judging unit 21 according to coming into force of resetting of the precedence relationship between resetting and two and cancel temporal information judge two reset between entry-into-force time successively and cancel the precedence relationship successively whether meeting configuration, and judged result is sent to transcription comparison's unit 19.Such as, need the reset entry-into-force time to be verified will be later than other multiple entry-into-force times in configuration information, this reset successively judging unit 21 judges whether the entry-into-force time of reset signal to be verified is greater than the entry-into-force time of other resets, and meet the demands when determining the entry-into-force time being greater than other resets, otherwise do not meet the demands.The precedence relationship inspection that identical inspection method is also cancelled for resetting.
The detection record file that this reset detection computing unit 16 stored in the expectation file stored in this expected result storage unit 17 and this detection record unit 18 calculates carries out contrasting to export automatic the result by text contrast unit 19.Particularly, the text contrast unit 19 according in this detection record unit 18 store detection record file judge whether reset the retention time do not meet information, reset signal to be verified and specify the asynchronous information of clock or and other reset between precedence relationship do not meet.If had, then the result exported is mistake.If no, then expectation file and detection record file are contrasted, when determining to expect that file is consistent with detection record file, then Output rusults is correct for emulating, and when determining expectation file and detection record file is inconsistent, then Output rusults is dummy error.
The reset signal testing circuit of a kind of SOC provided by the invention, by the reset detection computing unit that arranges carried out to reset signal to be verified the resets entry-into-force time and cancel time, retention time and calculate with specifying the parameters such as whether clock synchronous, and determine final simulation result by reset successively judging unit and transcription comparison's unit according to expected result and result of calculation, make all free record of all events, facilitate sequencing and Time To Event between inspection event, and the wave file preserving emulation can not be needed.Thus, solve complicated multi-clock zone SOC sampling classic method at substantial workload in prior art and the technical matters of bringing manual detection to slip up.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize instructions of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (5)
1. the reset signal testing circuit of a SOC, one reset signal to be verified is connected with the input end of described reset signal testing circuit with appointment synchronizing clock signals, described reset signal testing circuit comprises timing unit, for the generation time information when described reset signal testing circuit works; It is characterized in that, also comprise:
Configuration information storage unit, for prestoring configuration information, described configuration information comprises rising edge or negative edge effective information, the retention time requires information, reset between coming into force and cancelling precedence relationship requirement;
Expected result storage unit, for prestoring expectation file, described expectation file comprises the reset entry-into-force time and cancels the time;
High frequency clock generation unit, for generation of high frequency clock signal;
First reset signal judging unit, for judging whether reset signal to be verified occurs rising edge and/or negative edge according to described high frequency clock signal, and origination point information corresponding when determining to occur rising edge and/or negative edge;
Second reset signal judging unit, for producing according to the appointment synchronous clock of described input and the origination point information of the rising edge useful signal determined;
Reset detection computing unit, the temporal information produced for corresponding origination point information when the appearance rising edge determined according to described first reset signal judging unit and/or negative edge and described timing unit calculates and resets the entry-into-force time and cancel the time, according to reset entry-into-force time of described calculating with cancel the time, the origination point information of the rising edge useful signal that the configuration information stored in described configuration information storage unit and described second reset signal judging unit are determined judges whether the reset retention time of described reset signal to be verified meets preset value, and judge whether cancelling of described reset signal to be verified be synchronous with described synchronous clock of specifying,
Detection record unit, for storing the result of calculation of described reset detection computing unit;
Reset successively judging unit, for judging that according to entry-into-force time of configuration information and twice reset and the time of cancelling entry-into-force time between twice reset successively and cancel the precedence relationship successively whether meeting configuration; And
Transcription comparison's unit, for being undertaken contrasting to export automatic the result by the result of calculation stored in the expectation file stored in described expected result storage unit and described detection record unit according to the described judged result resetting priority judging unit.
2. the reset signal testing circuit of SOC as claimed in claim 1, it is characterized in that, described first reset signal judging unit comprises rising edge judge module and negative edge judge module, and described rising edge judge module and negative edge judge module include first order register, second level register and determining device;
The high frequency clock signal that the first order register of described rising edge judge module utilizes high frequency clock generation unit to produce agitates described reset signal to be verified for twice, and when the output valve of the first order register of described rising edge judge module be output valve that is high, second level register is low, rising edge appears in determining device determination reset signal;
The high frequency clock signal that the first order register of described negative edge judge module utilizes high frequency clock generation unit to produce agitates described reset signal to be verified for twice, and when the output valve of the first order register of described negative edge judge module be output valve that is low, second level register is high, negative edge appears in determining device determination reset signal.
3. the reset signal testing circuit of SOC as claimed in claim 2, is characterized in that, described reset signal testing circuit also comprises the reset entry-into-force time and cancels time memory cell, and described reset detection computing unit comprises:
Reset comes into force and cancels judge module, the configuration information stored in the negative edge origination point information determined for rising edge origination point information, the negative edge judge module determined according to described rising edge judge module, described configuration information storage unit judges reset entry-into-force time and the time of cancelling, and result of calculation is sent to described the resets entry-into-force time and cancels time memory cell, store in reset priority judging unit and detection record unit;
Reset retention time checking module, for reset entry-into-force time of obtaining in time memory cell according to described reset entry-into-force time and cancelling with cancel the configuration information stored in time and described configuration information storage unit and judge whether the described reset retention time meets preset value, and result of calculation is sent to the storage of described detection record unit; And
Synchronous reset checking module, for the origination point information of rising edge useful signal determined according to described second reset signal judging unit and from the described reset entry-into-force time with cancel the reset time of cancelling obtained time memory cell and judge whether cancelling of reset signal be synchronous with appointment synchronous clock, and judged result is sent to the storage of described detection record unit.
4. the reset signal testing circuit of SOC as claimed in claim 3, it is characterized in that, described second reset signal judging unit is rising edge judging unit.
5. the reset signal testing circuit of SOC as claimed in claim 3, it is characterized in that, described transcription comparison's unit according to the result of calculation stored in described detection record unit judge whether to reset the retention time do not meet information, reset signal to be verified and specify the asynchronous information of clock or and other reset between the ungratified information of precedence relationship occur, and when determining that the current result exported is mistake; When determining not occur, described expectation file and described result of calculation are contrasted, when determining that described expectation file is consistent with described result of calculation, Output rusults is correct for emulating, and when determining described expectation file and described result of calculation is inconsistent, Output rusults is dummy error.
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| CN201410009276.6A CN103729278B (en) | 2014-01-09 | 2014-01-09 | SOC reset signal detection circuit |
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| CN201410009276.6A CN103729278B (en) | 2014-01-09 | 2014-01-09 | SOC reset signal detection circuit |
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| CN103729278B true CN103729278B (en) | 2015-04-01 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201859389U (en) * | 2010-05-12 | 2011-06-08 | 华为技术有限公司 | Reset management chip and reset system |
| CN103365757A (en) * | 2013-07-29 | 2013-10-23 | 浙江中控技术股份有限公司 | Clock detecting method and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7010713B2 (en) * | 2002-12-19 | 2006-03-07 | Mosaid Technologies, Inc. | Synchronization circuit and method with transparent latches |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201859389U (en) * | 2010-05-12 | 2011-06-08 | 华为技术有限公司 | Reset management chip and reset system |
| CN103365757A (en) * | 2013-07-29 | 2013-10-23 | 浙江中控技术股份有限公司 | Clock detecting method and device |
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