CN201859389U - Reset management chip and reset system - Google Patents
Reset management chip and reset system Download PDFInfo
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- CN201859389U CN201859389U CN2010201941762U CN201020194176U CN201859389U CN 201859389 U CN201859389 U CN 201859389U CN 2010201941762 U CN2010201941762 U CN 2010201941762U CN 201020194176 U CN201020194176 U CN 201020194176U CN 201859389 U CN201859389 U CN 201859389U
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- resets
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Abstract
The utility model discloses a reset management chip and a reset system and belongs to the field of electronic communication. The reset management chip comprises a control module, a detection module, a delay reset module, a monitoring module and a basic input output system (BIOS) module, wherein the control module is respectively connected with the detection module, the delay reset module, the monitoring module and the BIOS module. The reset system comprises the reset management chip and a host system which are connected. By using the utility model, the conciseness of a single board can be improved, the power consumption can be reduced and the reliability and the manufacturability of the reset circuit can be improved.
Description
Technical field
The utility model relates to electronic communication field, particularly a kind of managing chip and resetting system of resetting.
Background technology
In resetting system, reset circuit is indispensable part.In the high resetting system of reliability requirement, require reset circuit to have multiple function, comprise functions such as time-delay reset, watchdog circuit and active and standby BIOS (Basic Input Output System, Basic Input or Output System (BIOS)) control.
Wherein, a plurality of discrete devices are serially connected the function that can realize time-delay reset, FPGA (Field-Programmable Gate Array, field programmable gate array) and watchdog circuit are combined the function that can realize active and standby BIOS control.By a plurality of discrete devices, FPGA and watchdog circuit are serially connected, form reset circuit at present, thereby make reset circuit have the function of time-delay reset, watchdog circuit and active and standby BIOS control.
But, present reset circuit is formed by a plurality of parts serial connections usually, and therefore the veneer of integrated reset circuit is higher than complexity and power consumption.And if certain parts breaks down, then whole reset circuit also breaks down thereupon, and therefore, the reliability of existing reset circuit is lower.
The utility model content
In order to improve the terseness of veneer, reduce board power consumption and improve the reliability of reset circuit, the utility model provides a kind of managing chip and resetting system of resetting.Described technical scheme is as follows:
A kind of managing chip that resets comprises: control module, detection module, time-delay reset module, monitoring module and BIOS module; Described control module links to each other with described detection module, described time-delay reset module, described monitoring module and described BIOS module respectively;
Described detection module is used to detect each external reset source, sends reset request if detect the external reset source, then described reset request is sent to described control module;
Described monitoring module is used for after the monitoring notice that receives described control module, begins real-time monitoring host computer system, takes place unusually if monitor out described host computer system, then sends reset request to described control module;
Described control module, if when being used for receiving the reset request from described monitoring module, transmit described reset request and be notified to described BIOS module for described time-delay reset module and transmission control, after described host computer system resets end, send described monitoring and be notified to described monitoring module; If when receiving the reset request from described detection module, transmit described reset request and give described time-delay reset module;
Described time-delay reset module is used to receive the reset request from described control module, and host computer system resetted after the time-delay very first time;
Described BIOS module is used to receive the control notice from described control module, and after described host computer system resets, controls described host computer system and start.
A kind of resetting system is characterized in that, described resetting system comprises host computer system and the described managing chip that resets; The described managing chip that resets directly links to each other with described host computer system;
A kind of resetting system, described resetting system comprises reset managing chip and host computer system; The described managing chip that resets directly links to each other with described host computer system;
The described managing chip that resets is used for when described host computer system is resetted, and sends look-at-me to described host computer system, sends reset signal after the wait very first time to described host computer system; The described host computer system of monitoring takes place then again described host computer system to be resetted unusually if monitor out described host computer system, and after described host computer system resets, controls described host computer system and start in real time;
Described host computer system is used for when receiving described look-at-me, interrupts and stores the handling procedure that all are moving, and when receiving described reset signal, self is resetted; Unusually then after resetting and under the control of the described managing chip that resets, begin to start if self take place.
Realize the function of time-delay reset by detection module and time-delay reset module, realize the function of watchdog circuit by monitoring module, realize the function of active and standby BIOS control by the BIOS module, thereby the function of time-delay reset, watchdog circuit and active and standby BIOS control all is integrated in the managing chip that resets, so, just not needing to be connected in series a plurality of parts realizes above-mentioned all functions in veneer, has improved the terseness of veneer, has improved the reliability and the manufacturability of reset circuit and has reduced power consumption.
Description of drawings
Fig. 1 is first kind of managing chip synoptic diagram that resets that the utility model embodiment 1 provides;
Fig. 2 is second kind of managing chip synoptic diagram that resets that the utility model embodiment 1 provides;
Fig. 3 is the external reset source and the managing chip connection diagram that resets that the utility model embodiment 1 provides;
Fig. 4 is first kind of resetting system synoptic diagram that the utility model embodiment 2 provides;
Fig. 5 is second kind of resetting system synoptic diagram that the utility model embodiment 2 provides.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, the utility model embodiment is described in further detail below in conjunction with accompanying drawing.
As shown in Figure 1, the utility model embodiment provides a kind of managing chip that resets, comprise: control module 11, detection module 12, monitoring module 13, time-delay reset module 14 and BIOS module 15, wherein, control module 11 links to each other with detection module 12, monitoring module 13, time-delay reset module 14 and BIOS module 15 respectively;
If control module 11 when being used for receiving reset request from monitoring module 13, being transmitted this reset request and is given time-delay reset module 14 and send control and be notified to BIOS module 15, when host computer system reset finish after, send monitoring and be notified to monitoring module 13; If when receiving the reset request from detection module 12, transmit this reset request and give time-delay reset module 14;
Time-delay reset module 14 is used to receive the reset request from control module 11, and host computer system resetted after the time-delay very first time;
Wherein, monitoring module 13 can be watchdog module, and it comprises the timing unit and first transmitting element; Wherein, timing unit links to each other with first transmitting element;
Timing unit, be used for when receiving from the monitoring of control module 11 notice, pick up counting, if the time of timing is in the second default time, receive clear dog signal, then restart timing, if the time of timing is in second time from host computer system, do not receive dog signal clearly, then judge host computer system and take place unusual;
First transmitting element is used for judging host computer system when timing unit and takes place when unusual, sends reset request to control module 11;
Wherein, if host computer system under normal circumstances, host computer system sends clear dog signal every one-period to the managing chip that resets, and this clear dog signal is used to empty the time of timing unit timing; If host computer system takes place unusual, host computer system can stop to send clear dog signal.
Wherein, time-delay reset module 14 comprises interrupt location and reset unit; Wherein, interrupt location links to each other with reset unit;
Interrupt location is used to receive the reset request from control module 11, sends look-at-me to host computer system;
Reset unit is used for after beginning to wait for the very first time, sending reset signal to host computer system when interrupting unit transmission look-at-me.
Wherein, the user can be provided with the size of the very first time as required, usually the size of the very first time is arranged to 200ms.When the interruption unit receives reset request, the look-at-me of Fa Songing is to host computer system immediately, after host computer system receives look-at-me, interrupt also preserving the handling procedure that is moving, send the reset signal of the host computer system that is used to reset after reset unit is waited for the default very first time more then again.
Wherein, after reset unit sends reset signal, behind the T that waits for a period of time again, the host computer system end that just resets, therefore, control module 11 is after transmitting reset request and giving time-delay reset module 13, after waiting for the very first time and time T again, judge the host computer system end that resets.
Wherein, BIOS module 15 comprises the judging unit and second transmitting element; Wherein, judging unit links to each other with second transmitting element;
Judging unit is used for receiving the control notice, judges that the current signal that sends to host computer system of second transmitting element is that main BIOS control signal still is equipped with the BIOS control signal;
Second transmitting element is main BIOS control signal if be used for the result of judgment unit judges, then sends to host computer system again to be equipped with the BIOS control signal, should be equipped with the BIOS control signal and be used for starting from being equipped with BIOS after the main control system system reset; If the result of judgment unit judges then sends main BIOS control signal to host computer system again for being equipped with the BIOS control signal, this main BIOS control signal is used for starting from main BIOS after the main control system system reset;
Wherein, unusual if host computer system takes place, the managing chip that then resets resets to host computer system, and the back main control system system that resets is from main BIOS or be equipped with the BIOS and start.
Further, as shown in Figure 2, this managing chip that resets also comprises memory module 16; Wherein, control module 11 also links to each other with memory module 16;
Correspondingly, detection module 12 also is used for obtaining this external reset source when detecting external reset source transmission reset request, and this external reset source is sent to control module 11;
Wherein, as shown in Figure 3, each external reset source all links to each other with a pin on the managing chip that resets, therefore, and can the corresponding external reset source of each pin of predefined.So, detection module 12 detects each external reset source from each pin that connects the external reset source, when detect the reset request that the external reset source sends from certain pin, directly obtain this pin, map out the external reset source of this pin correspondence according to this pin.
Further, control module 11 also is used for when receiving reset request, obtains reset time and is stored in the memory module 16;
Further, detection module 11 also is used to detect power supply, when detecting power supply power-fail, sends power down and is notified to control module 11;
Wherein, control module 11 can be controller, when control module 11 receives reset request, obtains the current time, and with the current time as reset time; When power down took place, control module 11 was obtained the current time, and with the current time as the power down time.
Wherein, the management chip internal that resets also has a clock, and this clock links to each other with control module 11, and the current time can be provided, and this clock can be oscillator; The management chip exterior that resets also has a standby power supply, and when power down took place, this standby power supply can be managed chip for reset transistor power supply is provided, and obtained and store the power down time for the control module 11 in the managing chip that resets, and this standby power supply can be capacitor.
Further, as shown in Figure 2, the managing chip that resets also comprises communication module 17;
Wherein, if operational order is a reading order, correspondingly,
Further, communication module 17 also is used to receive the information that control module 11 sends, and the information that receives is transmitted to host computer system;
Wherein, order is set if operational order is main BIOS, correspondingly,
Judging unit in the BIOS module 15, the main BIOS that also is used to receive from control module 11 is provided with order, whether the signal of judging the current transmission of second transmitting element in the BIOS module 15 is main BIOS control signal, if not, second transmitting element then is set and sends main BIOS control signal to host computer system again;
Wherein, after the normal startup of host computer system, host computer system also sends main BIOS to the managing chip that resets order is set; When host computer system is normal start after, the main BIOS control signal that second transmitting element sends to host computer system can the main control system system under normal condition from main BIOS space reading of content.
Wherein, if operational order is a pause command, correspondingly,
Wherein, the user is provided with the size of the 3rd time as required, and for example, second time that can be provided with is 30 seconds.
Wherein, host computer system is under normal condition, when the host computer system invoking block, host computer system can stop to send clear dog signal to the managing chip that resets, the time of calling for needs is less than or equal to the program block in the cycle that sends clear dog signal, host computer system does not need to send pause command to the managing chip that resets when calling these program blocks; The time of calling for needs, host computer system needed to send pause command to the managing chip that resets when calling these program blocks greater than the program block in the cycle that sends clear dog signal.
Wherein, if operational order is a corrective command, this corrective command carries the current time;
Correspondingly,
Wherein, memory module 16 can be nonvolatile memory, and for example, memory module 16 can be EPROM (Erasable Programmable ROM, erasable programmable ROM).
In embodiments of the present invention, realize the function of time-delay reset by detection module and time-delay reset module, realize the function of watchdog circuit by monitoring module, realize the function of reset source record and power down record by detection module and control module, realize the function of active and standby BIOS control by the BIOS module, with time-delay reset, the reset source record, watchdog circuit, the function of power down record and active and standby BIOS control all is integrated in the managing chip that resets, so, just not needing to be connected in series a plurality of parts realizes above-mentioned all functions in veneer, improved the terseness of veneer, improve the reliability and the manufacturability of reset circuit and reduced power consumption, in addition, make resetting system have the function of reset source record and power down record.
As shown in Figure 4, the embodiment of the invention provides a kind of resetting system, and this resetting system comprises reset managing chip 1 and host computer system 2; Wherein, the managing chip 1 that resets directly links to each other with host computer system 2;
Managing chip 1 resets, be used for when host computer system 2 is resetted, send look-at-me to host computer system 2, send reset signal after waiting for the very first time to host computer system 2, monitoring host computer system 2 takes place then again host computer system 2 to be resetted unusually if monitor out host computer system 2 in real time, and after host computer system 2 resetted, main control system system 2 started;
Wherein, as shown in Figure 5, host computer system 2 under normal circumstances periodically sends clear dog signal to the managing chip 1 that resets, and when generation is unusual, stops to send clear dog signal to the managing chip 1 that resets; The clear dog signal that the managing chip 1 that resets receives from host computer system is according to the real-time monitoring host computer of this clear dog signal system 2.
Wherein, the managing chip 1 that resets directly links to each other with the external reset source, and the managing chip 1 that resets can detect each external reset source, if detect external reset source 1 when sending reset request, then host computer system 2 is resetted; Also have an internal reset source in the managing chip 1 that resets, take place when unusual when the managing chip 1 that resets detects host computer system, the internal reset source produces reset request and the managing chip 1 that resets begins host computer system 2 is resetted.
Wherein, when the request of external reset source resetted, the managing chip 1 that resets can obtain and store this external reset source, can also obtain and store reset time; When the request of internal reset source resetted, the managing chip 1 that resets can obtain and store this internal reset source, can also obtain and store reset time.
Wherein, the managing chip 1 that resets can also detect the power supply of resetting system, when detecting power supply generation power down, then obtains and stores the power down time.
Wherein, the managing chip 1 that resets directly links to each other with reset pin with the interrupt pin of host computer system 2, host computer system 2 can also be communicated by letter with the managing chip 1 that resets by communication interface, and this communication interface can be I2C (Inter-Integrated Circuit, twin wire universal serial bus) interface.
Wherein, as shown in Figure 5, the managing chip 1 that resets sends to look-at-me on the interrupt pin of host computer system 2, and host computer system 2 receives look-at-me by the interrupt pin of self; The managing chip 1 that resets sends to the reset pin of host computer system 2 with reset signal, and host computer system 2 receives reset signal by reset pin.
Wherein, after host computer system 2 resetted, host computer system 2 can also be given the managing chip 1 that resets by communication interface transmit operation order, and this operational order comprises that reading order, main BIOS are provided with order, pause command and corrective command.
Wherein, if operational order is a reading order, correspondingly,
The managing chip 1 that resets also is used to receive reading order, and reads self canned data, and this information is sent to host computer system 2; Host computer system 2 receives the information that the managing chip 1 that resets sends by communication interface, and this information can comprise external reset source, internal reset source, reset time and/or power down time etc.
In embodiments of the present invention, the function of time-delay reset, reset source record, watchdog circuit, power down record and active and standby BIOS control all is integrated in the managing chip that resets, so, just not needing to be connected in series a plurality of parts realizes above-mentioned all functions in veneer, improved the terseness of veneer, improved the reliability of reset circuit and reduced power consumption, and made resetting system have the function of reset source record and power down record.
The above only is preferred embodiment of the present utility model, and is in order to restriction the utility model, not all within spirit of the present utility model and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (9)
1. the managing chip that resets is characterized in that, comprising: control module, detection module, time-delay reset module, monitoring module and BIOS module; Described control module links to each other with described detection module, described time-delay reset module, described monitoring module and described BIOS module respectively.
2. the managing chip that resets as claimed in claim 1 is characterized in that, described time-delay reset module comprises interrupt location and reset unit; Described interrupt location links to each other with described reset unit.
3. the managing chip that resets as claimed in claim 1 is characterized in that, described monitoring module comprises the timing unit and first transmitting element; Described timing unit links to each other with described first transmitting element.
4. the method for claim 1 is characterized in that, described BIOS module comprises the judging unit and second transmitting element; Described judging unit links to each other with described second transmitting element.
5. the managing chip that resets as claimed in claim 1 is characterized in that, also comprises memory module; Correspondingly, described control module also links to each other with described memory module.
6. the managing chip that resets as claimed in claim 1 is characterized in that, also comprises: communication module; Described communication module links to each other with described control module.
7. the managing chip that resets as claimed in claim 1 is characterized in that, the described managing chip that resets also comprises clock,
Described control module also links to each other with described clock.
8. a resetting system is characterized in that, described resetting system comprises host computer system and the managing chip that resets as described in arbitrary as claim 1 to 7; The described managing chip that resets directly links to each other with described host computer system.
9. resetting system as claimed in claim 8 is characterized in that, the described managing chip that resets directly links to each other with reset pin with the interrupt pin of described host computer system; Described host computer system also communicates by self communication interface and the described managing chip that resets.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201941762U CN201859389U (en) | 2010-05-12 | 2010-05-12 | Reset management chip and reset system |
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| CN2010201941762U CN201859389U (en) | 2010-05-12 | 2010-05-12 | Reset management chip and reset system |
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| CN201859389U true CN201859389U (en) | 2011-06-08 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508533A (en) * | 2011-09-21 | 2012-06-20 | 迈普通信技术股份有限公司 | Reset control device and method |
| CN103166612A (en) * | 2011-12-15 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Self-check handling circuit structure in reset control circuit and reset control circuit device |
| CN103728516A (en) * | 2014-01-09 | 2014-04-16 | 福州瑞芯微电子有限公司 | Soc chip clock detection circuit |
| CN103729278A (en) * | 2014-01-09 | 2014-04-16 | 福州瑞芯微电子有限公司 | SOC reset signal detection circuit |
| CN104461825A (en) * | 2014-12-04 | 2015-03-25 | 深圳市亿威尔信息技术股份有限公司 | Bypass processing device and method for responding power-on, power-failure and time-out incidents of system |
| CN104657235A (en) * | 2015-03-04 | 2015-05-27 | 广东威创视讯科技股份有限公司 | Self recovery system and state detecting method of self recovery system |
| CN113110966A (en) * | 2021-03-12 | 2021-07-13 | 广东纳睿雷达科技股份有限公司 | System upgrade monitoring management method, embedded system and storage medium |
| CN117009128A (en) * | 2023-09-14 | 2023-11-07 | 飞腾信息技术有限公司 | Error reporting method and computer system |
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2010
- 2010-05-12 CN CN2010201941762U patent/CN201859389U/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508533B (en) * | 2011-09-21 | 2014-07-09 | 迈普通信技术股份有限公司 | Reset control device and method |
| CN102508533A (en) * | 2011-09-21 | 2012-06-20 | 迈普通信技术股份有限公司 | Reset control device and method |
| CN103166612A (en) * | 2011-12-15 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Self-check handling circuit structure in reset control circuit and reset control circuit device |
| CN103166612B (en) * | 2011-12-15 | 2016-03-30 | 无锡华润矽科微电子有限公司 | Self-inspection treatment circuit structure in reset control circuit and reset control circuit device |
| CN103729278B (en) * | 2014-01-09 | 2015-04-01 | 福州瑞芯微电子有限公司 | SOC reset signal detection circuit |
| CN103729278A (en) * | 2014-01-09 | 2014-04-16 | 福州瑞芯微电子有限公司 | SOC reset signal detection circuit |
| CN103728516A (en) * | 2014-01-09 | 2014-04-16 | 福州瑞芯微电子有限公司 | Soc chip clock detection circuit |
| CN103728516B (en) * | 2014-01-09 | 2016-05-11 | 福州瑞芯微电子股份有限公司 | Soc chip clock detection circuit |
| CN104461825A (en) * | 2014-12-04 | 2015-03-25 | 深圳市亿威尔信息技术股份有限公司 | Bypass processing device and method for responding power-on, power-failure and time-out incidents of system |
| CN104657235A (en) * | 2015-03-04 | 2015-05-27 | 广东威创视讯科技股份有限公司 | Self recovery system and state detecting method of self recovery system |
| CN113110966A (en) * | 2021-03-12 | 2021-07-13 | 广东纳睿雷达科技股份有限公司 | System upgrade monitoring management method, embedded system and storage medium |
| CN117009128A (en) * | 2023-09-14 | 2023-11-07 | 飞腾信息技术有限公司 | Error reporting method and computer system |
| CN117009128B (en) * | 2023-09-14 | 2023-12-22 | 飞腾信息技术有限公司 | Error reporting method and computer system |
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