CN103166612A - Self-check handling circuit structure in reset control circuit and reset control circuit device - Google Patents
Self-check handling circuit structure in reset control circuit and reset control circuit device Download PDFInfo
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- CN103166612A CN103166612A CN201110419646XA CN201110419646A CN103166612A CN 103166612 A CN103166612 A CN 103166612A CN 201110419646X A CN201110419646X A CN 201110419646XA CN 201110419646 A CN201110419646 A CN 201110419646A CN 103166612 A CN103166612 A CN 103166612A
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Abstract
The invention relates to a self-check handling circuit structure applied in a reset control circuit. The self-check handling circuit structure comprises a self-check information storage module, a self-check information capture module, a self-check information judgment module and a self-check information response module. According to the self-check handling circuit structure applied in the reset control circuit and a reset control circuit device with the above structure, self-check information can be loaded in correctly, thus the effective operation of system key nodes is guaranteed, and the reliability of system reset is guaranteed effectively. Meanwhile, the circuit structure can monitor the state of the self-check information in real time in normal operation process and make corresponding responding movement to a system accordingly, and thus not only is the reliability of reset (the self-check information being loaded in correctly) ensured again. Besides, due to the fact that the self-check information is monitored in real time, when external disturbance enables the self-check information to be in error, the self-check handling module responds accordingly to reset the system again, and thus the reliability of system operation is improved greatly. The self-check handling circuit structure in the reset control circuit and the reset control circuit device have the advantages of being simple in structure, practical, stable in working performance and wide in application range.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, particularly reset control technology field of integrated circuit, specifically refer to a kind of self check treatment circuit structure and reset control circuit device that is applied to reset control circuit.
Background technology
Reset circuit is design commonly used in integrated circuit, its function is after system detects effective reset signal, and the homing action to system carries out the overall situation comprises resetting of system register, the systemic presupposition value is written into, and program pointer points to the execution of a plurality of key node actions such as reseting vector.For chip design, due to varying of peripheral applications environment, actual operating conditions is complicated and simple different, require circuit that higher reliability is arranged, the particularly design of reset circuit, if system is just unreliable in initial reseting procedure, so can't assurance system's normal operation.
In the design of reset circuit, the common pre-hot counter of drawing-in system in prior art, the assurance system completes homing action after counting down to certain numerical value.But this design may cause counting of abnormal running under the environment for use of strong interference, makes system withdraw from advance reset mode, or in the situation that do not have the everything of completion system in resetting just to withdraw from reset mode, such resetting is insecure.
Therefore, aspect how prior art guarantees that all key nodes of reseting procedure are all effectively carried out, Shortcomings.
Summary of the invention
The objective of the invention is to have overcome above-mentioned shortcoming of the prior art, provide a kind of reliability that can realize the Real Time Monitoring to reseting procedure, effectively improve system reset, simple and practical, stable work in work, the scope of application comparatively to be widely used in self check treatment circuit structure and the reset control circuit device of reset control circuit.
In order to realize above-mentioned purpose, self check treatment circuit structure and the reset control circuit device that is applied to reset control circuit of the present invention has following formation:
This is applied to the self check treatment circuit structure in reset control circuit, and its main feature is that described circuit structure comprises:
The self check information storage module is used for storage and the self check information that resets relevant;
Self check information capture module is connected with described self check information storage module, is used for reading the self check information of this self check information storage module;
The self check signal judgement module is connected with described self check information capture module, is used for judging whether the self check information that reads is correct; And
Self check information response module is connected with described self check signal judgement module, is used for the formed result of this self check signal judgement module of response.
This self check information storage module that is applied in self check treatment circuit structure in reset control circuit comprises:
The self check information memory cell is stored and the self check information that resets relevant;
Address decoding circuitry is connected with described self check information memory cell, takes out the self check information of designated storage location according to address signal.
This self check information capture module that is applied in self check treatment circuit structure in reset control circuit comprises:
The address generating unit records the triggering signal sequence and forms corresponding address information, and this address information is passed to described self check information storage module;
Data buffer storage unit is connected with described self check information storage module, carries out the buffer memory of data message.
This self check signal judgement module that is applied in self check treatment circuit structure in reset control circuit comprises:
The decision logic circuit unit is connected with described self check information capture module, the self check information after catching is carried out the logic judgement process, and form the real-time judge result;
Data buffer storage unit is responsible for recording the real-time judge result on decision node, form the fixed point judged result, and this judged result is delivered to described self check information response module.
This self check information response module that is applied in self check treatment circuit structure in reset control circuit comprises:
Triggering signal is selected module, and it is fixed point judged result or real-time judge result that the current state of system of controlling according to reset control circuit is selected triggering signal;
The reset detection module detects effective reset signal, triggers the completion system response that resets.
This has the reset control circuit device of above-mentioned circuit structure, and its main feature is, also has multiple control bit circuit in described device, and described reset control circuit comprises:
The reset detection module is responsible for extracting the effective reset signal in the system that controls;
The reset procedure processing module, all be connected with described self check information storage module, self check information capture module, self check signal judgement module, self check information response module, receive the effective reset signal of described reset detection module output, complete reset procedure, and export response message after reset procedure finishes;
The end module that resets receives the response message of described reset procedure processing module, and finishes the whole process that resets.
The self check treatment circuit structure that is applied to reset control circuit and the reset control circuit device of this invention have been adopted, existence due to self check treatment circuit structure, system can't work before correctly being written into default self check information, and being written into to synchronize with key node place action in system reset and carrying out of self check information, therefore self check information correctly be written into the very big effective operation that guarantees the system core node, thereby effectively guaranteed the reliability of system reset; Simultaneously, this circuit structure is in normal course of operation, meeting Real-Time Monitoring self check information state, and accordingly system is carried out corresponding response action, guaranteed again that not only the reliability (self check information correctly is written into) that resets is simultaneously due to the Real-Time Monitoring of self check information, when having made self check information, external interference makes mistakes, the self check processing module can be made to this response, system is resetted again, greatly promoted system's reliability of operation, simple and practical, stable work in work, the scope of application are comparatively extensive.
Description of drawings
Fig. 1 is the circuit function module schematic diagram with reset control circuit device of self check treatment circuit structure of the present invention.
Fig. 2 is the self check information capture operation principle schematic diagram in the reset control circuit device with self check treatment circuit structure of the present invention.
Fig. 3 is the self check information judgement operation principle schematic diagram in the reset control circuit device with self check treatment circuit structure of the present invention.
Fig. 4 is the self check information response operation principle schematic diagram in the reset control circuit device with self check treatment circuit structure of the present invention.
Embodiment
In order more clearly to understand technology contents of the present invention, describe in detail especially exemplified by following examples.
See also Fig. 1 to shown in Figure 4, this is applied to the self check treatment circuit structure in reset control circuit, and wherein, described circuit structure comprises:
(1) self check information storage module is used for storage and the self check information that resets relevant; This self check information storage module comprises:
● the self check information memory cell, store and the self check information that resets relevant;
● address decoding circuitry, be connected with described self check information memory cell, take out the self check information of designated storage location according to address signal;
(2) self check information capture module is connected with described self check information storage module, is used for reading the self check information of this self check information storage module; This self check information capture module comprises:
● the address generating unit, record the triggering signal sequence and form corresponding address information, and this address information is passed to described self check information storage module;
● data buffer storage unit, be connected with described self check information storage module, carry out the buffer memory of data message;
(3) self check signal judgement module is connected with described self check information capture module, is used for judging whether the self check information that reads is correct; This self check signal judgement module comprises:
● the decision logic circuit unit, be connected with described self check information capture module, the self check information after catching is carried out the logic judgement process, and form the real-time judge result;
● data buffer storage unit, be responsible for recording the real-time judge result on decision node, form the fixed point judged result, and this judged result is delivered to described self check information response module;
(4) self check information response module, be connected with described self check signal judgement module, is used for the formed result of this self check signal judgement module of response, and this self check information response module comprises:
● triggering signal is selected module, and it is fixed point judged result or real-time judge result that the current state of system of controlling according to reset control circuit is selected triggering signal;
● the reset detection module, detect effective reset signal, trigger the completion system response that resets.
This has the reset control circuit device of above-mentioned circuit structure, wherein also has multiple control bit circuit, and described reset control circuit comprises:
● the reset detection module, be responsible for extracting the effective reset signal in the system that controls;
● the reset procedure processing module, all be connected with described self check information storage module, self check information capture module, self check signal judgement module, self check information response module, receive the effective reset signal of described reset detection module output, complete reset procedure, and export response message after reset procedure finishes;
● the end module that resets receives the response message of described reset procedure processing module, and finishes the whole process that resets.
In the middle of reality was used, self check treatment circuit provided by the present invention comprised:
(1) self check information storage module, be used for storage and the self check information that resets relevant, memory module can be memory element such as the memory elements such as MASKROM, EPPROM, FLASH or even fuse in system, the memory capacity of memory element is at least 2 bits or two more than bits, actual design quantity can be decided according to the key node quantity in system resource configuration and reset procedure, self check information is more, and improved effect is better;
(2) self check information capture module, be used for reading the self check information of memory module, comprise readout sequence generation module and information temporary storage module, the occurrence time of its readout sequence be in the system reset process, be specially with the access of system core nodal information and synchronize, complete simultaneously the temporary of self check information, use for follow-up judge module.The theory that arranges of catching number of nodes is no less than key node number in the system reset process;
(3) self check signal judgement module is used for judging whether the self check information that reads is correct; The judgement of self check information can act on whole reseting period, also can act on system's normal work period.When acting on reseting period, after its judgement was the self check Information Read-Out opportunity, before reset procedure finishes, and the judging point that can arrange more than 1 or 1 was realized judging more reliably.When acting on normal work period, its judgement is real-time (judged result is according to the self check information real-time change of catching).
(4) self check information response module is used for the formed result of response judge module.Its response signal can affect system reset process or normal operation process.In reseting procedure, the self check respond module can realize according to the result of judgement system is again resetted or do not affect two kinds of results of system reset when system; When system is in the normal operation process, the self check respond module can realize according to the result of judgement again resetting or two kinds of results of not impact system's normal operation process on system.
Without any extremely, the self check processing module does not affect system process in the system reset process;
Occur abnormal in the system reset process, cause that certain key node does not effectively read, the failure of self check acquisition of information, the self check responding system will be formed with the effect system reset signal, restart reset procedure, until get the default self check information of appointment, system just can complete reset procedure, enters normal operating conditions;
In normal procedure, judged result will be according to the self check information real-time change of catching, respond module will be according to judged result real-time update system mode, if the self check information of catching in system's course of normal operation is correct and not variation, system keeps normal operating condition;
Reset as system exception, directly skipped the process that is written into of self check information, enter normal mode of operation, system will return reset procedure immediately this moment;
Be subject to abnormal the interference as the self check information of catching in course of normal operation variation has occured, system will return reset procedure immediately.
See also shown in Figure 1ly, it comprises for the reset circuit structure of improvement of the present invention:
(1) general reset circuit 104 comprises: reset detection module 101, reset procedure processing module 102 resets and finishes module 103.Reset detection module 101 is responsible for effective reset signal in extraction system, and effective reset signal is passed to reset procedure processing module 102, complete the main process that resets, after reset procedure finishes, the reset procedure processing module will send corresponding information and enter the end module 103 that resets, the end module 103 that resets will finish the whole process that resets according to the information of receiving, system is switched in normal operating conditions.
(2) self check processing module 109 comprises: self check information storage module 105, self check information capture module 106, self check signal judgement module 107, self check information response module 108.In reset procedure, self check information capture module 106 will be obtained self check information opportunity at all system core synchronisation of nodes from self check information storage module 105, and this information is passed to self check signal judgement module 107, self check judge module 107 is completed judgement and the storage of information, the judged result that forms is transferred to self check information response module 108, and self check information response module 108 is made the respective response action according to the state of the judged result of accepting and system.
(3) self check information storage module 105 comprises: address decoding circuitry 110, self check information 111.Address decoding circuitry 110 is responsible for taking out according to address signal the self check information of assigned address.
(4) self check information capture module 106 comprises: module 112, data cache module 113 occur in the address.The trapping module 106 formed information of detection system key node, and this signal is converted into the triggering signal of home address generation module 112, module 112 occurs and records the triggering signal sequence and form corresponding address information in the address, and this address information is passed to self check information storage module 105, by address decoding circuitry 110, take out corresponding self check information 111.Self check information is connected to self check information capture module 106, and the data cache module 113 in trapping module 106 is completed the buffer memory of data, thus the self check information 1～N after being caught, and the self check information after catching is imported the processing of self check signal judgement module again into.
(5) self check signal judgement module 107 comprises: decision logic circuit 115 and data cache module 114.Self check information 1～N after decision logic circuit 115 will be caught carries out the logic judgement and processes formation real-time judge result, data cache module 114 is responsible for recording the real-time judge result on decision node, form the fixed point judged result, difference according to decision node, system can form N real-time judge result and N fixed point judged result, and two groups of sentence read result will transfer to self check information response module 108.
(6) self check information response module 108 comprises: it is fixed point judged result/real-time judge result that triggering signal selects module 116 and reset detection module 101. triggering signals to select module 116 states (reset mode/normal operating conditions) current according to system to select triggering signal, reset detection module 101 is responsible for detecting effective reset signals, triggers the completion system response that resets.
See also shown in Figure 2ly, it is self check information capture principle schematic again.
As shown in Figure 2, in this embodiment, there be N key node in reset procedure, at each key node place, self check information capture module 106 can according to the sequence information of key node, by the address generation module 112 corresponding address informations of formation of inside, and be passed to self check information storage module 105 with this address information, by the address decoding circuitry 110 of inside, take out corresponding self check information 111.Self check information is connected to self check information capture module 106, and the data cache module 113 in trapping module 106 is completed the buffer memory of data, thus the self check information 1～N after being caught.
See also shown in Figure 3ly, it is self check information judgement principle schematic again.
As shown in Figure 3, in this embodiment, self check information 1～N after system will catch delivers to self check signal judgement module 107, self check information 1～N after decision logic circuit 115 will be caught carries out the logic judgement and processes formation real-time judge result, data cache module 114 is responsible for recording the real-time judge result on decision node, form the fixed point judged result, according to the difference of decision node, system can form N real-time judge result and N fixed point judged result
See also shown in Figure 4ly, it is self check information response principle schematic again.
As shown in Figure 4, in this embodiment, system will form two groups of judged results (real-time judge result and fixed point judged result) and deliver to self check information response module 108, and it is fixed point judged result/real-time judge result that triggering signal selects module 116 state (reset mode/normal operating conditions) current according to system to select triggering signal:
When system was in reset mode, triggering signal was selected module 116 gating fixed point judged results;
When system was in normal operating conditions, triggering signal was selected module 116 gating real-time judge results.After reset detection module 101 detected effective reset signal, triggering system resetted.Self check information response module 108 is made following response action according to the state of the judged result of accepting and system:
Reseting procedure is normal, and self check information response module 108 does not affect system's normal procedure;
Reseting procedure abnormal (the self check judged result is abnormal), self check information response module 108 will make system re-execute homing action;
In course of normal operation, self check information is disturbed and changes, and self check information response module 108 will make system re-execute homing action;
Intervention due to the self check processing module, system can't work before correctly being written into default self check information, and being written into to synchronize with key node place action in system reset and carrying out of self check information, therefore correctly being written into of self check information greatly guaranteed that the system core node effectively moves, and has effectively guaranteed the reliability of system reset.In addition in normal course of operation, the degree of makeing mistakes to the self check information that makes in buffer memory greatly when system interference, can not guarantee the reliability of system this moment, and self check information response module will make system re-execute homing action, thereby greatly promote the reliability of system.
Above-mentioned the self check treatment circuit structure that is applied to reset control circuit and reset control circuit device have been adopted, existence due to self check treatment circuit structure, system can't work before correctly being written into default self check information, and being written into to synchronize with key node place action in system reset and carrying out of self check information, therefore self check information correctly be written into the very big effective operation that guarantees the system core node, thereby effectively guaranteed the reliability of system reset; Simultaneously, this circuit structure is in normal course of operation, meeting Real-Time Monitoring self check information state, and accordingly system is carried out corresponding response action, guaranteed again that not only the reliability (self check information correctly is written into) that resets is simultaneously due to the Real-Time Monitoring of self check information, when having made self check information, external interference makes mistakes, the self check processing module can be made to this response, system is resetted again, greatly promoted system's reliability of operation, simple and practical, stable work in work, the scope of application are comparatively extensive.
In this specification, the present invention is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (6)
1. a self check treatment circuit structure that is applied in reset control circuit, is characterized in that, described circuit structure comprises:
The self check information storage module is used for storage and the self check information that resets relevant;
Self check information capture module is connected with described self check information storage module, is used for reading the self check information of this self check information storage module;
The self check signal judgement module is connected with described self check information capture module, is used for judging whether the self check information that reads is correct; And
Self check information response module is connected with described self check signal judgement module, is used for the formed result of this self check signal judgement module of response.
2. the self check treatment circuit structure that is applied in reset control circuit according to claim 1, is characterized in that, described self check information storage module comprises:
The self check information memory cell is stored and the self check information that resets relevant;
Address decoding circuitry is connected with described self check information memory cell, takes out the self check information of designated storage location according to address signal.
3. the self check treatment circuit structure that is applied in reset control circuit according to claim 1, is characterized in that, described self check information capture module comprises:
The address generating unit records the triggering signal sequence and forms corresponding address information, and this address information is passed to described self check information storage module;
Data buffer storage unit is connected with described self check information storage module, carries out the buffer memory of data message.
4. the self check treatment circuit structure that is applied in reset control circuit according to claim 1, is characterized in that, described self check signal judgement module comprises:
The decision logic circuit unit is connected with described self check information capture module, the self check information after catching is carried out the logic judgement process, and form the real-time judge result;
Data buffer storage unit is responsible for recording the real-time judge result on decision node, form the fixed point judged result, and this judged result is delivered to described self check information response module.
5. the self check treatment circuit structure that is applied in reset control circuit according to claim 1, is characterized in that, described self check information response module comprises:
Triggering signal is selected module, and it is fixed point judged result or real-time judge result that the current state of system of controlling according to reset control circuit is selected triggering signal;
The reset detection module detects effective reset signal, triggers the completion system response that resets.
6. the reset control circuit device with circuit structure claimed in claim 1, is characterized in that, also has multiple control bit circuit in described device, and described reset control circuit comprises:
The reset detection module is responsible for extracting the effective reset signal in the system that controls;
The reset procedure processing module, all be connected with described self check information storage module, self check information capture module, self check signal judgement module, self check information response module, receive the effective reset signal of described reset detection module output, complete reset procedure, and export response message after reset procedure finishes;
The end module that resets receives the response message of described reset procedure processing module, and finishes the whole process that resets.
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