CN105068969B - Single particle effect guard system and method for digital signal processing platform framework - Google Patents
Single particle effect guard system and method for digital signal processing platform framework Download PDFInfo
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Abstract
Single particle effect guard system and method for digital signal processing platform framework, it is therefore an objective to solve SEFI (Single Event Upset single event function interrupts) problem of digital signal processing platform under space environment.Organically blending by many kinds of measures of the invention, refinement and the platform architecture for improving the protection of support multi-layer single-particle soft error, detection and recovery technology, the DSP and the detection of FPGA single particle function outage and restoration methods of system are proposed, can effectively slow down the SEFI effects of digital signal processing platform.The present invention can effectively overcome the system single event function interrupt problem of long-time operation on orbit.
Description
Technical field
The present invention relates to a kind of system-level single particle effect guard system for digital signal processing platform framework and side
Method, belong to space communications technique field.
Background technology
At present, in spaceborne digital signal processing platform, due to mainly completing number using extensive SRAM type FPGA and DSP
Word signal processing function, the probability that single particle effect occurs for such product greatly improve.
Recognize from open publication, for current digital information processing system, mainly pass through redundancy, refreshing, error correction and detection
The methods of alleviate the single particle effect of system so that system still is able to normal work in the case where SEU occurs.But work as system
During generation SEFI, the above measure can not also solve, it is necessary to take targetedly SEFI recovery measures, could allow system
Recover normal.
The content of the invention
The purpose of the present invention is：Overcome the deficiencies in the prior art, there is provided a kind of for digital signal processing platform framework
Single particle effect guard system and method, the SEFI problems of system are can solve the problem that, improve the space of digital information processing system
Reliability.
The technical solution adopted by the present invention is：
For the single particle effect guard system of digital signal processing platform framework, including:Fpga chip, dsp chip,
SEFI detections recovery unit, first memory and second memory, SEFI detection recovery units include FPGA state-detections and extensive
Multiple module, DSP state-detections and recovery module, read back check and refresh module, configuration module, house dog, DSP Loading Control moulds
Block and memory control module；
Working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery by fpga chip
Module detects the working condition of fpga chip, if fpga chip is working properly, continues working condition detection, if FPGA cores
Single event function interrupt SEFI occurs for piece, then FPGA state-detections and recovery module send reset signal to fpga chip, make it
Reset reconfigures；
Configuration module is by memory control module controls first memory, the matching somebody with somebody fpga chip from first memory
Put the configuration memory block that program is loaded into fpga chip, read back check and refresh module from the configuration memory block of fpga chip by shape
The value of state register and control register is read out, and is compared with the original value of status register and control register, if
It is identical, then continue retaking of a year or grade detection, if it is different, then passing through to error indication signal to FPGA state-detections and recovery module
Read back check and refresh module carries out configuring memory block refreshing to fpga chip, if state is still abnormal, pass through FPGA states
Detection and recovery module reset to fpga chip to be reconfigured；
Working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery mould by dsp chip
Block detects the working condition of dsp chip, if dsp chip is working properly, judges whether test point information needs to store, if belonging to
Test point to be protected, then test point information is arrived into second memory by store control logic storage, and continue work
Make state-detection, if test point need not be stored, continue to be operated state-detection, if SEFI, DSP occur for dsp chip
State-detection and recovery module send reset signal to dsp chip, make its reset；The test point refers to be used to recover DSP works
Make the location point in the DSP programs at scene；
DSP Loading Controls module is by memory control module controls second memory, by DSP cores from second memory
The configurator of piece is loaded into the configuration memory block of dsp chip；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving instruction for a long time
Signal, watchdog module reset to dsp chip.
It is as follows for the single particle effect means of defence of digital signal processing platform framework, step：
(1) configuration module is by memory control module controls first memory, by fpga chip from first memory
Configurator be loaded into the configuration memory block of fpga chip；DSP Loading Controls module passes through memory control module controls
Two memories, the configurator of dsp chip is loaded into the configuration memory block of dsp chip from second memory；
(2) working state signal is sent to FPGA state-detections and recovery module by fpga chip, FPGA state-detections and
Recovery module detects the working condition of fpga chip, if fpga chip is working properly, continues working condition detection, if
Fpga chip operation irregularity, then it represents that there occurs single event function interrupt SEFI, then FPGA state-detections and recovery module are sent
Reset signal makes its reset reconfigure to fpga chip；
Read back check and refresh module configures memory block by status register and the value of control register from fpga chip
Read out, be compared with the value original value of status register and control register, if identical, continue retaking of a year or grade inspection
Survey, if it is different, then to error indication signal to FPGA state-detections and recovery module, by reading back check and refresh module pair
Fpga chip carries out configuring memory block refreshing, if state is still abnormal, by FPGA state-detections and recovery module to FPGA
Chip reset reconfigures；
(3) working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery by dsp chip
Module detects the working condition of dsp chip, if dsp chip is working properly, judges whether test point information needs to store, if category
In test point to be protected, then test point information is arrived into second memory by store control logic storage, and continue
Working condition detects, if test point need not be stored, continues to be operated state-detection, if dsp chip operation irregularity, table
Show that then DSP state-detections and recovery module transmission reset signal make it to dsp chip there occurs single event function interrupt SEFI
Reset；The test point refer to for recover DSP working sites DSP programs in location point；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving instruction for a long time
Signal, watchdog module reset to dsp chip, complete the protection of the single particle effect.
The working state signal of the fpga chip includes DONE signals, BUSY signals, FAR frame address register value, shape
State register value and control register value.
The step (2) is specially：
(4.1) DONE signals are monitored：Detect whether DONE signals are high level, if DONE signals are high level, perform
Step (4.2)；Otherwise it is assumed that the electrification reset circuit of fpga chip performs step (4.5) there occurs single event function interrupt；
(4.2) BUSY signals are monitored：Detect whether BUSY signals are high level, if BUSY signals are high level, perform step
Suddenly (4.3)；Otherwise it is assumed that fpga chip performs step (4.5) there occurs the single event function interrupt of SELECTMAP interfaces；
(4.3) FAR frame address register is read and write：Before refreshing every time or read back operation is carried out, FAR frame address is deposited
Device first writes the configuration memory block of fpga chip, judges whether the value that retaking of a year or grade goes out is correct, if correctly, continuing step
(4.4)；Otherwise it is assumed that fpga chip performs step (4.5) there occurs the single event function interrupt of SELECTMAP interfaces；
(4.4) status register value and control register value read-write：Pass through retaking of a year or grade status register and control register
Value, if differed with default value, it is believed that there occurs the Global signals SEFI (single-particles of overall signal for fpga chip
Function is interrupted) or POR SEFI (single event function interrupt of electrification reset circuit), perform step (4.5)；
(4.5) SEFI fault recoveries are carried out by resetting to reconfigure or power off to reconfigure.
The step (3) is specially：
(5.1) start house dog, feeding-dog signal is produced in DSP course of normal operation, and monitor the work that dsp chip is sent
Make status signal, if working state signal is expected right value, carry out step (5.2)；Otherwise it is assumed that dsp chip occurs
Single event function interrupt, perform step (5.3)；
(5.2) judge whether test point preservation condition meets, if belonging to test point to be protected, controlled by memory
Module preserves the content of test point to second memory, return to step (5.1) after the completion of storage；Otherwise, direct return to step
(5.1)；The test point to be protected refers to：Need to do in the DSP programs specified by user preservation action position or by
Specified fixed interval does the position of preservation action automatically；
(5.3) the DSP reseting logics in DSP state-detections and recovery module are started, and perform detection point recovers；The inspection
The content that measuring point recovers includes：(1) DSP programs perform scene:Include control register and general register；(2) program performs
Stack；(3) the calculating data acquisition system of program.
The perform detection point recovers：
The recovery of test point detects the DSP state-detections and recovery module in recovery unit by hardware trigger by SEFI
Triggering is interrupted, and is resetted DSP according to interrupt signal, after DSP restartings, automatic guiding, is then performed in a manner of abnormality processing
Test point recovers；In test point recovery process, the information of a test point in DSP programs is read from second memory, will
Information is loaded into register and storehouse, then jumps into the program address specified, and re-executes the program being interrupted.
Compared with the prior art, the invention has the advantages that：
(1) present invention in order to meet digital information processing system space environment adaptive faculty requirement, using detection DONE signals,
The single event function interrupt of the method detecting system of BUSY signals and FAR values and status register value and control register value,
Solve due to SELECTMAP interfaces, POR electrification reset circuits SEFI caused by FPGA power on configuration and refresh failure ask
Topic.
(2) present invention realizes system work(by way of write-back configuration file and test point storage file or system reset
The recovery of energy, substantially reduce and the general of single event function interrupt occurs when digital information processing system is run under space radiation environment
Rate, the anti-single particle ability of lifting system.
Brief description of the drawings
Fig. 1 is the theory diagram of guard system of the present invention；
Fig. 2 is means of defence flow chart of the present invention；
Fig. 3 is the present invention for system FPGA SEFI detections and recovers flow chart；
Fig. 4 is the present invention for system DSP SEFI detections and recovers flow chart.
Embodiment
The invention provides a kind of system-level single particle effect guard system for being adapted to digital signal processing platform and prevent
Maintaining method, the state-detection of system is carried out using SEFI detection recovery units, SEFI occurs for FPGA and DSP if judging, takes extensive
Multiple measure.For FPGA SEFI detections and recovery, FPGA is configured by SEFI detection recovery units, completion, which is matched somebody with somebody, postpones inspection
FPGA DONE signals, BUSY signals, FAR values, status register value and control register value is surveyed, is taken if SEFI occurs
Electricity reconfigures or repositioning method carries out system recovery.For DSP SEFI detections and recovery, recovery unit pair is detected by SEFI
DSP carries out test point preservation, detects whether DSP occurs SEFI by house dog, SEFI does not occur for detection, while preserves detection
Point, when SEFI occurs, it can be reached by recovering test point and go back the purpose of original system.
As shown in figure 1, provided by the present invention for the single particle effect guard system of digital signal processing platform framework, bag
Include:Fpga chip, dsp chip, SEFI detections recovery unit, first memory and second memory, SEFI detection recovery units
Comprising FPGA state-detections and recovery module, DSP state-detections and recovery module, read back check and refresh module, configuration module,
House dog, DSP Loading Controls module and memory control module；
Working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery by fpga chip
Module detects the working condition of fpga chip, if fpga chip is working properly, continues working condition detection, if FPGA cores
Piece operation irregularity, then FPGA state-detections and recovery module transmission reset signal make its reset reconfigure to fpga chip；
Configuration module is by memory control module controls first memory, the matching somebody with somebody fpga chip from first memory
Put the configuration memory block that program is loaded into fpga chip, read back check and refresh module from the configuration memory block of fpga chip by shape
The value of state register and control register is read out, and is compared with the value original value of status register and control register,
If identical, continue retaking of a year or grade detection, if it is different, then leading to error indication signal to FPGA state-detections and recovery module
Cross read back check and refresh module to fpga chip carry out configure memory block refresh, if state is still abnormal, pass through FPGA shapes
State detects and recovery module resets to fpga chip and reconfigured；
Working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery mould by dsp chip
Block detects the working condition of dsp chip, if dsp chip is working properly, judges whether test point information needs to store, if belonging to
Test point to be protected, then test point information is arrived into second memory by store control logic storage, and continue work
Make state-detection, if test point need not be stored, continue to be operated state-detection, if dsp chip operation irregularity, DSP
State-detection and recovery module send reset signal to dsp chip, make its reset；The test point refers to be used to recover DSP works
Make the location point in the DSP programs at scene；
DSP Loading Controls module is by memory control module controls second memory, by DSP cores from second memory
The configurator of piece is loaded into the configuration memory block of dsp chip；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving instruction for a long time
Signal, watchdog module reset to dsp chip.
As shown in Fig. 2 the present invention is based on above-mentioned single-particle guard system, also achieves one kind and put down for Digital Signal Processing
The single particle effect means of defence of stand structure, step are as follows：
(1) configuration module is by memory control module controls first memory, by fpga chip from first memory
Configurator be loaded into the configuration memory block of fpga chip；DSP Loading Controls module passes through memory control module controls
Two memories, the configurator of dsp chip is loaded into the configuration memory block of dsp chip from second memory；
(2) by working state signal, (working state signal of fpga chip includes DONE signals to fpga chip, BUSY believes
Number, FAR frame address register value, status register value and control register value) be sent to FPGA state-detections and recovery module,
The working condition of FPGA state-detections and recovery module detection fpga chip, if fpga chip is working properly, continues work
Make state-detection, if fpga chip operation irregularity, then it represents that there occurs single event function interrupt SEFI, then FPGA state-detections and
Recovery module sends reset signal to fpga chip, makes its reset；
Read back check and refresh module configures memory block by status register and the value of control register from fpga chip
Read out, be compared with the value original value of status register and control register, if identical, continue retaking of a year or grade inspection
Survey, if it is different, then to error indication signal to FPGA state-detections and recovery module, by reading back check and refresh module pair
Fpga chip carries out configuring memory block refreshing, if state is still abnormal, by FPGA state-detections and recovery module to FPGA
Chip reset；
As shown in figure 3, it is specially：
(2.1) DONE signals are monitored：Detect whether DONE signals are high level, if DONE signals are high level, perform
Step (2.2)；Otherwise it is assumed that the electrification reset circuit (POR) of fpga chip performs step there occurs single event function interrupt
(2.5)；When fpga chip is in normal condition, after the completion of power on configuration, DONE signals should be high level always whenever
It is low situation if there is DONE, fpga chip then needs to reconfigure, if DONE signals are always low, then it is assumed that FPGA
There occurs electrification reset circuit (POR) single event function interrupt for chip；Por circuit is to be used to monitor FPGA cores inside fpga chip
The I/O voltages of piece core voltage VCCINT, BANK4 and boost voltage VCCAUX circuit.When voltage declines, por circuit can answer
Position fpga chip, removes configuration memory block, and electric current recovers the original state after supreme electricity, DONE signal step-downs.POR-SEFI's
Phenomenon is pulled low similar to FPGA power down, or PROG signals.
(2.2) BUSY signals are monitored：Detect whether BUSY signals are high level, if BUSY signals are high level, perform step
Suddenly (2.3)；Otherwise it is assumed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；
When fpga chip is in normal condition, when writing configuration memory block, BUSY signals should be low level；When read back operation starts,
BUSY signals are high level, and BUSY signals, which become low level, means that the back read data on data/address bus is effective；If from WriteMode
After being switched to reading mode, more than the 32 CCLK cycles of BUSY signals are high level always, it is meant that there occurs SELECTMAP interfaces
Single event function interrupt SEFI；
(2.3) FAR frame address register is read and write：Before refreshing every time or read back operation is carried out, FAR frame address is deposited
Device first writes the configuration memory block of fpga chip, judges whether the value that retaking of a year or grade goes out is correct, if correctly, continuing step
(2.4)；Otherwise it is assumed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；FAR
It is the frame address register inside fpga chip, FAR SEFI may cause frame address register not read and write, it is also possible to touch
Hair frame address register counts automatically, so as to cause large area configuration data mistake；
(2.4) status register value and control register value read-write：Pass through retaking of a year or grade status register and control register
Value, if differed with default value, it is believed that fpga chip performs step there occurs Global signals SEFI, POR SEFI
(2.5)；When fpga chip is in normal condition, after the completion of power on configuration, the value of status register should be the 7E of X " 00 00
FC ", the value of control register should be X " 20 00 01 09 ", retaking of a year or grade status register and control register can be passed through
Value, judging fpga chip, whether there occurs SEFI；
(2.5) reconfigure or power off reloading progress SEFI fault recoveries by resetting.Different SEFI are to FPGA's
Influence differs.Por circuit and Global Signals SEFI can interrupt FPGA functions, it is necessary to be reconfigured immediately.
The SEFI of SELECTMAP interfaces and FAR frame address registers does not influence user function, but can lose detection to SEU and extensive
Reactivation power, cause SEU error accumulations, so as to cause systemic-function to be interrupted, therefore in the case where task allows, it should enter as early as possible
Row reconfigures；
(3) working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery by dsp chip
Module detects the working condition of dsp chip, if dsp chip is working properly, judges whether test point information needs to store, if category
In test point to be protected, then test point information is arrived into second memory by store control logic storage, and continue
Working condition detects, if test point need not be stored, continues to be operated state-detection, if dsp chip operation irregularity, table
Show that then DSP state-detections and recovery module transmission reset signal make it to dsp chip there occurs single event function interrupt SEFI
Reset；The test point refer to for recover DSP working sites DSP programs in location point；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving instruction for a long time
Signal, watchdog module reset to dsp chip, complete the protection of the single particle effect.
As shown in figure 4, it is specially：
(3.1) start house dog, feeding-dog signal is produced in DSP course of normal operation, and monitor the work that dsp chip is sent
Make status signal, if working state signal is expected right value, carry out step (3.2)；Otherwise it is assumed that dsp chip occurs
Single event function interrupt, perform step (3.3)；
The working state signal that dsp chip is sent includes DSP interrupt response signal IACK, interruption code, specific work(
The significant variable of energy；For example, when dsp chip uses external interrupt mechanism works, can by judge IACK and interruption code come
Identify whether DSP working condition is normal, and according to external interrupt 4, interruption code should be normally " 0010 ", if not
" 0010 ", then it can conclude that dsp chip abnormal interrupt；
(3.2) judge whether test point preservation condition meets, if belonging to test point to be protected, controlled by memory
Module preserves the content of test point to second memory, return to step (3.1) after the completion of storage；Otherwise, direct return to step
(3.1)；The test point to be protected refers to：Need to do in the DSP programs specified by user preservation action position or by
Specified fixed interval does the position of preservation action automatically；Memory control module completes the preservation and retaking of a year or grade to test point；
For example, the program pointer address location of DSP subprograms；
(3.3) the DSP reseting logics in DSP state-detections and recovery module are started, and perform detection point recovers；The inspection
The content that measuring point recovers includes：(1) DSP programs perform scene:Include control register and general register；(2) program performs
Stack；(3) the calculating data acquisition system of program.Dsp chip register is divided into two kinds of general register and control register.General deposit
Device is divided into two groups of registers, for data storage and data address pointer.Dsp chip shares 10 control registers, is respectively
Addressing mode register, state of a control register, interrupt flag register, interrupt set register, interrupt clear register, in
Disconnected enabled register, interrupt service table pointer, interrupt return pointer, non-maskable interrupts return pointer and program counter.Journey
Sequence execution stack is function inset call, is interrupted, and the place of related register is stored during task switch protecting scene.The calculating of program
Data acquisition system refers to the key variables at the program to be recovered scene.For example, the single event function interrupt of interrupt control register,
Cause the generation of accidental interruption, upset normal procedure process, when test point preserves, interrupt control register variable will be stored
Value, when perform detection point recovers, DSP can correctly respond interruption；For example, if DSP completes the calculating work(that an order performs
Can, the significant variable in calculating process can be preserved, can be from the last time if single event function interrupt occurs for dsp chip
Test point recovered, it is ensured that as early as possible recovery routine scene；
Perform detection point recovers：The recovery of test point is detected in recovery unit by hardware trigger by SEFI
DSP state-detections and recovery module triggering are interrupted, and reset DSP according to interrupt signal, after DSP restartings, automatic guiding, then
Perform detection point recovers in a manner of abnormality processing；In test point recovery process, read from second memory in DSP programs
The information of one test point, is loaded the information into register and storehouse, then jumps into the program address specified, re-execute by
The program of interruption.
In summary, the single particle effect guard system and method that the present invention is presented, effectively slow down by FPGA and DSP
The SEFI problems of the digital information processing system of composition, improve the space environment adaptability of digital information processing system.Can
Be widely used in China's military communication, navigation, remote sensing satellite Digital Signal Processing class product, promote China's New Generation Military
Satellite technology develops to high-performance, highly reliable, miniaturization, long-life direction.
Unspecified part of the present invention belongs to technology as well known to those skilled in the art.
Claims (5)
1. the single particle effect guard system for digital signal processing platform framework, it is characterised in that including:Fpga chip,
Dsp chip, SEFI detections recovery unit, first memory and second memory, SEFI detection recovery units include FPGA states
Detection and recovery module, DSP state-detections and recovery module, read back check and refresh module, configuration module, house dog, DSP add
Carry control module and memory control module；
Working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery module by fpga chip
The working condition of fpga chip is detected, if fpga chip is working properly, continues working condition detection, if fpga chip is sent out
Raw single event function interrupt SEFI, then FPGA state-detections and recovery module transmission reset signal make its reset to fpga chip
Reconfigure；
Configuration module is by memory control module controls first memory, by the configuration journey of fpga chip from first memory
Sequence is loaded into the configuration memory block of fpga chip, reads back check and refresh module posts state from the configuration memory block of fpga chip
The value of storage and control register is read out, and is compared with the original value of status register and control register, if identical,
Then continue retaking of a year or grade detection, if it is different, then passing through retaking of a year or grade school to error indication signal to FPGA state-detections and recovery module
Test and refresh module carried out configuring memory block and refreshed to fpga chip, if state is still abnormal, by FPGA state-detections and
Recovery module resets to fpga chip to be reconfigured；
Working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery module inspection by dsp chip
The working condition of dsp chip is surveyed, if dsp chip is working properly, judges whether test point information needs to store, if belonging to protect
The test point of shield, then test point information is arrived into second memory by store control logic storage, and continue work shape
State detects, if test point need not be stored, continues to be operated state-detection, if SEFI, DSP states occur for dsp chip
Detection and recovery module send reset signal to dsp chip, make its reset；The test point refers to be used to recover DSP work now
Location point in the DSP programs of field；
DSP Loading Controls module is by memory control module controls second memory, by dsp chip from second memory
Configurator is loaded into the configuration memory block of dsp chip；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving indication signal for a long time,
Watchdog module resets to dsp chip.
2. the single particle effect means of defence for digital signal processing platform framework, it is characterised in that step is as follows：
(1) configuration module is by memory control module controls first memory, the matching somebody with somebody fpga chip from first memory
Put the configuration memory block that program is loaded into fpga chip；DSP Loading Controls module is deposited by memory control module controls second
Reservoir, the configurator of dsp chip is loaded into the configuration memory block of dsp chip from second memory；
(2) working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery by fpga chip
Module detects the working condition of fpga chip, if fpga chip is working properly, continues working condition detection, if FPGA cores
Piece operation irregularity, then it represents that there occurs single event function interrupt SEFI, then FPGA state-detections and recovery module, which are sent, resets letter
Number fpga chip is given, make its reset reconfigure；
Read back check and refresh module reads the value of status register and control register from the configuration memory block of fpga chip
Out, the value original value with status register and control register is compared, if identical, continues retaking of a year or grade detection, if
Difference, then to error indication signal to FPGA state-detections and recovery module, by reading back check and refresh module is to FPGA cores
Piece is carried out configuring memory block refreshing, if state is still abnormal, fpga chip is answered by FPGA state-detections and recovery module
Position reconfigures；
Specially：
(2.1) DONE signals are monitored：Detect whether DONE signals are high level, if DONE signals are high level, perform step
(2.2)；Otherwise it is assumed that the electrification reset circuit of fpga chip performs step (2.5) there occurs single event function interrupt；
(2.2) BUSY signals are monitored：Detect whether BUSY signals are high level, if BUSY signals are high level, perform step
(2.3)；Otherwise it is assumed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；
(2.3) FAR frame address register is read and write：It is before refreshing every time or read back operation is carried out, FAR frame address register is first
The configuration memory block of fpga chip is write, judges whether the value that retaking of a year or grade goes out is correct, if correctly, continuing step (2.4)；It is no
Then, it is believed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；
(2.4) status register value and control register value read-write：By retaking of a year or grade status register and the value of control register, such as
Fruit differs with default value, it is believed that fpga chip performs step there occurs Global signals SEFI or POR SEFI
(2.5)；
(2.5) SEFI fault recoveries are carried out by resetting to reconfigure or power off to reconfigure；
(3) working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery module by dsp chip
The working condition of dsp chip is detected, if dsp chip is working properly, judges whether test point information needs to store, will if belonging to
The test point of protection, then test point information is arrived into second memory by store control logic storage, and continue work
State-detection, if test point need not be stored, continue to be operated state-detection, if dsp chip operation irregularity, then it represents that hair
Single event function interrupt SEFI is given birth to, then DSP state-detections and recovery module send reset signal to dsp chip, make its reset；
The test point refer to for recover DSP working sites DSP programs in location point；
Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving indication signal for a long time,
Watchdog module resets to dsp chip, completes the protection of the single particle effect.
3. the single particle effect means of defence according to claim 2 for digital signal processing platform framework, its feature
It is：The working state signal of the fpga chip includes DONE signals, BUSY signals, FAR frame address register value, state and posted
Storage value and control register value.
4. the single particle effect means of defence according to claim 2 for digital signal processing platform framework, its feature
It is：The step (3) is specially：
(5.1) start house dog, feeding-dog signal is produced in DSP course of normal operation, and monitor the work shape that dsp chip is sent
State signal, if working state signal is expected right value, carry out step (5.2)；Otherwise it is assumed that there occurs list for dsp chip
Particle function is interrupted, and performs step (5.3)；
(5.2) judge whether test point preservation condition meets, if belonging to test point to be protected, pass through memory control module
The content of test point is preserved to second memory, return to step (5.1) after the completion of storage；Otherwise, direct return to step
(5.1)；The test point to be protected refers to：Need to do in the DSP programs specified by user preservation action position or by
Specified fixed interval does the position of preservation action automatically；
(5.3) the DSP reseting logics in DSP state-detections and recovery module are started, and perform detection point recovers；The test point
The content of recovery includes：(1) DSP programs perform scene:Include control register and general register；(2) program execution stack；
(3) the calculating data acquisition system of program.
5. the single particle effect means of defence according to claim 4 for digital signal processing platform framework, its feature
It is：The perform detection point recovers：
The recovery of test point is detected DSP state-detections and the recovery module triggering in recovery unit by hardware trigger by SEFI
Interrupt, DSP is resetted according to interrupt signal, after DSP restartings, guided automatically, then the perform detection in a manner of abnormality processing
Point recovers；In test point recovery process, the information of a test point in DSP programs is read from second memory, by information
It is loaded into register and storehouse, then jumps into the program address specified, re-executes the program being interrupted.
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