CN105068969B - Single particle effect guard system and method for digital signal processing platform framework - Google Patents

Abstract

The single event effect protection system and method for the digital signal processing platform architecture are aimed at solving the SEFI (Single Event Upset single event functional interruption) problem of the digital signal processing platform in the space environment. The present invention refines and perfects the platform framework supporting multi-level single particle soft error protection, detection and recovery technology through the organic integration of various measures, and proposes a systematic DSP and FPGA single particle function interruption fault detection and recovery method, which can effectively Mitigate SEFI effects on digital signal processing platforms. The invention can effectively overcome the problem of single event function interruption of the system working on orbit for a long time.

Description

Single event effect protection system and method for digital signal processing platform architecture

technical field

The invention relates to a system-level single event effect protection system and method for a digital signal processing platform architecture, belonging to the technical field of space communication.

Background technique

At present, in the on-board digital signal processing platform, since the large-scale SRAM type FPGA and DSP are mainly used to complete the digital signal processing function, the probability of single event effect of this type of product is greatly increased.

It is known from public publications that for the current digital signal processing system, the single event effect of the system is mainly alleviated by means of redundancy, refresh, error correction and detection, so that the system can still work normally in the event of SEU. However, when SEFI occurs in the system, the above measures cannot be solved, and targeted SEFI recovery measures must be taken to restore the system to normal.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art and provide a single event effect protection system and method for digital signal processing platform architecture, which can solve the SEFI problem of the system and improve the space reliability of the digital signal processing system.

The technical scheme adopted in the present invention is:

The single event effect protection system for digital signal processing platform architecture, including: FPGA chip, DSP chip, SEFI detection and recovery unit, first memory and second memory, SEFI detection and recovery unit includes FPGA state detection and recovery module, DSP state detection and recovery module, readback verification and refresh module, configuration module, watchdog, DSP loading control module and memory control module;

The FPGA chip sends the working status signal to the FPGA status detection and recovery module. The FPGA status detection and recovery module detects the working status of the FPGA chip. If the FPGA chip is working normally, it will continue to detect the working status. , the FPGA state detection and recovery module sends a reset signal to the FPGA chip to reset and reconfigure it;

The configuration module controls the first memory through the memory control module, loads the configuration program of the FPGA chip into the configuration storage area of the FPGA chip from the first memory, and reads back the verification and refresh module from the configuration storage area of the FPGA chip. The value of the register is read out and compared with the original value of the status register and the control register. If they are the same, the readback detection will continue. If they are different, an error indication signal will be sent to the FPGA status detection and recovery module. The inspection and refresh module refreshes the configuration storage area of the FPGA chip. If the state is still abnormal, the FPGA chip is reset and reconfigured through the FPGA state detection and recovery module;

The DSP chip sends the working status signal to the DSP status detection and recovery module. The DSP status detection and recovery module detects the working status of the DSP chip. If the DSP chip is working normally, it will judge whether the detection point information needs to be stored. If it belongs to the detection point to be protected , the detection point information is stored in the second memory through the memory control logic, and the working state detection is continued. If the detection point does not need to be stored, the working state detection is continued. If SEFI occurs on the DSP chip, the DSP state detection and recovery module Send a reset signal to the DSP chip to reset it; the detection point refers to a position point in the DSP program for recovering the DSP work site;

The DSP loading control module controls the second memory through the memory control module, and loads the configuration program of the DSP chip into the configuration storage area of the DSP chip from the second memory;

The watchdog module regularly receives the working status indication signal from the DSP chip, and if the indication signal is not received for a long time, the watchdog module resets the DSP chip.

A single event effect protection method for digital signal processing platform architecture, the steps are as follows:

(1) the configuration module controls the first memory by the memory control module, and loads the configuration program of the FPGA chip to the configuration storage area of the FPGA chip from the first memory; the DSP load control module controls the second memory by the memory control module, from the second Loading the configuration program of the DSP chip into the configuration storage area of the DSP chip in the memory;

(2) The FPGA chip sends the working status signal to the FPGA status detection and recovery module. The FPGA status detection and recovery module detects the working status of the FPGA chip. If the FPGA chip is working normally, continue to perform the working status detection. It means that a single event function interrupt SEFI has occurred, and the FPGA state detection and recovery module sends a reset signal to the FPGA chip to reset and reconfigure it;

The readback verification and refresh module reads the values of the status register and the control register from the configuration storage area of the FPGA chip, and compares them with the original values of the status register and the control register. If they are the same, continue the readback detection. If it is different, send an error indication signal to the FPGA state detection and recovery module, refresh the configuration storage area of the FPGA chip through the readback verification and refresh module, if the state is still abnormal, reset the FPGA chip through the FPGA state detection and recovery module reconfiguration;

(3) The DSP chip sends the working status signal to the DSP status detection and recovery module. The DSP status detection and recovery module detects the working status of the DSP chip. If the DSP chip is working normally, it is judged whether the detection point information needs to be stored. If there is no detection point, the detection point information is stored in the second memory through the memory control logic, and the working state detection is continued. If the detection point does not need to be stored, the working state detection is still continued. When the single event function interrupts SEFI, the DSP state detection and recovery module sends a reset signal to the DSP chip to reset it; the detection point refers to the position point in the DSP program for recovering the DSP work site;

The watchdog module regularly receives the working status indication signal from the DSP chip. If the indication signal is not received for a long time, the watchdog module resets the DSP chip to complete the protection against the single event effect.

The working status signals of the FPGA chip include a DONE signal, a BUSY signal, a FAR frame address register value, a status register value and a control register value.

Described step (2) is specifically:

(4.1) Monitor the DONE signal: detect whether the DONE signal is high level, if the DONE signal is high level, then perform step (4.2); otherwise, it is considered that the power-on reset circuit of the FPGA chip has a single event function interruption, and perform step (4.5);

(4.2) Monitor the BUSY signal: check whether the BUSY signal is high level, if the BUSY signal is high level, perform step (4.3); otherwise, consider that the single event function of the SELECTMAP interface on the FPGA chip is interrupted, and perform step (4.5) ;

(4.3) Reading and writing of FAR frame address register: Before each refresh or readback operation, write the FAR frame address register into the configuration storage area of the FPGA chip to determine whether the value read back is correct, and if it is correct, continue Carry out step (4.4); Otherwise, think that the single event function interruption of SELECTMAP interface has occurred in FPGA chip, carry out step (4.5);

(4.4) Reading and writing of the status register value and the control register value: By reading back the value of the status register and the control register, if it is different from the default value, it is considered that the FPGA chip has a Global signals SEFI (single event function interrupt of the global signal) or POR SEFI (single event function interrupt of power-on reset circuit), perform step (4.5);

(4.5) Perform SEFI fault recovery through reset reconfiguration or power-off reconfiguration.

Described step (3) is specifically:

(5.1) Start the watchdog, generate a dog feeding signal during the normal operation of the DSP, and monitor the working status signal sent by the DSP chip, if the working status signal is the expected correct value, then proceed to step (5.2); otherwise, consider A single event function interruption has occurred in the DSP chip, and step (5.3) is performed;

(5.2) Judging whether the detection point preservation condition is satisfied, if it belongs to the detection point to be protected, then the content of the detection point is saved to the second memory by the memory control module, and the storage is completed and returns to step (5.1); otherwise, directly returns to step ( 5.1); The detection point to be protected refers to: the position where the save action needs to be done in the DSP program specified by the user or the position where the save action is automatically done by specifying a fixed interval;

(5.3) start DSP state detection and the DSP reset logic in the recovery module, and carry out detection point recovery; The content of described detection point recovery comprises: (1) DSP program execution scene: comprise control register and general purpose register; (2) program Execution stack; (3) The calculation data set of the program.

The recovery of the execution detection point is specifically:

The recovery of the detection point is triggered by hardware, that is, it is interrupted by the DSP state detection and recovery module in the SEFI detection and recovery unit, and the DSP is reset according to the interrupt signal. After the DSP restarts, it will automatically boot, and then execute the detection point recovery in the way of exception handling; In the recovery process of the detection point, read the information of the last detection point of the DSP program from the second memory, load the information into the register and the stack, then jump into the specified program address, and re-execute the interrupted program.

The beneficial effect of the present invention compared with prior art is:

(1) In order to meet the space environment adaptability requirement of the digital signal processing system, the present invention adopts the single event function interruption of the method detection system of detecting DONE signal, BUSY signal and FAR value and state register value and control register value, has solved due to SELECTMAP interface , The FPGA power-on configuration and refresh failure problems caused by the SEFI of the POR power-on reset circuit.

(2) The present invention realizes the restoration of system functions by writing back configuration files and detection point storage files or system reset, which greatly reduces the probability of single-event function interruption when the digital signal processing system operates in a space radiation environment, and improves the system performance. single particle resistance.

Description of drawings

Fig. 1 is the functional block diagram of protection system of the present invention;

Fig. 2 is the flowchart of protection method of the present invention;

Fig. 3 is that the present invention is used for the SEFI detection of system FPGA and restores flowchart;

Fig. 4 is a flow chart of SEFI detection and recovery for system DSP according to the present invention.

detailed description

The invention provides a system-level single event effect protection system and protection method adapted to a digital signal processing platform. A SEFI detection and recovery unit is used to detect the state of the system, and if SEFI occurs in FPGA and DSP, recovery measures are taken. For the SEFI detection and recovery of the FPGA, the SEFI detection and recovery unit configures the FPGA. After the configuration is completed, it detects the DONE signal, BUSY signal, FAR value, status register value, and control register value of the FPGA. If SEFI occurs, power-on reconfiguration is adopted. or reset method for system recovery. For SEFI detection and recovery of DSP, the SEFI detection and recovery unit saves the detection point of DSP, detects whether SEFI occurs in DSP through the watchdog, detects that SEFI does not occur, and saves the detection point at the same time. When SEFI occurs, the detection point can be restored by To achieve the purpose of restoring the system.

As shown in Figure 1, the single event effect protection system for digital signal processing platform architecture provided by the present invention includes: FPGA chip, DSP chip, SEFI detection recovery unit, first memory and second memory, SEFI detection recovery unit includes FPGA state detection and recovery module, DSP state detection and recovery module, readback verification and refresh module, configuration module, watchdog, DSP loading control module and memory control module;

The FPGA chip sends the working status signal to the FPGA status detection and recovery module. The FPGA status detection and recovery module detects the working status of the FPGA chip. If the FPGA chip works normally, it continues to detect the working status. If the FPGA chip works abnormally, the FPGA status The detection and recovery module sends a reset signal to the FPGA chip to reset and reconfigure it;

The configuration module controls the first memory through the memory control module, loads the configuration program of the FPGA chip into the configuration storage area of the FPGA chip from the first memory, and reads back the verification and refresh module from the configuration storage area of the FPGA chip. The value of the register is read out and compared with the original value of the status register and the control register. If they are the same, the readback detection will continue. If they are different, an error indication signal will be sent to the FPGA status detection and recovery module. The verification and refresh module refreshes the configuration storage area of the FPGA chip. If the state is still abnormal, the FPGA chip is reset and reconfigured through the FPGA state detection and recovery module;

The DSP chip sends the working status signal to the DSP status detection and recovery module. The DSP status detection and recovery module detects the working status of the DSP chip. If the DSP chip is working normally, it will judge whether the detection point information needs to be stored. If it belongs to the detection point to be protected , the detection point information is stored in the second memory through the memory control logic, and the working state detection is continued. If the detection point does not need to be stored, the working state detection is continued. Send a reset signal to the DSP chip to reset it; the detection point refers to a position point in the DSP program for recovering the DSP work site;

The DSP loading control module controls the second memory through the memory control module, and loads the configuration program of the DSP chip into the configuration storage area of the DSP chip from the second memory;

The watchdog module regularly receives the working status indication signal from the DSP chip, and if the indication signal is not received for a long time, the watchdog module resets the DSP chip.

As shown in Figure 2, the present invention is based on the above single event protection system, and also realizes a single event effect protection method for digital signal processing platform architecture, the steps are as follows:

(1) the configuration module controls the first memory by the memory control module, and loads the configuration program of the FPGA chip to the configuration storage area of the FPGA chip from the first memory; the DSP load control module controls the second memory by the memory control module, from the second Loading the configuration program of the DSP chip into the configuration storage area of the DSP chip in the memory;

(2) The FPGA chip sends the working status signal (the working status signal of the FPGA chip includes DONE signal, BUSY signal, FAR frame address register value, status register value and control register value) to the FPGA status detection and recovery module, FPGA status detection and The recovery module detects the working status of the FPGA chip. If the FPGA chip is working normally, it will continue to detect the working status. If the FPGA chip is working abnormally, it means that a single event function interrupt SEFI has occurred, and the FPGA status detection and recovery module sends a reset signal to the FPGA. Chip, reset it;

The readback verification and refresh module reads the values of the status register and the control register from the configuration storage area of the FPGA chip, and compares them with the original values of the status register and the control register. If they are the same, continue the readback detection. If it is different, send an error indication signal to the FPGA state detection and recovery module, refresh the configuration storage area of the FPGA chip through the readback verification and refresh module, if the state is still abnormal, reset the FPGA chip through the FPGA state detection and recovery module ;

As shown in Figure 3, specifically:

(2.1) Monitor the DONE signal: detect whether the DONE signal is high level, if the DONE signal is high level, then perform step (2.2); otherwise, it is considered that the power-on reset circuit (POR) of the FPGA chip has a single event function interruption , execute step (2.5); when the FPGA chip is in a normal state, after the power-on configuration is completed, the DONE signal should always be high. If the DONE is low at any time, the FPGA chip needs to be reconfigured. If the DONE signal is always If it is low, it is considered that the FPGA chip has a power-on reset circuit (POR) single event function interruption; the POR circuit is a circuit inside the FPGA chip used to monitor the FPGA chip core voltage VCCINT, the I/O voltage of BANK4 and the auxiliary voltage VCCAUX. When the voltage drops, the POR circuit will reset the FPGA chip, clear the configuration storage area, the current will return to the initial state after power-on, and the DONE signal will become low. The phenomenon of POR-SEFI is similar to FPGA power down, or the PROG signal is pulled low.

(2.2) Monitor the BUSY signal: check whether the BUSY signal is high level, if the BUSY signal is high level, perform step (2.3); otherwise, consider that the single event function of the SELECTMAP interface on the FPGA chip is interrupted, and perform step (2.5) ;When the FPGA chip is in a normal state, when writing the configuration storage area, the BUSY signal should be low; when the readback operation starts, the BUSY signal is high, and the BUSY signal becomes low, which means the readback on the data bus The data is valid; if the BUSY signal has been at a high level for more than 32 CCLK cycles after switching from the write mode to the read mode, it means that the single event function interrupt SEFI of the SELECTMAP interface has occurred;

(2.3) Reading and writing of FAR frame address register: Before each refresh or readback operation, write the FAR frame address register into the configuration storage area of the FPGA chip to determine whether the value read back is correct, and if it is correct, continue Proceed to step (2.4); otherwise, think that the single event function interruption of the SELECTMAP interface has occurred on the FPGA chip, and perform step (2.5); FAR is the frame address register inside the FPGA chip, FAR SEFI may cause the frame address register to be unable to read and write, and it is also possible Trigger the automatic counting of the frame address register, resulting in large-area configuration data errors;

(2.4) Reading and writing of status register value and control register value: By reading back the value of the status register and control register, if it is different from the default value, it is considered that Global signals SEFI and POR SEFI have occurred on the FPGA chip, and step (2.5) is performed; FPGA chip When the chip is in a normal state, after the power-on configuration is completed, the value of the status register should be X"00 00 7EFC", and the value of the control register should be X"20 00 01 09". You can read back the values of the status register and the control register , to determine whether the FPGA chip has SEFI;

(2.5) Perform SEFI failure recovery by reconfiguring or power-off and reloading. Different SEFIs have different effects on FPGAs. The POR circuitry and Global Signals' SEFI interrupt FPGA functionality and must be reconfigured immediately. The SEFI of the SELECTMAP interface and the FAR frame address register does not affect the user function, but it will lose the ability to detect and recover SEU, resulting in the accumulation of SEU errors, resulting in interruption of system functions. Therefore, reconfiguration should be performed as soon as possible if the task permits;

(3) The DSP chip sends the working status signal to the DSP status detection and recovery module. The DSP status detection and recovery module detects the working status of the DSP chip. If the DSP chip is working normally, it is judged whether the detection point information needs to be stored. If there is no detection point, the detection point information is stored in the second memory through the memory control logic, and the working state detection is continued. If the detection point does not need to be stored, the working state detection is still continued. When the single event function interrupts SEFI, the DSP state detection and recovery module sends a reset signal to the DSP chip to reset it; the detection point refers to the position point in the DSP program for recovering the DSP work site;

The watchdog module regularly receives the working status indication signal from the DSP chip. If the indication signal is not received for a long time, the watchdog module resets the DSP chip to complete the protection against the single event effect.

As shown in Figure 4, specifically:

(3.1) Start the watchdog, generate a dog feeding signal during the normal operation of the DSP, and monitor the working status signal sent by the DSP chip, if the working status signal is the expected correct value, then proceed to step (3.2); otherwise, consider A single event function interruption has occurred in the DSP chip, and step (3.3) is performed;

The working status signal sent by the DSP chip includes the DSP interrupt response signal IACK, interrupt code, and important variables of specific functions; Normal, if external interrupt 4 is used, the interrupt code should be "0010" normally, if not "0010", it can be concluded that the DSP chip is interrupted abnormally;

(3.2) Judging whether the detection point preservation condition is satisfied, if it belongs to the detection point to be protected, then the content of the detection point is saved to the second memory by the memory control module, and returns to step (3.1) after the storage is completed; otherwise, directly returns to step ( 3.1); The detection point to be protected refers to: in the DSP program designated by the user, the position of the preservation action needs to be done or the position of the preservation action is automatically performed by the specified fixed interval time; the memory control module completes the preservation and return of the detection point Read; for example, the program pointer address location of a DSP subroutine;

(3.3) start DSP state detection and the DSP reset logic in the recovery module, and carry out detection point recovery; The content of described detection point recovery comprises: (1) DSP program execution scene: comprise control register and general purpose register; (2) program Execution stack; (3) The calculation data set of the program. DSP chip registers are divided into general registers and control registers. General-purpose registers are divided into two groups of registers for storing data and data address pointers. The DSP chip has a total of 10 control registers, which are addressing mode register, control status register, interrupt flag register, interrupt setting register, interrupt clearing register, interrupt enabling register, interrupt service table pointer, interrupt return pointer, non-maskable interrupt return pointer and program counter. The program execution stack is the place where related registers are stored when function nested calls, interrupts, and task switching protect the scene. The calculation data set of the program refers to the key variables of the program site to be restored. For example, the single-event function interrupt of the interrupt control register will cause an unexpected interrupt and disturb the normal program process. When the check point is saved, the variable value of the interrupt control register will be stored. When the check point is restored, the DSP can correctly respond to the interrupt; for example , if the DSP completes a sequential calculation function, it can save the important variables in the calculation process. If the single event function of the DSP chip is interrupted, it can recover from the latest detection point to ensure that the program site can be restored as soon as possible;

Execution of detection point recovery is specifically: the recovery of detection points is triggered by hardware, that is, interrupted by the DSP state detection and recovery module in the SEFI detection recovery unit, and the DSP is reset according to the interrupt signal. Execute checkpoint recovery in the same way; during the checkpoint recovery process, read the information of the last checkpoint of the DSP program from the second memory, load the information into the register and stack, then jump into the specified program address, and re-execute the interrupted program.

In summary, the single event effect protection system and method presented in the present invention effectively alleviate the SEFI problem of the digital signal processing system composed of FPGA and DSP, and improve the space environment adaptability of the digital signal processing system. It can be widely used in digital signal processing products of my country's military communication, navigation, and remote sensing satellites, and promotes the development of my country's new generation of military satellite technology in the direction of high performance, high reliability, miniaturization, and long life.

Parts not described in detail in the present invention belong to the well-known technology of those skilled in the art.

Claims (5)

1. the single particle effect guard system for digital signal processing platform framework, it is characterised in that including:Fpga chip, Dsp chip, SEFI detections recovery unit, first memory and second memory, SEFI detection recovery units include FPGA states Detection and recovery module, DSP state-detections and recovery module, read back check and refresh module, configuration module, house dog, DSP add Carry control module and memory control module；

Working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery module by fpga chip The working condition of fpga chip is detected, if fpga chip is working properly, continues working condition detection, if fpga chip is sent out Raw single event function interrupt SEFI, then FPGA state-detections and recovery module transmission reset signal make its reset to fpga chip Reconfigure；

Configuration module is by memory control module controls first memory, by the configuration journey of fpga chip from first memory Sequence is loaded into the configuration memory block of fpga chip, reads back check and refresh module posts state from the configuration memory block of fpga chip The value of storage and control register is read out, and is compared with the original value of status register and control register, if identical, Then continue retaking of a year or grade detection, if it is different, then passing through retaking of a year or grade school to error indication signal to FPGA state-detections and recovery module Test and refresh module carried out configuring memory block and refreshed to fpga chip, if state is still abnormal, by FPGA state-detections and Recovery module resets to fpga chip to be reconfigured；

Working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery module inspection by dsp chip The working condition of dsp chip is surveyed, if dsp chip is working properly, judges whether test point information needs to store, if belonging to protect The test point of shield, then test point information is arrived into second memory by store control logic storage, and continue work shape State detects, if test point need not be stored, continues to be operated state-detection, if SEFI, DSP states occur for dsp chip Detection and recovery module send reset signal to dsp chip, make its reset；The test point refers to be used to recover DSP work now Location point in the DSP programs of field；

DSP Loading Controls module is by memory control module controls second memory, by dsp chip from second memory Configurator is loaded into the configuration memory block of dsp chip；

Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving indication signal for a long time, Watchdog module resets to dsp chip.

2. the single particle effect means of defence for digital signal processing platform framework, it is characterised in that step is as follows：

(1) configuration module is by memory control module controls first memory, the matching somebody with somebody fpga chip from first memory Put the configuration memory block that program is loaded into fpga chip；DSP Loading Controls module is deposited by memory control module controls second Reservoir, the configurator of dsp chip is loaded into the configuration memory block of dsp chip from second memory；

(2) working state signal is sent to FPGA state-detections and recovery module, FPGA state-detections and recovery by fpga chip Module detects the working condition of fpga chip, if fpga chip is working properly, continues working condition detection, if FPGA cores Piece operation irregularity, then it represents that there occurs single event function interrupt SEFI, then FPGA state-detections and recovery module, which are sent, resets letter Number fpga chip is given, make its reset reconfigure；

Read back check and refresh module reads the value of status register and control register from the configuration memory block of fpga chip Out, the value original value with status register and control register is compared, if identical, continues retaking of a year or grade detection, if Difference, then to error indication signal to FPGA state-detections and recovery module, by reading back check and refresh module is to FPGA cores Piece is carried out configuring memory block refreshing, if state is still abnormal, fpga chip is answered by FPGA state-detections and recovery module Position reconfigures；

Specially：

(2.1) DONE signals are monitored：Detect whether DONE signals are high level, if DONE signals are high level, perform step (2.2)；Otherwise it is assumed that the electrification reset circuit of fpga chip performs step (2.5) there occurs single event function interrupt；

(2.2) BUSY signals are monitored：Detect whether BUSY signals are high level, if BUSY signals are high level, perform step (2.3)；Otherwise it is assumed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；

(2.3) FAR frame address register is read and write：It is before refreshing every time or read back operation is carried out, FAR frame address register is first The configuration memory block of fpga chip is write, judges whether the value that retaking of a year or grade goes out is correct, if correctly, continuing step (2.4)；It is no Then, it is believed that fpga chip performs step (2.5) there occurs the single event function interrupt of SELECTMAP interfaces；

(2.4) status register value and control register value read-write：By retaking of a year or grade status register and the value of control register, such as Fruit differs with default value, it is believed that fpga chip performs step there occurs Global signals SEFI or POR SEFI (2.5)；

(2.5) SEFI fault recoveries are carried out by resetting to reconfigure or power off to reconfigure；

(3) working state signal is sent to DSP state-detections and recovery module, DSP state-detections and recovery module by dsp chip The working condition of dsp chip is detected, if dsp chip is working properly, judges whether test point information needs to store, will if belonging to The test point of protection, then test point information is arrived into second memory by store control logic storage, and continue work State-detection, if test point need not be stored, continue to be operated state-detection, if dsp chip operation irregularity, then it represents that hair Single event function interrupt SEFI is given birth to, then DSP state-detections and recovery module send reset signal to dsp chip, make its reset； The test point refer to for recover DSP working sites DSP programs in location point；

Working condition indication signal of the watchdog module timing receipt from dsp chip, if not receiving indication signal for a long time, Watchdog module resets to dsp chip, completes the protection of the single particle effect.

3. the single particle effect means of defence according to claim 2 for digital signal processing platform framework, its feature It is：The working state signal of the fpga chip includes DONE signals, BUSY signals, FAR frame address register value, state and posted Storage value and control register value.

4. the single particle effect means of defence according to claim 2 for digital signal processing platform framework, its feature It is：The step (3) is specially：

(5.1) start house dog, feeding-dog signal is produced in DSP course of normal operation, and monitor the work shape that dsp chip is sent State signal, if working state signal is expected right value, carry out step (5.2)；Otherwise it is assumed that there occurs list for dsp chip Particle function is interrupted, and performs step (5.3)；

(5.2) judge whether test point preservation condition meets, if belonging to test point to be protected, pass through memory control module The content of test point is preserved to second memory, return to step (5.1) after the completion of storage；Otherwise, direct return to step (5.1)；The test point to be protected refers to：Need to do in the DSP programs specified by user preservation action position or by Specified fixed interval does the position of preservation action automatically；

(5.3) the DSP reseting logics in DSP state-detections and recovery module are started, and perform detection point recovers；The test point The content of recovery includes：(1) DSP programs perform scene:Include control register and general register；(2) program execution stack； (3) the calculating data acquisition system of program.

5. the single particle effect means of defence according to claim 4 for digital signal processing platform framework, its feature It is：The perform detection point recovers：

The recovery of test point is detected DSP state-detections and the recovery module triggering in recovery unit by hardware trigger by SEFI Interrupt, DSP is resetted according to interrupt signal, after DSP restartings, guided automatically, then the perform detection in a manner of abnormality processing Point recovers；In test point recovery process, the information of a test point in DSP programs is read from second memory, by information It is loaded into register and storehouse, then jumps into the program address specified, re-executes the program being interrupted.