CN104866387A - Storage method and system based on stored data anti-jamming of ERC32 processor - Google Patents
Storage method and system based on stored data anti-jamming of ERC32 processor Download PDFInfo
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Abstract
The invention provides a storage method and system based on stored data anti-jamming of an ERC32 processor. The abnormal trap mechanism of an ERC32 processor is utilized, the EDAC method and the triple-modular redundancy method are combined, and an internal memory is periodically refreshed by software. If one-bit turnover occurs, the EDAC method is adopted for error correction; if multi-bit errors occur, wrong data in units are eliminated at first, a specific abnormality is triggered to reset, and data recovery is realized through three-out-of-two principle. All data on the bottom program follow the three-out-of-three principle, and independent three-out-of-two principle of the upper-layer application program before use of each data is not required, so that the software complexity is reduced and the software reliability is improved.
Description
Technical field
The present invention relates to the reliability design of satellite carried device data transmission, particularly relate to a kind of based on the jamproof storage means of ERC32 processor memory data and system.
Background technology
Spaceborne computer uses under outer space environment; owing to lacking magnetic field of the earth protection; data bit in internal storage location is more easily subject to as the impact of the factor such as solar windstorm, cosmic rays; occur that " 0 " of transient state becomes the failure condition that " 1 " or " 1 " becomes " 0 ", this phenomenon is called " single-particle inversion ".
Realize in current satellite model that internal storage data is anti-interference mainly contains two kinds of methods: a kind of method is by hardware circuit EDAC EDC error detect correction, the each unit refreshed in internal memory regularly read and write by software, owing to hardware adding suitable supervision code bit when reading unit, coordinate EDAC algorithm, make the data read to correct or to detect possible bit flipping; Another kind method takes the storage mode of triplication redundancy, during storage, data is stored in respectively three different region of memorys, carries out three and get two votings, choose the numerical value occupied the majority before using.
Two kinds of above-mentioned internal storage data anti-interference methods exist significantly not enough: the method for EDAC EDC error detect correction is due to the code bit length restriction that is subjected to supervision, 1 bit-errors in each 32 bit locations can only be corrected at present, and the mistake of more than two and two can not be corrected, the latter three data of getting in two are stored in address gaps three regions far away, the possibility be totally disrupted is very low, but first general data triplication redundancy first can read the data of three internal storage locations when recovering, if there is mistake, the trap (TRAP INTRAP) in fault trap can be caused, this situation can make calling program be absorbed in endless loop, the expense of triplication redundancy committed memory is larger in addition, when particularly adopting in a large number in software, realization on coding can make software readable decline, complexity rises, thus in another side effect software reliability.
Summary of the invention
In order to solve deficiency set forth above, the invention provides a kind of based on the jamproof storage means of ERC32 processor memory data, comprising:
After starting to store data:
Every a very first time, data are stored into the address location that three of application program argument table in RAM are different; Keep in the region of certain address gaps until all data are all stored in three;
Every one second time, in RAM stored in data refresh, and detect data and whether there is mistake; If the data in address location exist a dislocation, then corrected by EDAC, then the data after correcting are write back raw address unit; If the data in address location exist multidigit mistake, then by the zeros data in this address location;
After one the 3rd time or processor are reset, read the data be stored in three address locations of same data, data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority is covered the address location writing back the data occupied the minority.
Optionally, before starting to store data, also comprise the process of RAM being carried out to internal memory initialization.
Optionally, stored in three of same data different address locations address between difference be fixed value, and this fixed value is not less than value corresponding to the combined length of the required all data stored in described application program table.
Optionally, corrected by EDAC, then the process data after correction being write back raw address unit at least comprises:
Whether address register numerical value corresponding to misjudgment data is positioned at ram region, if be arranged in ram region, then from the address location that this address register indicates, take out data, writes back after correction again.
Optionally, the process of the zeros data in this address location is at least comprised:
Address register numerical value corresponding to misjudgment data whether is arranged in ram region and whether trap register trap type value is a particular value, if be positioned at ram region and trap type value is this particular value, then by the zeros data in this address location.
Optionally, the data after correction write back raw address unit and by after the zeros data in address location, also comprise the process of error count and the reset of system fault condition register.
Present invention also offers a kind of based on the jamproof storage system of ERC32 processor memory data, comprising:
Unified three storing modules, three in order to data to be stored into application program argument table in RAM different address locations; Keep in the region of certain address gaps until all data are all stored in three;
Unified three get a module, in order to read the data be stored in three address locations of same data, the data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority are covered the address location writing back the data occupied the minority;
, in order to respond the testing result of described storage unit, there is the situation of a dislocation, corrected by EDAC in one dislocation processing module, then the data after correcting are write back raw address unit for the data in address location;
, in order to respond the testing result of described storage unit, there is the situation of multidigit mistake for the data in address location in the wrong processing module of multidigit, by the zeros data in this address location, and resetting processor;
Storage unit, in order to in RAM stored in data refresh, read and detect data whether there is mistake, thus call and start the wrong processing module of a described dislocation processing module or multidigit;
Main program module, at least calls described unification three storing module of startup in order to whether to be reset according to time and processor, storage unit, unified three gets a module;
And described application program argument table.
Optionally, describedly internal memory initialization module is also comprised, in order to carry out internal memory initialization to RAM based on the jamproof storage system of ERC32 processor memory data.
Optionally, described also comprises interruption initialization module based on the jamproof storage system of ERC32 processor memory data, with thinking that a described dislocation processing module and multidigit fault reason block configuration are interrupted accordingly, thus make described storage unit can by the wrong processing module of a dislocation processing module described in interrupt call and multidigit.
Optionally, described storage unit is further in order to pass through a dislocation processing module described in interrupt call and the wrong processing module of multidigit; Described storage unit when refreshing data, further in order to:
Close and interrupt, the data reading the address location of specifying, to register, then write back in address location, then open interruption.
The present invention utilizes the exception trap mechanism of ERC32 processor, EDAC and triplication redundancy two methods combining are got up to use, software regularly refreshes internal memory, if there is a bit flipping, then adopt between EDAC mode and correct a mistake, if there is multi-bit error, misdata then first in clearing cell, and trigger specific exceptional reset, two recovery data are got again by three, on underlying programs realizes, deposit three to each data unified three get, upper level applications need not be carried out separately three and be got two before each data of use, thus reduce complex software program, improve software reliability.
For this reason, a kind of internal storage data anti-interference method based on ERC32 processor can change this deficiency, this methods combining EDAC refreshes and three advantages of getting 2 two kinds of methods, it also avoid the shortcoming existed separately simultaneously, can either simple and quick correction one bit-errors, two recovery multi-bit errors can be got by three again, improve the jamproof ability of internal storage data.
Accompanying drawing explanation
Fig. 1 is the data flow diagram based on the jamproof storage means of ERC32 processor memory data and system in one embodiment of the invention;
Fig. 2 is the logic diagram of a dislocation process in one embodiment of the invention;
Fig. 3 is the logic diagram of multidigit fault reason in one embodiment of the invention.
Embodiment
Be described in detail based on the jamproof storage means of ERC32 processor memory data and system provided by the invention below with reference to Fig. 1 to Fig. 3, it is optional embodiment of the present invention, can think, those skilled in the art can modify to it and polish in the scope not changing the present invention's spirit and content.
Please refer to Fig. 1, the invention provides a kind of based on the jamproof storage means of ERC32 processor memory data, comprising:
After starting to store data:
Every a very first time, data are stored into the address location that three of application program argument table in RAM are different; Keep in the region of certain address gaps until all data are all stored in three;
Every one second time, in RAM stored in data refresh, and detect data and whether there is mistake; In the present invention one optional embodiment, specifically can comprise the data of the address location that reading is specified to register to the process that data refresh, then write back in address location;
After one the 3rd time or processor are reset, read the data be stored in three address locations of same data, data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority is covered the address location writing back the data occupied the minority.
Please refer to Fig. 2, in the embodiment of its signal, if the data in address location exist a dislocation, then corrected by EDAC, then the data after correcting are write back raw address unit; Furthermore, at least comprise: whether address register numerical value corresponding to misjudgment data is positioned at ram region, if be arranged in ram region, then from the address location that this address register indicates, take out data, writes back after correction again.
Please refer to Fig. 3, in the embodiment of its signal, if the data in address location exist multidigit mistake, then by the zeros data in this address location; The process of the zeros data in this address location is at least comprised address register numerical value corresponding to misjudgment data and whether be arranged in ram region and whether trap register trap type value is a particular value, if be positioned at ram region and trap type value for this particular value, then by the zeros data in this address location.
Data after correcting are write back raw address unit and by after the zeros data in address location, also comprise the process of error count and the reset of system fault condition register.Please refer to Fig. 2, when existence one dislocation, after the data after correction are write back raw address unit, also carry out single-bit error counting, interrupt clearly, system fault condition register resets; Please refer to Fig. 3, when there is multidigit mistake, after clearing, also carrying out multi-bit errors counting, system fault condition register resets.
Before starting to store data, also comprise the process of RAM being carried out to internal memory initialization.Unit whole in RAM must reset by internal memory initialization.
The problem of 1 dislocation that the present invention causes by space environment Single event upset effecf in order to the spaceborne computer internal storage location solved based on ERC32 processor and the wrong date restoring of multidigit, the object of the invention is to propose a kind of internal storage data anti-disturbance method based on ERC32 processor, utilize the present invention, the object improving data reliability and recovery capability on star can be realized.
Corresponding with the method, present invention also offers a kind of based on the jamproof storage system of ERC32 processor memory data, comprising:
Unified three storing modules, three in order to data to be stored into application program argument table in RAM different address locations; Keep in the region of certain address gaps until all data are all stored in three; Namely each data are deposited three parts, and the portion wherein of each data is stored in an address area, there is address gaps between three address areas; The unit of three described different addresses, difference between address is fixed value, and this fixed value should be more than or equal to the combined length of all defined complete sets of data in application program table, in this definition, can be understood as, after carrying out redundant storage, three sets of data can be formed, here a complete sets of data, what only refer to wherein is a set of, here defined can be understood as in whole application program need 1 deposit 3 all data.；
Unified three get a module, in order to read the data be stored in three address locations of same data, data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority is covered the address location writing back the data occupied the minority, here covering writes back, refer to the address location this numerical value being write the data occupied the minority, to cover the data be originally written in this address location; About three get two voting, what refer to can be carry out comparison between two after taking out in three corresponding address unit, is taken to the numerical value of rare two parts of consistent unit, and this numerical value is covered the unit writing back another part and occupy the minority.
Unified three storing modules and unified three get two modules should for the whole variablees defined in application program table.
One dislocation processing module, in order to respond the testing result of described storage unit, is namely stored cell call and starts, there is the situation of a dislocation, corrected by EDAC for the data in address location, then the data after correcting are write back raw address unit; Please refer to Fig. 2, specifically, whether address register numerical value corresponding to misjudgment data is positioned at ram region, if address is positioned at ram region, from the address location that this address register indicates, take out data, write back this unit again after correction, single-bit error counts, clear interruption, system fault condition register resets; One dislocation processing execution terminates rear program pointer and returns the address continuation execution interrupted before occurring, and does not reset to processor.Visible, it, by read operation, is corrected the dislocation in single 32 bit locations, then writes back raw address unit, thus recovers the data in storage unit
, in order to respond the testing result of described storage unit, there is the situation of multidigit mistake for the data in address location in the wrong processing module of multidigit, by the zeros data in this address location, and resetting processor; Specifically, please refer to Fig. 3, address register numerical value corresponding to misjudgment data whether is arranged in ram region and whether trap register trap type value is a particular value, in the embodiment of Fig. 3 signal, trap type value is 9, if be positioned at ram region and trap type value for this particular value, then by the zeros data in this address location, multi-bit errors counts, and system fault condition register resets.Must reset to processor after the wrong processing execution of multidigit terminates, after resetting, unified three get a module and can carry out unifying three and get two by application programs argument table; Visible, it resets after the zeros data occurred in the address location of multidigit mistake, re-uses triplication redundancy Backup Data, gets two recovery data by three;
Storage unit, in order to in RAM stored in data refresh, read and detect data whether there is mistake, thus call and start the wrong processing module of a described dislocation processing module or multidigit; Furthermore, a storage unit regularly refreshes, whole address location in traversal read/write memory, and storage unit starts a dislocation processing module and the wrong processing module of multidigit by interrupt call; Described storage unit performs following process when regularly refreshing: close and interrupt; Read the data of assigned address unit to register; Then data in register are write back this address location again; Open interruption again; Assigned address adds 1;
Internal memory initialization module, in order to carry out internal memory initialization to RAM; Unit whole in RAM must reset by internal memory initialization;
Interrupting initialization module, with thinking that a described dislocation processing module and multidigit fault reason block configuration are interrupted accordingly, thus making described storage unit can by the wrong processing module of a dislocation processing module described in interrupt call and multidigit; Because storage unit is by interrupting calling a dislocation processing module and the wrong processing module of multidigit, so just needing the initialization carrying out interrupting is that a dislocation processing module and multidigit fault reason block configuration are interrupted accordingly; In an optional embodiment, described interruption initialization at least must configure No. 6 can correct the interrupt service routine that memory error is interrupted and No. 29 memory protections are interrupted;
Main program module, at least call described unification three storing module of startup in order to whether to be reset according to time and processor, storage unit, unified three gets a module, specifically, same three storing modules are called exactly every the very first time, storage unit is called every the second time, after the 3rd time or processor are reset, call same three and get a module; In optional embodiment of the present invention, described master routine at least must open No. 6 can correct memory error interruption and No. 29 memory protections interruptions, and is in the state of circular wait interruption;
And described application program argument table, store global data, i.e. variable needed for application program for pressing triplication redundancy.
In the present invention's major part embodiment, after electrifying startup, order performs internal memory initialization and interrupts initialization, enter master routine, in master routine timesharing call unified three to deposit, storage unit regularly refreshes and unifies three and get two modules, if processor detects error in data when storage unit regularly refreshes, by the dislocation process of different exception trap entrance interrupt call one and multidigit fault reason.
In sum, the present invention utilizes the exception trap mechanism of ERC32 processor, EDAC and triplication redundancy two methods combining are got up to use, software regularly refreshes internal memory, if there is a bit flipping, then adopt between EDAC mode and correct a mistake, if there is multi-bit error, misdata then first in clearing cell, and trigger specific exceptional reset, two recovery data are got again by three, on underlying programs realizes, deposit three to each data unified three get, upper level applications need not be carried out separately three and be got two before each data of use, thus reduce complex software program, improve software reliability.
For this reason, a kind of internal storage data anti-interference method based on ERC32 processor can change this deficiency, this methods combining EDAC refreshes and three advantages of getting 2 two kinds of methods, it also avoid the shortcoming existed separately simultaneously, can either simple and quick correction one bit-errors, two recovery multi-bit errors can be got by three again, improve the jamproof ability of internal storage data.
Claims (10)
1., based on the jamproof storage means of ERC32 processor memory data, comprising:
After starting to store data:
Every a very first time, data are stored into the address location that three of application program argument table in RAM are different; Keep in the region of certain address gaps until all data are all stored in three;
Every one second time, in RAM stored in data refresh, and detect data and whether there is mistake; If the data in address location exist a dislocation, then corrected by EDAC, then the data after correcting are write back raw address unit; If the data in address location exist multidigit mistake, then by the zeros data in this address location, resetting processor;
After one the 3rd time or processor are reset, read the data be stored in three address locations of same data, data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority is covered the address location writing back the data occupied the minority.
2. as claimed in claim 1 based on the jamproof storage means of ERC32 processor memory data, it is characterized in that: before starting to store data, also comprise the process of RAM being carried out to internal memory initialization.
3. as claimed in claim 1 based on the jamproof storage means of ERC32 processor memory data, it is characterized in that: stored in three of same data different address locations address between difference be fixed value.
4. as claimed in claim 1 based on the jamproof storage means of ERC32 processor memory data, it is characterized in that: corrected by EDAC, then the process data after correction being write back raw address unit at least comprises:
Whether address register numerical value corresponding to misjudgment data is positioned at ram region, if be arranged in ram region, then from the address location that this address register indicates, take out data, writes back after correction again.
5. as claimed in claim 1 based on the jamproof storage means of ERC32 processor memory data, it is characterized in that: the process of the zeros data in this address location is at least comprised:
Address register numerical value corresponding to misjudgment data whether is arranged in ram region and whether trap register trap type value is a particular value, if be positioned at ram region and trap type value is this particular value, then by the zeros data in this address location.
6. as claimed in claim 1 based on the jamproof storage means of ERC32 processor memory data, it is characterized in that: the data after correcting are write back raw address unit and by after the zeros data in address location, also comprise the process of error count and the reset of system fault condition register.
7., based on the jamproof storage system of ERC32 processor memory data, it is characterized in that: comprising:
Unified three storing modules, three in order to data to be stored into application program argument table in RAM different address locations; Keep in the region of certain address gaps until all data are all stored in three;
Unified three get a module, in order to read the data be stored in three address locations of same data, the data in three address locations are carried out the voting that three get two, the numerical value of the data occupied the majority are covered the address location writing back the data occupied the minority;
One dislocation processing module, in order to there is the situation of a dislocation for the data in address location, is corrected by EDAC, then the data after correcting are write back raw address unit;
The wrong processing module of multidigit, in order to there is the situation of multidigit mistake for the data in address location, by the zeros data in this address location, resetting processor;
Storage unit, in order to in RAM stored in data refresh, read and detect data whether there is mistake, thus call and start the wrong processing module of a described dislocation processing module or multidigit;
Main program module, at least calls described unification three storing module of startup in order to whether to be reset according to time and processor, storage unit, unified three gets a module;
And described application program argument table.
8. as claimed in claim 7 based on the jamproof storage system of ERC32 processor memory data, it is characterized in that: also comprise internal memory initialization module, in order to carry out internal memory initialization to RAM.
9. as claimed in claim 7 based on the jamproof storage system of ERC32 processor memory data, it is characterized in that: also comprise interruption initialization module, with thinking that a described dislocation processing module and multidigit fault reason block configuration are interrupted accordingly, thus make described storage unit can by the wrong processing module of a dislocation processing module described in interrupt call and multidigit.
10. as claimed in claim 7 based on the jamproof storage system of ERC32 processor memory data, it is characterized in that: described storage unit is further in order to pass through a dislocation processing module described in interrupt call and the wrong processing module of multidigit; Described storage unit when refreshing data, further in order to:
Close and interrupt, the data reading the address location of specifying, to register, then write back in address location, then open interruption.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112181711A (en) * | 2020-09-15 | 2021-01-05 | 浙江吉利控股集团有限公司 | Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP |
| CN113849393A (en) * | 2020-06-28 | 2021-12-28 | 苏州宝时得电动工具有限公司 | Self-moving equipment and working method thereof |
| CN114090327A (en) * | 2022-01-20 | 2022-02-25 | 浙江吉利控股集团有限公司 | Single-particle error processing method, system and device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040210799A1 (en) * | 2003-04-17 | 2004-10-21 | International Business Machines Corporation | Cache directory array recovery mechanism to support special ECC stuck bit matrix |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
| CN103984630A (en) * | 2014-05-27 | 2014-08-13 | 中国科学院空间科学与应用研究中心 | Single event upset fault processing method based on AT697 processor |
-
2015
- 2015-06-23 CN CN201510354852.5A patent/CN104866387A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040210799A1 (en) * | 2003-04-17 | 2004-10-21 | International Business Machines Corporation | Cache directory array recovery mechanism to support special ECC stuck bit matrix |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
| CN103984630A (en) * | 2014-05-27 | 2014-08-13 | 中国科学院空间科学与应用研究中心 | Single event upset fault processing method based on AT697 processor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113849393A (en) * | 2020-06-28 | 2021-12-28 | 苏州宝时得电动工具有限公司 | Self-moving equipment and working method thereof |
| CN112181711A (en) * | 2020-09-15 | 2021-01-05 | 浙江吉利控股集团有限公司 | Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP |
| CN112181711B (en) * | 2020-09-15 | 2022-06-14 | 浙江吉利控股集团有限公司 | Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP |
| CN114090327A (en) * | 2022-01-20 | 2022-02-25 | 浙江吉利控股集团有限公司 | Single-particle error processing method, system and device |
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