CN112181711A - Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP - Google Patents
Error correction system and method for inhibiting single event upset by low-orbit satellite-borne DSP Download PDFInfo
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
Abstract
The application discloses an error correction system and method for inhibiting single event upset by a low-orbit satellite-borne DSP (digital signal processor). A refresh starting address and a target refresh number are written into a field programmable logic gate array by a digital signal processor; the field programmable gate array sets the digital signal processor to be in a waiting state, reads data corresponding to a refresh starting address in the static random access memory based on the refresh starting address, the data is processed by the error detection and correction module before being read, and the field programmable gate array writes the data corresponding to the refresh starting address in the static random access memory into the refresh starting address in the static random access memory; repeating the steps until the number of the data written into the static random access memory is equal to the target refreshing number; and finally, the digital signal processor is set to be in a preparation state so as to enable the digital signal processor to continue to operate, the problem of single event upset of the low-earth satellite load digital signal processor can be solved, the cost is low, and the development period is short.
Description
Technical Field
The invention relates to the field of satellite digital signal processing, in particular to an error correction system and method for inhibiting single event upset by a low-orbit satellite-borne DSP.
Background
The cosmic space has a large amount of high-energy particle radiation which mainly comes from earth radiation zones, solar electromagnetic radiation, cosmic rays and the like, and single high-energy particles enter a sensitive region of a semiconductor device to cause reaction, so that a storage unit is subjected to bit inversion, and equipment operation is abnormal. The error caused by the single event upset belongs to a soft error, namely, the system can be restored to a normal state through resetting, powering up again or rewriting.
The most easily occurring single event upset is a device which utilizes bistable state to store, such as RAM, DSP program runs in RAM without protective measures, and system working abnormity and even satellite early failure are easily caused by single event upset. When a high-energy particle impacts a programmable logic device, the energy of the impact can change the configuration data of a configurable RAM unit in the device, so that the system runs to an unpredictable state, and the whole system is caused to fail. This must be avoided in aerospace devices.
In the prior art, an antifuse PROM, a 6-chip FLASH and a military FPGA (XQV300) are used for program loading of a DSP, so that program loading errors caused by single event upset can be effectively reduced, but program abnormity caused by single event upset in the program running process can not be effectively inhibited, the problem of function interruption of a system working in orbit for a long time due to the single event effect can not be effectively solved, repeated resetting or re-electrifying is needed to keep the program running normally, and the antifuse PROM and the military FPGA are high in cost and are not suitable for satellite load systems with low-orbit satellite loads, micro-satellites and the like which are strictly controlled in cost. Or the DSP program is operated outside the chip, and the program data in the SRAM outside the chip is subjected to error check and error program recovery through the special ASIC chip, but the special ASIC chip has long early development period and high cost, has no cost advantage for satellite-borne equipment, and has weak universality and difficult upgrading and maintenance.
Disclosure of Invention
In order to solve the technical problems, the invention provides an error correction system and method for low-orbit satellite-borne single event upset, which can automatically repair a program in the running process without electrifying again, can solve the problem of single event upset of a low-orbit satellite-borne digital signal processor, and has low cost and short development period.
In order to achieve the purpose of the above application, the present application provides an error correction system for low-rail satellite-borne single event upset, which includes:
a digital signal processor, a field programmable gate array and a static random access memory;
the digital signal processor is connected with the field programmable gate array through an external memory interface line, a reset signal line and a timer signal line;
the field programmable gate array is connected with the static random access memory through a first address line, a first data line, a first control line and a first error signal line;
the static random access memory comprises a storage unit and an error detection and correction module, wherein the error detection and correction module is used for detecting whether one-bit single event upset occurs in data and correcting the upset data when the occurrence of one-bit single event upset is detected.
On the other hand, the application also provides an error correction method for low-rail satellite-borne single event upset, which is based on the error correction system for low-rail satellite-borne single event upset to correct errors, and the method comprises the following steps:
the digital signal processor writes the refresh starting address and the target refresh number into the field programmable gate array;
the field programmable gate array carries out waiting setting on the digital signal processor so as to enable the digital signal processor to enter a waiting state;
when the field programmable gate array is ready to read the data corresponding to the refresh start address in the static random access memory, controlling an error detection and correction module in the static random access memory to detect and correct the original data of the refresh start address in the static random access memory;
when the error detection and correction module detects that single-event upset of one bit occurs, correcting the upset data to obtain first target data;
the field programmable gate array reads the first target data and writes the first target data into the refresh starting address in the static random access memory;
updating the refresh starting address to obtain an updated refresh starting address;
repeating the field programmable gate array to control an error detection and correction module in the static random access memory to detect and correct the original data of the updated refresh start address in the static random access memory until the number of the first target data written into the static random access memory is equal to the target refresh number;
the field programmable gate array sets the digital signal processor to a ready state so that the digital signal processor resumes operation based on the refreshed data in the field programmable gate array. In addition, the present application also provides a storage medium, in which at least one instruction or at least one program is stored, and the at least one instruction or the at least one program is loaded and executed by a processor to implement the method of any one of the above.
The application has the following beneficial effects:
the method comprises the steps that a refreshing initial address and a target refreshing number are written into a field programmable logic gate array through a digital signal processor; the field programmable gate array carries out waiting setting on the digital signal processor so as to enable the digital signal processor to enter a waiting state; the field programmable gate array reads data corresponding to a refresh start address in the static random access memory based on the refresh start address, wherein the data corresponding to the refresh start address in the static random access memory comprises data of the static random access memory after the original data is processed by the error detection and correction module; the field programmable gate array writes data corresponding to a refresh starting address in the static random access memory into the refresh starting address in the static random access memory; adding 1 to the refresh start address to obtain a new refresh start address; the field programmable gate array reads data corresponding to the new refreshing start address in the static random access memory repeatedly based on the new refreshing start address, wherein the data corresponding to the new refreshing start address in the static random access memory comprises data of new original data in the static random access memory after being processed by the error detection and correction module until the number of the data written into the static random access memory is equal to the target refreshing number; the field programmable gate array sets the digital signal processor to be in a preparation state so that the digital signal processor can continue to operate without being electrified again, the program is automatically repaired in the operation process, the problem of single event upset of the low-earth satellite load digital signal processor can be solved, and meanwhile, the cost is low and the development period is short.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an error correction system for suppressing single event upset by a low-rail satellite-borne DSP according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an error correction system for suppressing single event upset by using a low-rail satellite-borne DSP according to another embodiment of the present application;
fig. 3 is a schematic flow chart of an error correction method for suppressing single event upset by using a low-rail satellite-borne DSP according to another embodiment of the present application;
fig. 4 is a schematic flowchart illustrating a process of processing data corresponding to a refresh start address by an error detection and correction module according to another embodiment of the present disclosure;
fig. 5 is a schematic flowchart of a system power-on loading according to another embodiment of the present application;
fig. 6 is a schematic flow chart of an error correction method for suppressing single event upset by a low-rail satellite-borne DSP according to another embodiment of the present application;
fig. 7 is a schematic flowchart illustrating a process of monitoring an abnormal state through a timer output signal according to another embodiment of the present application.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to implement the technical solution of the present application, so that more engineering workers can easily understand and apply the present application, the working principle of the present application will be further described with reference to specific embodiments.
The method and the device can be applied to the field of satellites, and correction of single event upset of the satellite-borne digital signal processor is carried out on low-earth orbit satellites or microsatellites.
First, an error correction system for suppressing single event upset by a low-rail satellite-borne DSP according to an embodiment of the present application is described below, and as shown in fig. 1, the system may include:
a DSP (Digital Signal processor) 11, an FPGA (Field Programmable Gate Array) 12, and an SRAM (Static Random Access Memory) 13. The field programmable gate array is a FLASH type FPGA (non-volatile FLASH type field programmable gate array), which is not easily affected by high-energy particles and can immunize a single event, so that a program in the field programmable gate array is not affected by the single event. The digital signal processor 11 and the field programmable gate array 12 are connected by an external memory interface line 111, a reset signal line 121, and a timer signal line 131. The fpga 12 is connected to the sram 13 through a first address line 211, a first data line 212, a first control line 213, and a first error control line 214, the sram 13 includes a storage unit 133 and an error detection and correction module 134, and the error detection and correction module 134 is configured to monitor whether a one-bit single event upset occurs in the data, and correct the data when the one-bit single event upset occurs. The sram 13 may include two parallel sram chips, and the data bit width may be expanded by the parallel connection of the two sram chips.
Specifically, the first address line 211 is used for transmitting address data between the field programmable gate array 12 and the sram 13, the first data line 212 is used for transmitting data between the field programmable gate array 12 and the sram 13, and the first control line 213 is used for transmitting control signals between the field programmable gate array 12 and the sram 13. For example, when the fpga 12 reads a datum from the sram 13, it needs to first find the address of the datum through the first address line 211, find the address of the datum enough, send a read signal through the first control line 213, and read the datum through the first data line 212. The reset signal line 121 is used for transmitting a reset signal, the timer signal line 131 is used for transmitting a timer signal between the digital signal processor 11 and the field programmable gate array 12, the digital signal processor 11 sends the timer signal to the field programmable gate array 12 at intervals, and when the timer signal is not sent within a preset time period, an exception occurs.
In particular, external memory interface lines 111 may include a third address line, a third data line, a third control line, and a hardware wait signal line. The third address line is used for transmitting address data between the digital signal processor 11 and the field programmable gate array 12, the third data line is used for transmitting data between the digital signal processor 11 and the field programmable gate array 12, and the third control line is used for transmitting control signals between the digital signal processor 11 and the field programmable gate array 12.
In particular, the field programmable gate array may further include a register. The third control line comprises a first chip select line and a second chip select line, the first chip select line is used for a chip select static random access memory of the digital signal processor, and the second chip select line is used for a register in a chip select field programmable gate array of the digital signal processor.
In a further embodiment, as shown in FIG. 2, the system may also include NOR FLASH non-volatile FLASH memory 14. The nonvolatile flash memory 14 is connected to the field programmable gate array through a second address line 141, a second data line 142, a second control line 143, and a free/busy indication signal line 144. The storage area of the non-volatile flash memory 14 may include a solidified area and a reconstructed area. The solidified region may include three modules and the reconstruction region may include three modules. The three modules of the curing zone may store the same data, and the three modules of the reconstruction zone may also store the same data. In a specific embodiment, the nonvolatile flash memory has a capacity of 16MB, and DSP program data is stored in the solid-state area and the reconstruction area before factory shipment, and stored in a three-mode manner, that is, six identical sets of DSP data are stored in three blocks of the solid-state area and three blocks of the reconstruction area, respectively, and the six sets of DSP program data are named as "DSP _ TMR 1", "DSP _ TMR 2", "DSP _ TMR 3", "DSP _ TMR 1", "DSP _ TMR 2", and "DSP _ TMR 2", respectively, and each set of DSP data is stored in a space of 2 MB. The data of the curing area is the data which can not be modified, and the data of the reconstruction area can be reconstructed by a ground station injection mode. As shown in table 1:
TABLE 1
In further embodiments, the system may further include a second error signal line. The field programmable gate array and the static random access memory are also connected through a second error signal line, and the error detection and correction module is also used for sending a second error signal to the field programmable gate array when two-bit single event upset occurs, so that the field programmable gate array controls the digital signal processor to reload data.
The following introduces an error correction method for inhibiting single event upset by a low-rail satellite-borne DSP, and the error correction method in the present application specification can be applied to the error correction system for inhibiting single event upset by a low-rail satellite-borne DSP described in any of the above embodiments.
Fig. 3 is a flowchart of an error correction method for suppressing single event upset by a low-rail satellite-borne DSP according to an embodiment of the present application, where the method may include:
s101: the digital signal processor writes the refresh start address and the target refresh number into the field programmable gate array.
Specifically, the refresh start address refers to an address at which the field programmable logic gate array starts to read data from the static random access memory in the subsequent step, and the target refresh number refers to a target number of data between a data bit number refresh start address, which is read from the static random access memory by the field programmable logic gate array, and a new refresh start address added with 1 in the subsequent step. The transmission of the refresh start address and the target refresh number may be performed through a third data line between the digital signal processor and the field programmable gate array. In the program running process, the digital signal processor selects a register in the field programmable logic gate array by setting a chip selection signal corresponding to a first chip selection line so as to trigger the refreshing operation, and the digital signal processor writes a refreshing start address and a target refreshing number into the field programmable logic gate array.
S103: the field programmable gate array performs a wait setting on the digital signal processor to cause the digital signal processor to enter a wait state.
Specifically, when the field programmable gate array reads and refreshes, the field programmable gate array sends a hardware waiting signal to the digital signal processor through the hardware waiting signal line, and controls the digital signal processor to enter a waiting state. The hardware wait signal is a level signal set in advance, and a level signal opposite to the level signal is a signal for causing the digital signal processor to enter a standby state. In a specific embodiment, the preset digital signal processor receives a low level through a hardware waiting signal line to enter a waiting state, and receives a high level to enter a preparation state, and the field programmable gate array can send a low level signal to the digital signal processor through the hardware waiting signal line in order to wait for the digital signal processor to be set.
S105: when the field programmable gate array is ready to read the data corresponding to the refresh start address in the static random access memory, the error detection and correction module in the static random access memory is controlled to detect and correct the original data of the refresh start address in the static random access memory.
Specifically, the raw data in the sram refers to data that has not been processed by the error detection and correction module, and the raw data may be data written into the sram by the solidification area or the reconstruction area during the system power-on initialization process. The original data of the refresh start address in the sram may include 32 bits of data. In addition, the non-volatile flash memory type field programmable gate array is adopted, and the field programmable gate array is not easily influenced by high-energy particles and can immunize single-particle events, so that programs in the field programmable gate array are prevented from being influenced by the single particles.
S107: and when the error detection and correction module detects that single-event upset of one bit occurs, correcting the upset data to obtain first target data.
The error detection and correction module in the static random access memory generates a check code with a certain number of bits according to the written data when the data is written into the static random access memory, and stores the check code and corresponding data in the static random access memory together. If the check code read at this time is not consistent with the check code stored in the static random access memory, the two check codes are decoded to determine which bit in the data is wrong, and then the data of the wrong bit is corrected.
When the number of the field programmable logic gate arrays in parallel connection and the number of the error detection and correction modules in the field programmable logic gate arrays in parallel connection are selected, the field programmable logic gate arrays read data of one address in the static random access memories, and can read 32 bits, namely 4 bytes of data, and the bit width of the data after the two static random access memories are connected in parallel is 32 bits. The error detection and correction module can perform error detection by adding a check code to the original data bit, and if the data bit is 8 bits, the error detection module needs to add a check code of 5 bits for error detection, wherein, every time the data bit is increased by 1 time, the error detection and correction module needs to add a check code of 1 bit. When the data bits are 16 bits, a check code of 6 bits is required. In the embodiment that two static random access memories are connected in parallel, a mode that two error detection and correction modules are connected in parallel can be adopted in a single static random access memory, namely, each error detection and correction module can correct 1 bit of errors in every 8 bits; when a 16-bit data, the upper 8 bits and the lower 8 bits each have 1-bit error, the two independent error detection and correction modules can correct the errors in the upper 8 bits and the lower 8 bits, respectively. The transmission data bit width of the single-chip static random access memory 16 bits can meet the transmission of 8-bit data bits plus 5-bit check codes. The bit width of the data after the two static random access memories are connected in parallel is 32 bits, and 4 error detection and correction modules can carry out 1-bit error correction on the data of one address of each Byte (Byte).
When the error detection and correction module detects that one-bit single event upset occurs in data corresponding to a refresh start address in the static random access memory, the one-bit data with the single event upset is corrected to obtain correct data which is used as first target data for being read by the field programmable logic gate array.
In another embodiment, the processing of the data corresponding to the refresh start address by the error detection and correction module shown in fig. 4 may include the following steps:
s1071: and the error detection and correction module detects the data of the address to be read of the field programmable gate array.
S1073: and when the single event upset of the original data of the refresh initial address in the static random access memory is not detected, the error detection and correction module outputs the original data of the refresh initial address in the static random access memory as first target data.
S1075: and when detecting that two-bit single-event upset occurs in the original data of the refreshing initial address in the static random access memory, sending a second error signal to the field programmable logic gate array so that the field programmable logic gate array controls the digital signal processor to reload the data in the curing area.
The error detection and correction module in the static random access memory generates a check code with a certain number of bits according to the written data when the data is written into the static random access memory, and stores the check code and corresponding data in the static random access memory together. If the check code read at the moment is inconsistent with the check code stored in the static random access memory, the two check codes are decoded to determine which bit in the data is wrong, and when two or more bits of single event upset occur, the calculation amount for decoding the two check codes is very large, so that when two or more bits of single event upset occur, a second error signal is directly sent to the field programmable gate array, and the field programmable gate array controls the digital signal processor to reload the data in the curing area based on the signal, so that the stability of the system can be improved.
S109: and the field programmable gate array reads the first target data and writes the first target data into the static random access memory to refresh the initial address.
Specifically, the field programmable gate array searches the refresh start address through the first address line, reads the first target data after the error detection and correction module outputs the first target data, and puts the first target data into the static flash access memory to complete the refresh of data in one address from the refresh start address.
S111: and updating the refresh start address to obtain the updated refresh start address.
Specifically, one address can store 32 bits of data. After the field programmable logic gate array finishes refreshing the data of an address in the static random access memory, the refreshing initial address in the field programmable logic gate array is added with 1, and the field programmable logic gate array searches the corresponding address in the static random access memory according to the refreshing initial address added with 1.
S113: and reading data corresponding to the new refreshing start address in the static random access memory by the field programmable gate array based on the new refreshing start address.
Specifically, the data corresponding to the new refresh start address in the sram includes data obtained by processing the new original data in the sram by the error detection and correction module. The error detection and correction module checks the new original data based on the check code.
S115: and judging whether the number of the data written into the static random access memory is equal to the target refreshing number or not.
Specifically, in the above process, the fpga reads data of an address in the sram, and then rewrites the data processed by the error detection and correction module into the address in the sram, that is, completes the refresh of the data in the address. And finishing the refreshing of the data in one address, refreshing the data in the next address, and judging the number of the data written into the static random access memory, namely whether the number of the refreshed data is equal to the target refreshing number, wherein the target refreshing number is the target refreshing number written into the field programmable gate array by the digital signal processor in the step S101.
S117: if yes, the field programmable gate array sets the digital signal processor to a preparation state, so that the digital signal processor controls the digital signal processor to recover operation based on the refreshed data in the field programmable gate array.
If not, the step S111 is executed.
Specifically, when the number of the refreshed data is equal to the target refresh number, the hardware preparation signal is sent to the digital signal processor through the hardware wait signal line. For example, it is preset that the digital signal processor receives a low level through the hardware waiting signal line to enter a waiting state and receives a high level to enter a preparation state, and when the number of data written into the static random access memory is equal to the target refresh number, the hardware waiting signal line sends a hardware preparation signal to the digital signal processor, that is, the field programmable gate array sends a high level signal to the digital signal processor. And entering the next address for data refreshing when the number of the data written into the static random access memory is less than the target refreshing number.
In the above embodiment, during the operation of the digital signal processor, the field programmable gate array controls the digital signal processor to pause for a very short time, so as to refresh data of the static random access memory, correct possible single event upset, correct all address spaces in the static random access memory, and ensure long-term reliable operation of the system.
In another embodiment, as shown in fig. 5, before the digital signal processor writes the refresh start address and the target refresh number into the field programmable gate array, the system needs to be powered on and loaded, and the specific flow is as follows:
s201: and (4) electrifying and initializing the field programmable gate array.
S203: the field programmable gate array sets the digital signal processor into a wait and reset state.
Specifically, in some embodiments, the wait/ready state signal is a dsp _ ardy signal, which is set to 0 for dsp _ ardy, i.e., to put the digital signal processor into the wait state, and the reset/release reset signal is a dsp _ reset _ n, which is set to 0 for dsp _ reset _ n, i.e., to reset the digital signal processor.
S205: and the field programmable gate array controls the corresponding addresses of the three modules of the curing area to perform three-mode comparison according to the bit positions so as to output second target data, and the three modules of the curing area are positioned in the nonvolatile flash memory.
When the non-volatile flash memory sends an idle instruction to the field programmable gate array, the current non-volatile flash memory can be controlled by the field programmable gate array and executes corresponding operation.
In further embodiments, as shown in fig. 6, the method may further include:
s204: and the digital signal processor receives the program data injected on the ground station and stores the program data into the three reconstruction area modules in the nonvolatile flash memory.
Accordingly, the step S205 may be replaced with:
s206: and the field programmable gate array controls the corresponding addresses of the three modules of the reconstruction area to perform three-mode comparison according to the bit positions so as to output second target data.
Specifically, the data in the curing area is non-modifiable data, and the program data injected on the ground station can be stored in the three reconstruction area modules of the nonvolatile flash memory. By switching the solidification region to the reconstruction region, the program data injected on the ground station can be loaded.
S207: and the field programmable gate array reads the second target data.
Specifically, the same data may be stored in three modules of the curing zone. When the field programmable gate array is ready to read data in the nonvolatile flash memory, the three modules in the curing area in the nonvolatile flash memory simultaneously execute the operation of outputting the data to be read, and the output which is the same in most of the three modules is taken as the correct output. The three modules in the curing area are mutually independent, so that the error of a fault module can be avoided by using the most same output in the three modules as correct output, the correct output of data to be read is ensured, and the fault tolerance rate of the system is greatly improved.
S209: and the field programmable gate array writes the second target data into the corresponding address of the static random access memory.
And the field programmable gate array writes the second target data into the corresponding address of the static random access memory, and the data stored in the static random access memory is used for calling between the digital signal processor and the static random access memory.
S211: and when the data in the curing area are all written into the corresponding address of the static random access memory, the field programmable logic array releases and resets the digital signal processor.
The digital signal processor after releasing the reset can load new data. When the step S205 is replaced with the step S206, the data of the solidified area in S211 is replaced with the data of the reconstructed area accordingly.
S213: after the preset time, the field programmable gate array sets the digital signal processor to a preparation state, so that the digital signal processor and the field programmable gate array establish communication through an external memory interface line.
S215: the digital signal processor completes the loading of the data based on the communication established by the external memory interface line.
In particular, the external memory interface lines may include a first chip select line for the dsp chip select sram and a second chip select line for a register in the dsp chip select fpga. The digital signal processor can read the data in the static random access memory by using the first chip select line and can also read the data in the field programmable gate array by using the second chip select line.
In the above embodiment, the solidified area or the reconstructed area in the nonvolatile flash memory performs three-mode comparison by using three respective modules storing the same data to output the second target data, the field programmable gate array reads the second target data, and then communication between the digital signal processor and the field programmable gate array is established to complete data loading of the digital signal processor, so that an error of a faulty module can be avoided, correct output of data to be read is ensured, and the fault tolerance of the system is greatly improved.
In further embodiments, as shown in fig. 7, the method may further include:
s301: the field programmable gate array detects a timer output signal of the digital signal processor.
In particular, a timer may be included in the digital signal processor, the timer being configured to generate a timer output signal.
S303: when the field programmable gate array does not detect the timer output signal of the digital signal processor in the first preset time period, the running state of the digital signal processor is recorded to be an abnormal state, and the digital signal processor is controlled to be reloaded.
Specifically, when the digital signal processor works normally, the timer outputs a timer signal to the field programmable gate array at intervals. The interval time of the output signal can be set in advance to obtain a first preset time period, and when the field programmable logic gate array does not detect the timer signal output by the digital signal processor in the first preset time period, the running state of the digital signal processor is recorded to be an abnormal state.
S305: and when the frequency of the abnormal state of the digital signal processor in the second preset time period meets the preset condition, the field programmable gate array controls the digital signal processor to switch the loading area for loading, wherein the switching area comprises a curing area and a reconstruction area.
Specifically, the second preset time period is longer than the first preset time period, for example, the first preset time period may be set to 8 seconds, and the second preset time period is set to 5 minutes, so that within 8 seconds, the field programmable gate array does not receive the timer output signal output by the digital signal processor, that is, an abnormal state occurs, and at this time, the digital signal processor is reloaded. When 4 dog bites occur within 5 minutes, the digital signal processor switches the curing zone to the reconstruction zone or switches the reconstruction zone to the curing zone for reloading.
As can be seen from the above embodiments, the present application writes the refresh start address and the target refresh number into the field programmable gate array through the digital signal processor; the field programmable gate array carries out waiting setting on the digital signal processor so as to enable the digital signal processor to enter a waiting state; the field programmable gate array reads data corresponding to a refresh start address in the static random access memory based on the refresh start address, wherein the data corresponding to the refresh start address in the static random access memory comprises data of the static random access memory after the original data is processed by the error detection and correction module; the field programmable gate array writes data corresponding to a refresh starting address in the static random access memory into the refresh starting address in the static random access memory; adding 1 to the refresh start address to obtain a new refresh start address; the field programmable gate array reads data corresponding to the new refreshing start address in the static random access memory repeatedly based on the new refreshing start address, wherein the data corresponding to the new refreshing start address in the static random access memory comprises data of new original data in the static random access memory after being processed by the error detection and correction module until the number of the data written into the static random access memory is equal to the target refreshing number; the field programmable gate array sets the digital signal processor to be in a preparation state, so that the digital signal processor continues to operate without being electrified again, the program can be automatically repaired in operation, the problem of single event upset of the low-earth satellite load digital signal processor can be solved, and meanwhile, the cost is low and the development period is short.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that although embodiments described herein include some features included in other embodiments, not other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims of the present invention, any of the claimed embodiments may be used in any combination.
The present invention may also be embodied as apparatus or system programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website, provided on a carrier signal, or provided in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps or the like not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering and these words may be interpreted as names.
Claims (10)
1. An error correction system for inhibiting single event upset by a low-rail satellite-borne DSP (digital signal processor), the system comprising:
a digital signal processor, a field programmable gate array and a static random access memory;
the digital signal processor is connected with the field programmable gate array through an external memory interface line, a reset signal line and a timer signal line;
the field programmable logic gate array is connected with the static random access memory through a first address line, a first data line, a first control line and a first error signal line, and is a nonvolatile flash memory type field programmable logic gate array;
the static random access memory comprises a storage unit and an error detection and correction module, wherein the error detection and correction module is used for detecting whether one-bit single event upset occurs in data and correcting the upset data when the occurrence of one-bit single event upset is detected.
2. The system of claim 1, wherein the system further comprises a non-volatile flash memory;
the nonvolatile flash memory is connected with the field programmable logic gate array through a second address line, a second data line, a second control line and a free/busy indication signal line;
the storage area of the nonvolatile flash memory comprises a curing area and a reconstruction area;
the curing area comprises three modules, and the three modules of the curing area store the same data;
the reconstruction area comprises three modules, and the three modules of the reconstruction area store the same data.
3. The system of claim 2, further comprising a second error signal line;
the field programmable gate array and the static random access memory are also connected through the second error signal line, and the error detection and correction module is also used for sending a second error signal to the field programmable gate array when two-bit single event upset occurs, so that the field programmable gate array controls the digital signal processor to reload data.
4. The system in accordance with claim 1, wherein the external memory interface line comprises:
a third address line, a third data line, a third control line and a hardware wait signal line; address information is transmitted between the digital signal processor and the field programmable gate array through the third address line, and data is transmitted through the third data line;
the digital signal processor chip selects the SRAM by using the third control line.
5. The system of claim 4, wherein the field programmable gate array further comprises a register;
correspondingly, the digital signal processor also selects the register by using the third control line.
6. An error correction method for inhibiting single event upset by a low-rail satellite-borne DSP (digital signal processor), which is characterized in that error correction is carried out based on the error correction system of any one of claims 1 to 5, and the method comprises the following steps:
the digital signal processor writes the refresh starting address and the target refresh number into the field programmable gate array;
the field programmable gate array carries out waiting setting on the digital signal processor so as to enable the digital signal processor to enter a waiting state;
when the field programmable gate array is ready to read the data corresponding to the refresh start address in the static random access memory, controlling an error detection and correction module in the static random access memory to detect and correct the original data of the refresh start address in the static random access memory;
when the error detection and correction module detects that single-event upset of one bit occurs, correcting the upset data to obtain first target data;
the field programmable gate array reads the first target data and writes the first target data into the refresh starting address in the static random access memory;
updating the refresh starting address to obtain an updated refresh starting address;
repeating the field programmable gate array to control an error detection and correction module in the static random access memory to detect and correct the original data of the updated refresh start address in the static random access memory until the number of the first target data written into the static random access memory is equal to the target refresh number;
the field programmable gate array sets the digital signal processor to a ready state so that the digital signal processor resumes operation based on the refreshed data in the field programmable gate array.
7. The method of claim 6, wherein before the digital signal processor writes the refresh start address and the target refresh number into the field programmable gate array, the method further comprises:
the field programmable gate array is electrified and initialized;
the field programmable gate array sets the digital signal processor to a waiting and resetting state;
the field programmable gate array controls the corresponding addresses of the three modules of the curing area to carry out three-mode comparison according to bit positions so as to output second target data, and the three modules of the curing area are positioned in the nonvolatile flash memory;
the field programmable gate array reads the second target data;
the field programmable gate array writes the second target data into an address corresponding to the static random access memory;
when the total data of the curing area is written into the corresponding address of the static random access memory, the field programmable logic array controls the digital signal processor to release reset;
after the preset time, the field programmable logic gate array sets the digital signal processor to be in a preparation state, so that the digital signal processor and the field programmable logic gate array establish communication through an external memory interface line;
the digital signal processor completes the loading of data based on the communication established by the external memory interface line.
8. The method of claim 7, further comprising:
the digital signal processor receives a program injected on a ground station and stores the program injected on the ground station into three reconstruction area modules in the nonvolatile flash memory;
correspondingly, the field programmable gate array controls the addresses corresponding to the three modules of the curing area to perform three-module comparison according to the bit positions so as to output second target data, and the second target data is replaced by:
the field programmable gate array controls the corresponding addresses of the three modules of the reconstruction area to carry out three-mode comparison according to bit positions so as to output second target data;
the field programmable gate array reads the second target data.
9. The method of claim 7, further comprising:
the error detection and correction module detects the data of the address to be read of the field programmable gate array;
when the single event upset of the original data of the refresh start address in the static random access memory is not detected, the error detection and correction module outputs the original data of the refresh start address in the static random access memory as the first target data;
and when detecting that two-bit single event upset occurs in the original data of the refresh start address in the static random access memory, sending a second error signal to the field programmable logic gate array so as to enable the field programmable logic gate array to control the digital signal processor to reload the data of the curing area.
10. The method of claim 7, further comprising:
the field programmable gate array detects a timer output signal of the digital signal processor;
when the field programmable gate array does not detect the timer output signal of the digital signal processor in a first preset time period, recording the running state of the digital signal processor as an abnormal state, and controlling the digital signal processor to reload;
and when the times of the abnormal state of the digital signal processor in a second preset time period meet a preset condition, the field programmable logic gate array controls the digital signal processor to switch a loading area for loading, wherein the switching area comprises the curing area and the reconstruction area.
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