CN104021051A - Monitoring and correcting device for single event upset fault of satellite borne spread spectrum responder - Google Patents
Monitoring and correcting device for single event upset fault of satellite borne spread spectrum responder Download PDFInfo
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- CN104021051A CN104021051A CN201410248359.0A CN201410248359A CN104021051A CN 104021051 A CN104021051 A CN 104021051A CN 201410248359 A CN201410248359 A CN 201410248359A CN 104021051 A CN104021051 A CN 104021051A
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Abstract
The invention discloses a monitoring and correcting device for a single event upset fault of a satellite borne spread spectrum responder. The monitoring and correcting device is used for monitoring and correcting a communication processing module of the satellite borne spread spectrum responder. The monitoring and correcting device is characterized by comprising an anti-fuse FPGA circuit, a watchdog circuit and an AND gate logic circuit, the anti-fuse FPGA circuit is used for conducting backward reading, backward reading information comparing and heavy load judging on the configuration information of the communication processing module and used for sending first heavy load signals to the AND gate logic circuit, the watchdog circuit is used for sending second heavy load signals to the AND gate logic circuit according to feed dog signals sent by the communication processing module, and the AND gate logic circuit is used for conducting AND logic operation on the received first heavy load signals and the received second heavy load signals and sending heavy load enabling signals to the communication processing module according to AND results.
Description
Technical field
The invention belongs to the anti-single particle overturn reinforcement design technology field of space flight aerospace product, be specifically related to a kind of monitoring and correcting device for spaceborne spread spectrum answering machine single-particle inversion fault.
Background technology
Spread spectrum answering machine has played abnormal important Link role in space flight measurement and control, receives up survey signal and completes range finding, speed measuring function, receives up remote signal, converting downlink telesignalisation and in-hole run signal.The major function of spread spectrum answering machine is by channel signal processing modules implement, channel signal processing module function is by based on static RAM (Static RAM, SRAM) extensive 6,000,000 field programmable gate arrays (Field-Programmable Gate Array, FPGA) XQR2V6000-4CF1144H completes.
SRAM type FPGA is a kind of to adopt the SRAM structure of CMOS technique as the FPGA of storage unit, there is the advantages such as capacity is large, cost of development is low, the construction cycle is short, aerospace also has certain anti-integral dose radiation ability with SRAM type FPGA, and to single event latch-up immunity, therefore, SRAM type FPGA is widely used in astrionic system design.But, the SRAM type FPGA single-particle inversion effect sensitivity that incident causes for high energy particle.Single-particle inversion occurs in FPGA internal configurations storer, may cause FPGA internal logic function to change, and may directly affect the realization of electronic system function.Therefore, SRAM type FPGA must take certain safeguard procedures while being applied in space radiation environment, to ensure that electronic system function is not subject to the impact of single-particle inversion.It is exactly a kind of effectively anti-single particle overturn measure that FPGA internal configurations storer is carried out to retaking of a year or grade comparison.
Current spaceborne spread spectrum answering machine is in orbit applied based on 1,000,000 aerospace level FPGA of SRAM type, does not take system-level program control command reset measure, and the performance index decline that single-particle inversion causes can occur unit, and even partial function lost efficacy.Spread spectrum answering machine, as the bridge of communicating by letter between star ground, must take effective measures in unit conceptual design, guarantees that star ground communication function is normal.
Summary of the invention
In order to overcome the defect existing in prior art, the invention provides a kind of monitoring and correcting device for spaceborne spread spectrum answering machine single-particle inversion fault, concrete technical scheme is as follows:
For monitoring and the correcting device of spaceborne spread spectrum answering machine single-particle inversion fault, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, it is characterized in that, described monitoring and correcting device comprise:
Anti-fuse FPGA circuit, for the configuration information of Communications Processor Module being carried out to retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement, and sends the first override signal to described AND gate;
Watchdog circuit, for the feeding-dog signal sending according to described Communications Processor Module, sends the second override signal to described AND gate;
AND gate, for the first override signal receiving and the second override signal are carried out with logical operation, and according to result send heavily loaded enable signal to described communication module.
As prioritization scheme, described anti-fuse FPGA circuit further comprises:
Command analysis module, exports to retaking of a year or grade control module for outside being inputted after instruction is resolved; Described outside input instruction comprises that retaking of a year or grade allows instruction, retaking of a year or grade inhibit command, reset instruction;
CRC check module, for retaking of a year or grade information described in buffer memory and retaking of a year or grade information is carried out to CRC check calculating, compares with preset CRC check value, and check results is exported to retaking of a year or grade control module;
Retaking of a year or grade control module, for arranging corresponding state according to outside input instruction; Under retaking of a year or grade enable state, every Preset Time interval, described Communications Processor Module is sent it back to read control signal and start retaking of a year or grade, judge whether heavy duty according to described check results, described the first override signal is sent to described AND gate; Under retaking of a year or grade illegal state, stop sending it back the operation of read control signal; All storage information zero clearing under reset mode, all arrangement reset also quit work, and the first override signal is sent to described AND gate; In real time instruction response condition in retaking of a year or grade control module and current duty are write to remote measurement and return to module;
Module is returned in remote measurement, for the job information including instruction response condition and current duty is sent to described Communications Processor Module;
And timer module, writes and once answers permission signal described retaking of a year or grade control module for timing and every Preset Time interval.
As prioritization scheme, described Communications Processor Module comprises a FPGA circuit and PROM chip;
Described FPGA circuit, produces the feeding-dog signal of lasting clock signal as watchdog circuit, supports retaking of a year or grade function, receives heavily loaded enable signal, fetch program configuration file from described PROM chip;
PROM chip, storage program configuration file, is the mode of operation of disposable fusing.
The monitoring of single-particle inversion fault and a correcting method, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, is characterized in that, described monitoring and correcting method comprise the steps:
A: anti-fuse FPGA circuit carries out retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement to the configuration information of Communications Processor Module, and sends the first override signal to described AND gate;
B: the feeding-dog signal that watchdog circuit sends according to described Communications Processor Module, sends the second override signal to described AND gate;
C: AND gate by steps A send the first override signal and step B the second override signal carry out with logical operation, and according to result send heavily loaded enable signal to described communication module.
As prioritization scheme, described steps A is specially:
Anti-fuse FPGA circuit arranges status information operation response according to outside input instruction;
Under retaking of a year or grade enable state: anti-fuse FPGA circuit carries out retaking of a year or grade to the configuration information of Communications Processor Module, obtain retaking of a year or grade information; Described retaking of a year or grade information is carried out to CRC check calculating, compare with preset CRC check value, obtain comparison result; When comparison result is while being correct, the first override signal sending to AND gate is high level, not heavily loaded; In the time that comparison result is mistake, the first override signal sending to AND gate is low level, heavy duty;
Under retaking of a year or grade illegal state: anti-fuse FPGA circuit stops the operation of retaking of a year or grade control signal and the transmission of the first override signal;
Under reset mode: the zero clearing of retaking of a year or grade information, all arrangement reset, stop retaking of a year or grade operation the first override signal.
As prioritization scheme, described step B is specially:
The feeding-dog signal that watchdog circuit received communication processing module sends, normal if described feeding-dog signal sends, the second override signal sending to AND gate is high level, not heavily loaded; If described feeding-dog signal sends abnormal, the second override signal sending to AND gate is low level, heavy duty.
As prioritization scheme, described step C is specially:
The first override signal that AND gate sends described steps A and described step B the second override signal carry out with logical operation, obtain heavily loaded enable signal; Heavily loaded enable signal is sent to described Communications Processor Module; When heavily loaded enable signal is high level, be not heavily loaded; When heavily loaded enable signal is low level, be heavy duty.
As prioritization scheme, described anti-fuse FPGA circuit sends to described Communications Processor Module by the job information including instruction response condition and current duty in real time.
Compared with prior art, the present invention has following beneficial effect:
The present invention can realize the monitoring to spaceborne spread spectrum answering machine Communications Processor Module, find in time and correct the single-particle inversion that high energy particle incident causes, the problem such as spaceborne spread spectrum answering machine performance index decline or partial function inefficacy of effectively having avoided single-particle inversion to cause, has guaranteed that star ground communication function is normal.The present invention has good versatility, and the monitoring software relating to has good portability.Secondly, the present invention can be applied to designing and developing of the similar unit product of aerospace model, improves the anti-single particle overturn ability of unit, meets the mission requirements that power up for a long time in-orbit work, and can effectively shorten the cycle of designing and developing and cost.
Brief description of the drawings
Fig. 1 is principle composition frame chart of the present invention;
Fig. 2 is anti-fuse FPGA circuit practical function block diagram of the present invention;
Fig. 3 is single-particle monitoring of the present invention and corrects the logic diagram that function realizes.
Embodiment
Describe the present invention below in conjunction with accompanying drawing in detail in the mode of embodiment.
As shown in Figure 1, a kind of monitoring and correcting device for spaceborne spread spectrum answering machine single-particle inversion fault, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, is characterized in that, described monitoring and correcting device comprise:
Anti-fuse FPGA circuit, for the configuration information of Communications Processor Module being carried out to retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement, and sends the first override signal to described AND gate;
Watchdog circuit, for the feeding-dog signal sending according to described Communications Processor Module, sends the second override signal to described AND gate;
AND gate, for the first override signal receiving and the second override signal are carried out with logical operation, and according to result send heavily loaded enable signal to described communication module.
The monitoring of single-particle inversion fault and a correcting method, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, is characterized in that, described monitoring and correcting method comprise the steps:
A: anti-fuse FPGA circuit carries out retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement to the configuration information of Communications Processor Module, and sends the first override signal to described AND gate;
B: the feeding-dog signal that watchdog circuit sends according to described Communications Processor Module, sends the second override signal to described AND gate;
C: AND gate by steps A send the first override signal and step B send the second override signal carry out with logical operation, and according to result send heavily loaded enable signal to described communication module.
The Communications Processor Module of this device and spaceborne spread spectrum answering machine is arranged in same printed board, realize SRAM type FPGA circuit working monitoring running state and correction to Communications Processor Module, when overturning in the application configuration district that monitors SRAM type FPGA circuit, carrying out immediately that program reshuffles is described heavy duty, makes SRAM type FPGA circuit return to normal duty.
What the watchdog circuit in the present embodiment adopted is IS9-705RH-Q model watchdog circuit, and anti-fuse FPGA circuit is selected the A54SX72A-CQ208B type product of ACTEL company, can meet the positive sample installation of aerospace model request for utilization.
As shown in Figure 2, in the present embodiment, anti-fuse FPGA circuit further comprises:
Command analysis module, exports to retaking of a year or grade control module for outside being inputted after instruction is resolved; Described outside input instruction comprises that retaking of a year or grade allows instruction, retaking of a year or grade inhibit command, reset instruction;
CRC check module, for retaking of a year or grade information described in buffer memory and retaking of a year or grade information is carried out to CRC check calculating, compares with preset CRC check value, and check results is exported to described retaking of a year or grade control module;
Retaking of a year or grade control module, for arranging corresponding state according to outside input instruction; Under retaking of a year or grade enable state, every 30 minutes, described Communications Processor Module is sent it back to read control signal and start retaking of a year or grade, judge whether heavy duty according to described check results, described the first override signal is sent to described AND gate; Under retaking of a year or grade illegal state, stop sending it back read control signal, the first override signal of transmission is not for heavily loaded; All storage information zero clearing under reset mode, all arrangement reset, the first override signal of transmission is heavy duty; In real time instruction response condition in retaking of a year or grade control module and current duty are write to remote measurement and return to module;
Module is returned in remote measurement, for the job information of anti-fuse FPGA circuit is exported to described Communications Processor Module with binary coding; Described job information specifically comprises again: whether allow retaking of a year or grade, whether single-particle inversion and the CRC comparison number of times of makeing mistakes occurs.
And, timer module, for timing, the present embodiment is set as and every 30 minutes, described retaking of a year or grade control module is write once to answer and allows signal.
Described retaking of a year or grade control signal comprises chip selection signal and enable signal.
The specific works method of installing described in the present embodiment is described below in conjunction with Fig. 2, Fig. 3.
Command analysis module in anti-fuse FPGA circuit is inputted instruction by outside and is resolved to corresponding sequential.
The duty of this device is determined by outside input instruction: in the time that outside input instruction is reset, this device is operated in reset mode; In the time that outside input instruction is retaking of a year or grade inhibit command, this device is operated in retaking of a year or grade illegal state; In the time that outside input instruction is retaking of a year or grade permission instruction, this device is operated in retaking of a year or grade enable state, and immediately startup read back waveform is set high to level once in the time first retaking of a year or grade enable state being set.
The priority of wherein, forbidding read-back order is higher than allowing read-back order.
In the time installing in reset mode, the retaking of a year or grade information of buffer memory in zero clearing CRC check module, all arrangement reset in anti-fuse FPGA circuit, stop sending it back read control signal, and the first override signal of transmission is heavy duty.Now, no matter whether watchdog circuit occurs that extremely, AND gate all can send low level enable signal PROG_B, make the SRAM type FPGA circuit heavy duty of communication module.
When device is during in retaking of a year or grade illegal state, equally with reset mode stop sending it back read control signal, the first override signal of transmission is for heavily loaded, but not zero clearing of retaking of a year or grade information to buffer memory in CRC check module, and configuration in anti-fuse FPGA circuit does not reset.Now only depend on watchdog circuit to monitor the Communications Processor Module of spaceborne spread spectrum answering machine, only have in the time that feeding-dog signal occurs extremely causing watchdog circuit to send low level the second override signal, AND gate just can send low level enable signal PROG_B, makes the SRAM type FPGA circuit heavy duty of Communications Processor Module.
In the time installing the state allowing in retaking of a year or grade, while meeting retaking of a year or grade condition a, b, start retaking of a year or grade:
Retaking of a year or grade condition a, the SRAM type FPGA circuit output done signal of communication module is high level;
Retaking of a year or grade condition b, startup read back waveform is high level.
While being set to first allow retaking of a year or grade state, immediately the startup read back waveform in retaking of a year or grade control module is set high to level once.
Start retaking of a year or grade, timer starts timing, produces a clock signal afterwards send to retaking of a year or grade control module every 30 minutes, makes retaking of a year or grade control module that startup read back waveform is set high to level once.
The SRAM type FPGA circuit output done signal of described communication module is high level, is heavy duty success; When heavy duty failure, done signal remains low level, and SRAM type FPGA circuit is automatically again heavily loaded until heavy duty success.SRAM type FPGA circuit is switched on first and is just read immediately the application configuration file of storing in PROM, now completes first heavy duty success, and done signal is high level.
Start retaking of a year or grade, first retaking of a year or grade control module sends it back read control signal to SRAM type FPGA circuit, and SRAM type FPGA circuit is opened retaking of a year or grade process; The internal configuration information of SRAM type FPGA circuit is now deposited in CRC check module as described retaking of a year or grade information; CRC check module is calculated corresponding CRC check value to retaking of a year or grade information, compares with preset CRC check value; Comparison result is exported to retaking of a year or grade control module.
When comparison result is correct, there is not single-particle inversion in SRAM type FPGA circuit, and internal configurations is not made mistakes, and the first override signal of retaking of a year or grade control module output is high level, not heavily loaded.
When comparison result is mistake, there is single-particle inversion in SRAM type FPGA circuit, and internal configurations is made mistakes, and the first override signal of retaking of a year or grade control module output is low level, heavy duty.
Under retaking of a year or grade enable state the enable signal PROG_B of AND gate output be described the first override signal and the second override signal phase and result.
Remote measurement is returned to module and in real time the job information of anti-fuse FPGA circuit is exported to SRAM type FPGA circuit, and SRAM type FPGA circuit will send to digital quantity telemetry-acquisition unit after the job information of anti-fuse FPGA circuit and the duty of himself integration.
The present invention has good versatility, and the monitoring software relating to has good portability.The present invention can be applied to designing and developing of the similar unit product of aerospace model, improves the anti-single particle overturn ability of unit, meets the mission requirements that power up for a long time in-orbit work, and can effectively shorten the cycle of designing and developing and cost.
Disclosed is above only the application's a specific embodiment, but the application is not limited thereto.The changes that any person skilled in the art can think of, all should drop in the application's protection domain.
Claims (8)
1. for monitoring and the correcting device of spaceborne spread spectrum answering machine single-particle inversion fault, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, it is characterized in that, described monitoring and correcting device comprise:
Anti-fuse FPGA circuit, for the configuration information of Communications Processor Module being carried out to retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement, and sends the first override signal to described AND gate;
Watchdog circuit, for the feeding-dog signal sending according to described Communications Processor Module, sends the second override signal to described AND gate;
AND gate, for the first override signal receiving and the second override signal are carried out with logical operation, and according to result send heavily loaded enable signal to described Communications Processor Module.
2. a kind of monitoring and correcting device for spaceborne spread spectrum answering machine single-particle inversion fault as claimed in claim 1, is characterized in that, described anti-fuse FPGA circuit further comprises:
Command analysis module, exports to retaking of a year or grade control module for outside being inputted after instruction is resolved; Described outside input instruction comprises that retaking of a year or grade allows instruction, retaking of a year or grade inhibit command, reset instruction;
CRC check module, for retaking of a year or grade information described in buffer memory and retaking of a year or grade information is carried out to CRC check calculating, compares with preset CRC check value, and check results is exported to retaking of a year or grade control module;
Retaking of a year or grade control module, for arranging corresponding state according to outside input instruction; Under retaking of a year or grade enable state, every Preset Time interval, described Communications Processor Module is sent it back to read control signal and start retaking of a year or grade, judge whether heavy duty according to described check results, described the first override signal is sent to described AND gate; Under retaking of a year or grade illegal state, stop sending it back read control signal, the first override signal of transmission is not for heavily loaded; All storage information zero clearing under reset mode, all arrangement reset, the first override signal of transmission is heavy duty; Every Preset Time interval, instruction response condition in retaking of a year or grade control module and current duty are write to remote measurement and return to module;
Module is returned in remote measurement, for the job information including instruction response condition and current duty is sent to described Communications Processor Module;
And timer module, once returns read enable signal for timing and every Preset Time interval to described retaking of a year or grade control module output.
3. a kind of monitoring and correcting device for spaceborne spread spectrum answering machine single-particle inversion fault as claimed in claim 1, is characterized in that, described Communications Processor Module comprises a FPGA circuit and PROM chip;
Described FPGA circuit, produces the feeding-dog signal of lasting clock signal as watchdog circuit, supports retaking of a year or grade function, receives heavily loaded enable signal, fetch program configuration file from described PROM chip;
PROM chip, storage program configuration file, is the mode of operation of disposable fusing.
4. the monitoring of single-particle inversion fault and a correcting method, for the Communications Processor Module of spaceborne spread spectrum answering machine is monitored and corrected, is characterized in that, described monitoring and correcting method comprise the steps:
A: anti-fuse FPGA circuit carries out retaking of a year or grade, the comparison of retaking of a year or grade information, heavy duty judgement to the configuration information of Communications Processor Module, and sends the first override signal to described AND gate;
B: the feeding-dog signal that watchdog circuit sends according to described Communications Processor Module, sends the second override signal to described AND gate;
C: AND gate by steps A send the first override signal and step B the second override signal carry out with logical operation, and according to result send heavily loaded enable signal to described Communications Processor Module.
5. the monitoring of a kind of single-particle inversion fault as claimed in claim 4 and correcting method, is characterized in that, described steps A is specially:
Anti-fuse FPGA circuit arranges status information operation response according to outside input instruction;
Under retaking of a year or grade enable state: anti-fuse FPGA circuit carries out retaking of a year or grade to the configuration information of Communications Processor Module, obtain retaking of a year or grade information; Described retaking of a year or grade information is carried out to CRC check calculating, compare with preset CRC check value, obtain comparison result; When comparison result is while being correct, the first override signal sending to AND gate is high level, not heavily loaded; In the time that comparison result is mistake, the first override signal sending to AND gate is low level, heavy duty;
Under retaking of a year or grade illegal state: anti-fuse FPGA circuit stops sending it back read control signal, and the first override signal of transmission is not for heavily loaded;
Under reset mode: the zero clearing of all storage information, all arrangement reset also stop sending it back read control signal, and the first override signal of transmission is heavy duty.
6. the monitoring of a kind of single-particle inversion fault as claimed in claim 4 and correcting method, is characterized in that, described step B is specially:
The feeding-dog signal that watchdog circuit received communication processing module sends, normal if described feeding-dog signal sends, the second override signal sending to AND gate is high level, not heavily loaded; If described feeding-dog signal sends abnormal, the second override signal sending to AND gate is low level, heavy duty.
7. monitoring and the correcting method of a kind of single-particle inversion fault as described in claim 4 or 5 or 6, is characterized in that, described step C is specially:
The first override signal that AND gate sends described steps A and described step B the second override signal carry out with logical operation, obtain heavily loaded enable signal; Heavily loaded enable signal is sent to described Communications Processor Module; When heavily loaded enable signal is high level, be not heavily loaded; When heavily loaded enable signal is low level, be heavy duty.
8. the monitoring of a kind of single-particle inversion fault as claimed in claim 4 and correcting method, it is characterized in that, described anti-fuse FPGA circuit sends to described Communications Processor Module by the job information including instruction response condition and current duty in real time.
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