CN102779079B - Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time - Google Patents
Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time Download PDFInfo
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Abstract
The invention relates to a configuration method and system used for a satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for a long time. The method comprises the following steps: electrification: a delay configuration strategy is adopted for the FPGA to avoid configuration errors caused by power supply fluctuation generated at the moment of the boot; configuration process monitoring: the configuration condition of the FPGA is monitored by a DSP (Digital Signal Processor), and when the configuration of the FPGA is monitored to be normally completed, the FPGA is informed of entering a normal measurement state by the DSP, and an on-line reconfiguration step is started if the configuration of the FPGA is monitored to be not completed in time; reconfiguration: a low-level pulse larger than 300ns is controlled to be applied to a configuration reset pin of the FPGA by the DSP under the condition of uninterruptible power supply, and then the configuration process is automatically completed by the FPGA; normal working process monitoring: whether the configuration of the FPGA is correct or not is monitored regularly by the DSP in a normal working process, and FPGA on-line reconfiguration is started by the DSP if the configuration of the FPGA is wrong; and regular reconfiguration: a triple modular redundancy design is adopted for the FPGA, and is matched with the regular reconfiguration to improve the reliability of the FPGA.
Description
Technical field
The present invention relates to SRAM type FPGA for satellite borne equipment, configuration and the Monitoring Design of FPGA in the anti-single particle Design of Reinforcement while being operated in the high radiation environment of space, be specifically related to collocation method and the system of a kind of spaceborne SRAM type FPGA for long-term operation on orbit.
Background technology
Spaceborne radar altitude gauge is a kind of active microwave remote sensor, and it can realize the effective measurement to sea level height, sea significant wave height, backscattering from ocean surfaces coefficient and sea wind speed.The further inverting of these data be can be applicable to the research of the aspects such as marine geophysics, ocean dynamics, marine climatology and the detection of utmost point ice.
HY-2 radar altimeter is dual-frequency radar, there are two wave bands of Ku and C, numerical control unit adopt this SRAM type of the 2V3000 FPGA of the Virtex II series of Xilinx company realize to the switching sequence of the transmitter unit of whole altitude gauge system, microwave front end, power amplifier etc. control, receiver gain is controlled, echoed signal collection follow the tracks of processing, the important task such as platform and ground communication via satellite by DSP, and in-orbit, belong to long-term uninterrupted operation, so the High Reliability Design of FPGA is related to the safety of whole system.But this SRAM type FPGA is single-particle Sensitive Apparatus, the data providing according to the official website of the said firm and the domestic anti-irradiation test result to this device, this device is operated on this track of this about 960Km of HY-2 satellite, meet with about 4-6 time of single event every day, therefore anti-/ (alleviation) single particle effect is an importance that needs concern in FPGA reliability design.
SRAM type FPGA is not the i.e. operation that powers on, but needs the first configuration RAM from PROM loading procedure to FPGA.Configured and just entered duty afterwards, and FPGA electrify restoration circuit (POR:power on reset) is the responsive part of single event function interrupt (SEFI), the layoutprocedure that powers on may lose efficacy; Although the probability that SEFI occurs is extremely low, once the impact causing is very serious, so works in the design of satellite borne equipment of space environment and also need emphasis consideration.FPGA for uphole equipment does not generally need the configuration successful of FPGA whether to monitor.Because as long as circuit and system are reasonable, there is not the unsuccessful problem of configuration, simultaneously owing to not needing to consider single particle effect, therefore needn't do triplication redundancy and reshuffle design.
Single-particle inversion (SEU) refers to that high energy particle is beaten and on key node, causes storage unit bit flipping, for SRAM type FPGA, the position that single-particle inversion occurs comprises the bit flipping of the config memory of FPGA, register itself, lut memory, BlockRAM storer etc.Single event transient pulse (SET) is because high energy particle produces the input that a transient current pulse has influence on next stage logical circuit on routing path, causes this logical circuit output disorderly.SET causes the moment mistake of FPGA internal logic circuit, and its impact is also equivalent to SEU one time.SEU and SET are the two class single particle effects that occurrence frequency is higher.
Prior art adopts the mode of " triplication redundancy design+is regularly reshuffled " effectively to alleviate SEU.Triplication redundancy design philosophy is that same function little module is copied into three parts, then is exported by voting machine, if wherein two parts normal, whole logic function is exactly correct; And what regularly reshuffle solution is the problem of error accumulation; Work at present the FPGA of space environment, more or less all include triplication redundancy design; For the FPGA that belongs to the work of short-term discontinuity during in-orbit, be anti-single particle effect, should do triplication redundancy design, but not need to be designed to regularly reshuffle; This is because for the FPGA of the discontinuity start work of short-term, and because an on time is shorter, in the work period, three parts of same logical block generation single-particle inversions are unlikely accumulated to 2 parts and cause output error.And for the FPGA of long-term work during in-orbit, three parts of same logical blocks make a mistake and may be accumulated to 2 parts, finally cause this functional unit mistake so that whole system to make a mistake.Therefore, regularly reshuffle the accumulation problem of energy solving error.But existing reconfiguration technology generally realizes by sending out program control command, and function is not reshuffled in some design, if find, single particle effect can only close equipment, start shooting to eliminate.Can greatly reduce like this long-term work in-orbit containing the automatization level of the equipment of this SRAM type FPGA, repeated switching increases the frequency of utilization to relay simultaneously.Triplication redundancy design resource overhead is large, but concerning working in the satellite borne equipment of space environment, and first reliability will consider, it is necessary adopting and exchanging reliability for more resource.
Summary of the invention
The object of the invention is to, for the mistake of alleviation at the single particle effect of the FPGA generation of the SRAM type of the employing triplication redundancy design of the high radiation environment long-term work of space adds up, the invention provides a kind of method that FPGA regularly reshuffles and its configuring condition is monitored, when monitoring, configuration fails to complete on schedule or start in time online reconfiguration when normal work period occurs configuration error; Simultaneously the present invention also adopts a kind of means of upper electric delay configuration to overcome the problem that configuration error that booting moment power-supply fluctuation causes occurs.The SRAM type FPGA reliability effectively having improved in the high radiation environment long-term work of space, the invention provides collocation method and the system of a kind of spaceborne SRAM type FPGA for long-term operation on orbit.
For achieving the above object, the present invention adopts DSP to realize the FPGA collocation method in described spaceborne SRAM type FPGA reliability, comprises:
Delayed configuration, adopts time delay collocation strategy to avoid booting moment power-supply fluctuation after the powering on of FPGA and causes configuration error.
Regularly reshuffle step, this step is for the FPGA in surveying work, and DSP is regularly to carrying out online reconfiguration to described FPGA;
The step of monitoring, this step comprises monitors power on configuration and online reconfiguration, described DSP monitors sub-step to the performance of the FPGA online reconfiguration that powers on configuration and controlled by DSP of FPGA, and the configuring condition of the FPGA in normal work is monitored to sub-step; When described DSP monitors described FPGA, fail normally to complete configuration or the FPGA in normal work while there is configuration error in official hour section, described DSP carries out online reconfiguration to described FPGA;
Described DSP carries out online reconfiguration process to described FPGA: the in the situation that of not power-off, described DSP startup is controlled the configuration pin of described FPGA is applied to a low level pulse that is greater than 300ns, complete the reset operation to configuration logic, FPGA is configured process automatically afterwards.
Wherein, the described cycle of regularly reshuffling can be injected and be modified by ground data;
The step that reset configuration logic is reshuffled is: the in the situation that of not power-off, described DSP startup is controlled the arrangement reset pin of described FPGA is applied to a low level pulse that is greater than 300ns, complete the reset operation to configuration logic, FPGA is configured process automatically afterwards.
In technique scheme, described concrete configuration process comprises: step, the step of elements with configuration data frame, the step of the step of CRC check and Start-Up of removing config memory.
Described time delay collocation strategy is: its output while utilizing house dog to power on
pin produces the low level of 200ms, and this signal is received to FPGA's
pin just can be realized after FPGA powers on and postpone to configure after 200ms;
Wherein, the FPGA described in which comprises: ground or spaceborne SRAM type FPGA.
In technique scheme, the power on performance of configuration and the FPGA online reconfiguration controlled by DSP of described FPGA is carried out to monitoring step, if described DSP does not detect its universal input mouth TINP1 mouth for ' 0 ' in the normally work that powers in latter 3 seconds, or its universal input mouth TINP1 mouth do not detected for ' 0 ' in after DSP startup FPGA online reconfiguration 3 seconds, represent FPGA configuration failure; If described DSP detected its universal input mouth TINP1 mouth for ' 0 ' in 3 seconds, represent and this FPGA configuration successful, DSP notice FPGA enters normal surveying work state.
A described low level pulse that is greater than 300ns adopts following steps to obtain:
DSP arranges it
the sequential of writing of EMIF (being external memory interface) the control register CE1CTL of (being that sheet selects 1) address space is its slowest sequential, " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle, add up to 81 DSP cycles, wherein cpu cycle is 9.6ns, and the time of DSP mono-recordable is 81x 9.6ns=777.6ns like this.Like this when DSP need to reshuffle FPGA, DSP couple
write operation is carried out in certain address of address space, and gating three or eight code translators are connecting FPGA's
the output of pin Na road, makes this output produce a low level pulse that width is 777.6ns (=DSP instruction cycle 9.6ns x mono-recordable periodicity 81), and this low level is applied to FPGA's
fPGA will start online reconfiguration process.
Preferably, described in power in configuration, online reconfiguration process and configured after control before FPGA enters normal surveying work to DSP, be subject to the switch to the every other equipment of system that FPGA controls to be "off" state, guaranteed the safety of system.
Described assurance security of system method is: the system switching of system agreement FPGA control, and level is controlled and is defined as high level pass, and low level is opened, and along controlling, is defined as negative edge pass, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground by a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch to the every other equipment of system of being controlled by FPGA during FPGA configuration is like this "off" state;
The initial value that FPGA arranges all registers is ' 1 ', before entering normal surveying work like this, is subject to the switch to the every other equipment of system that FPGA controls to be "off" state after FPGA has configured to DSP control FPGA.
For method set forth above, the configuration-system of a kind of spaceborne SRAM type FPGA for long-term operation on orbit, comprises: DSP, FPGA and some PROM, it is characterized in that, and described system also comprises:
Delayed collocation method, is connected to the configuration pin of FPGA with the reset output terminal mouth of house dog
postpone FPGA boot;
Configuration monitoring method, the configuration pin of FPGA " DONE " is linked DSP universal input port by phase inverter, after FPGA normal configuration completes, its configuration pin " DONE " can be drawn high automatically as ' 1 ', this configuration pin is connected to the universal input port of DSP through phase inverter, DSP judges by this universal input port of inquiry whether FPGA configuration is correct.
Method for reconfiguration, when DSP monitors FPGA configuration error or regularly reshuffles interruption arrival, the in the situation that of not power-off, DSP starts the online reconfiguration to FPGA.PROM belongs to fuse-type high reliability device, and DSP and FPGA program are all kept at PROM separately for a long time.All need to be from PROM boot separately to ram in slice separately before the normal work of DSP and FPGA.
Preferably, the described regularly cycle of reshuffling can be injected and be modified by ground data.A described low level pulse that is greater than 300ns adopts following steps to obtain:
DSP arranges it
the sequential of writing of EMIF (being external memory interface) the control register CE1CTL of (being that sheet selects 1) address space is its slowest sequential, " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle, add up to 81 DSP cycles, wherein cpu cycle is 9.6ns, and the time of DSP mono-recordable is 81x 9.6ns=777.6ns like this.Like this when DSP need to reshuffle FPGA, DSP couple
write operation is carried out in certain address of address space, and gating three or eight code translators are connecting FPGA's
the output of pin Na road, makes this output produce a low level pulse that width is 777.6ns (=DSP instruction cycle 9.6ns x mono-recordable periodicity 81), and this low level is applied to FPGA's
fPGA will start online reconfiguration process.
Preferably, described in power in configuration, online reconfiguration process and configured after control before FPGA enters normal surveying work to DSP, be subject to the switch to the every other equipment of system that FPGA controls to be "off" state, guaranteed the safety of system.
Described assurance security of system method is: the system switching that system agreement is controlled by FPGA, and level is controlled and is defined as high level pass, and low level is opened, and is defined as negative edge closes along control, and rising edge is opened; The HSWAP EN pin of FPGA is pulled down to ground by a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch to the every other equipment of system of being controlled by FPGA during FPGA configuration is like this "off" state;
The initial value that FPGA software arranges all registers is ' 1 ', before entering normal surveying work like this, is subject to the switch to the every other equipment of system that FPGA controls to be "off" state after FPGA has configured to DSP control FPGA.
The invention has the advantages that, provide the strategy of delayed configuration can avoid booting moment because power-supply fluctuation causes the generation of FPGA configuration error, reduced the requirement to design for power supply and distribution simultaneously; Utilize DSP to monitor the configuration performance of FPGA, avoided in the high radiation environment of space FPGA configuration to cause the unsuccessful whole system that causes of configuration can not normal boot-strap work owing to meeting with single event function interrupt, by DSP Real-Time Monitoring, when finding that FPGA configures DSP when unsuccessful and can automatically start and reshuffle, do not need ground artificial intervention, and than manual intervention, recover faster, also reduce the on-off times of relay; Regularly reshuffle, for working for a long time, adopt the SRAM type FPGA of triplication redundancy design in the high radiation environment of space, regularly reshuffle and prevent because the cumulative of single-particle inversion causes the function of FPGA to make a mistake; The cycle of regularly reshuffling can be injected and be modified by ground data, be operated in like this satellite borne equipment of space environment, by the data accumulation of a period of time, obtain moderate reshuffling the cycle of frequency, by ground data, inject the default cycle of regularly reshuffling of revising software setting, also can, according to the variation of irradiation space level, such as strengthening at solar activity peak year radiation level, now can inject relatively short regularly reshuffling the cycle simultaneously.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of raising FPGA reliability of the present invention;
Fig. 2 is the invention process strategy schematic diagram that combines with actual FPGA configuration flow;
Fig. 3 is the composition schematic diagram of the configuration-system that specifically powers on provided by the invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further described.
As shown in Figure 1, the FPGA of onboard system of the present invention adopts triplication redundancy design, for fear of the generation cumulatively that causes FPGA local error due to single-particle inversion, the invention provides and comprise: the configuration that powers on, configuration monitoring, online reconfiguration and the layout strategy such as regularly reshuffle, specific works flow process is:
The step that powers on, described FPGA adopts time delay collocation strategy to avoid booting moment power-supply fluctuation to cause configuration error;
Monitor the step of the rear configuring condition that powered on, described DSP monitors the configuring condition that described FPGA powers on after finishing, if monitor configuration successful, notifies described FPGA to enter normal measuring state; If described DSP monitors described FPGA configuration failure, enter the step that reset configuration logic is reshuffled;
Online reconfiguration process is: the in the situation that of not power-off, described DSP startup is controlled the arrangement reset pin of described FPGA is applied to a low level pulse that is greater than 300ns, completes the reset operation to configuration logic, and FPGA is configured process automatically afterwards.After DSP startup FPGA reshuffles, equally still to monitor the performance of FPGA configuration, if monitor configuration successful, notify described FPGA to enter normal measuring state; If described DSP monitors described FPGA configuration failure, enter the step that reset configuration logic starts FPGA online reconfiguration;
Under normal operating conditions, DSP periodically monitors FPGA whether configuration error has occurred, and if it is DSP reset FPGA configuration logic starts FPGA online reconfiguration;
Under normal operating conditions, when timer is regularly reshuffled while interrupt arriving in DSP inside, the DSP FPGA configuration logic that also resets starts FPGA online reconfiguration;
Wherein, described reconfiguration course comprises: remove config memory, elements with configuration data frame, CRC check and Start-Up process.
As shown in Figure 2, this figure is the invention process strategy schematic diagram that combines with actual FPGA configuration flow, is described below:
System powers on, when FPGA supply voltage meets following condition: core voltage VCCINT, be greater than the IO voltage VCCO that 1.2V, boosting voltage VCCAUX be greater than 2.5V, Bank4 and be greater than after 1.5V as shown in Figure 1, layoutprocedure enters into the config memory process of removing automatically, removes FPGA's in config memory process
for low level;
FPGA configuration pin
for bi-directional pin, this pin can also utilize outside to make it remain low level ' 0 ', FPGA is maintained and know in config memory process, house dog output signal of the present invention
link this pin, utilize house dog to power on after its
maintain low level 200ms, in this 200ms, FPGA configuration flow maintains the config memory process of removing, when
signal becomes after high level ' 1 ', and FPGA just starts follow-up configuration process.When configuration process detects
after high level ' 1 ', FPGA configuration process checks configuration mode pin, afterwards the configuration RAM from program storage elements with configuration data frame to FPGA, then carries out CRC check.If CRC check value is not mated,
become the failure of low level sign CRC check, layoutprocedure finishes.If CRC check is correct, its configuration pin " DONE " becomes high level ' 1 '; Carry out Start-Up, FPGA just enters user's control model afterwards again.The present invention links configuration pin " DONE " a universal input pin of DSP exactly through phase inverter, whether correctly DSP judges FPGA configuration by this universal input pin of inquiry.
If need to carry out online reconfiguration to FPGA, only need be to its arrangement reset pin
apply the level that a width is greater than 300ns, the configuration logic that just can reset,
after uprising level, automatically start the above-mentioned processes such as config memory, elements with configuration data frame, CRC check, Start-Up of knowing.
As shown in Figure 3, this figure is the composition schematic diagram of a concrete FPGA configuration and monitoring system.Specifically describe as follows:
1) delayed configuration design
The object of time delay configuration be avoid powering on during because power-supply fluctuation causes configuration error; Method is its output while utilizing U1Max706 to power on
produce the low level of 200ms, this signal is received to FPGA's
pin just can be realized after FPGA powers on and postpone to configure after 200ms.
2) FPGA exports the reliability safeguard of controlling during powering on and configuring
The system switching that system agreement FPGA controls, level is put down to control and is defined as high level pass, and low level is opened, and along controlling, is defined as negative edge pass, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground by a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, during FPGA configuration, be subject to like this switch to the every other equipment of system that FPGA controls to be "off" state;
The initial value that FPGA software arranges all registers is ' 1 ', before entering normal surveying work like this, is subject to the switch to the every other equipment of system that FPGA controls to be "off" state after FPGA has configured to DSP control FPGA.
3) DSP carries out Monitoring Design to the configuring condition of FPGA
The necessity that DSP monitors the configuration of FPGA is:
After system powers on, DSP need to be from PROM U9 boot to its sheet internal program RAM, FPGA also need to be from its PROM U8 boot to the configuration RAM of FPGA simultaneously, due to DSP boot adopt parallel mode, guiding speed fast, need the program of guiding little, so actual result is that DSP completes program designation for 2.8 seconds approximately in advance compared with FPGA.If DSP did not detect TINP1 mouth for ' 0 ' in 3 seconds during system power-up, represent the FPGA configuration failure that powers on.
FPGA load and normal work after, its " DONE " pin should remain on ' height ' level, if not then the configuration logic of explanation FPGA occurred to cause configuration error because of reasons such as SEU.Therefore after normal work, DSP still needs to monitor at any time FPGA configuration pin by its TINP1 mouth.
If DSP loads because its watchdog reset causes, and DSP program fleet causes one of possible reason of watchdog reset, be that FPGA has met with SEU mistake, cause FPGA and DSP communication to be broken down, if now DSP works after loading and starting working of their own, do not find the fault of FPGA and process, its result may be only ceaselessly Self-resetting of DSP.Cannot from fault, recover.
The configuration pin of hardware design FPGA " DONE " is linked DSP through phase inverter and is used as the timer TINP1 mouth of universal input mouth at this, dsp software is designed to DSP just ceaselessly inquires about its TINP1 mouth with 10ms interval after starting working, when inquiring TINP1 mouth for ' 0 ', represent that FPGA has configured (configuration pin " DONE " that is FPGA is drawn high ' 1 '), now DSP writes height control word to FPGA, measure AGC value, DDS bandwidth control etc., opens interrupters, and notify FPGA to open radar sequential control, DSP and FPGA all enter normal surveying work pattern, whole radar altitude meter systems starts to measure.4) DSP reshuffles FPGA
Hardware design
FPGA lower electric in the situation that to its configuration pin
apply a low level that is not less than 300ns, FPGA will reconfigure; But must guarantee that design reshuffles circuit and should not affect the FPGA self-configuring that powers on.
Circuit hardware design is as Fig. 3.The EA17 of DSP, EA18 link two input end A, the B of code translator LVC138, and DSP output chip enable signal CE1 drives LVTH16244 to be divided into two-way by line and exports, a road
select input end to the Low level effective ground sheet of code translator LVC138.The hardware design of DSP makes BOOTMODE[4:0]=" 01101 " be that the Memory Mapped of DSP is MAP1.
Dsp software design
The Software for Design of DSP arranges its slowest default sequential for read/write sequential of the EMIF control register CE1CTL of CE1 address space, be that Set/Strobe/Hold is respectively 15/63/3 DSP clock period, because clock period of hardware design DSP is 9.6ns, when Memory Mapped is MAP1.The method for reconfiguration that DSP starts FPGA is that address 0x01460000 is carried out to single write operation, corresponding like this CE1=' 0 ', EA17=' 1 ' EA18=' 1 ', through three or eight code translator LVC138, its output Y4 pin just produces a width for the low level of (15+63+3) Cycle * 9.6ns=777.6ns, this low level width is greater than 300ns, through R4, arrives FPGA's
pin.
What this programme designed is regularly FPGA to be reshuffled, the superiority of regularly reshuffling is that satellite is after observation in orbit after a while, obtain the cycle of more regularly reshuffling and finally by DSP, receive and understand and carry out by noting data block on ground, just not needing afterwards manual intervention; If find on the other hand SEU mistake during tasks carrying, can also go up very short regularly the reshuffling the cycle of note (approximately 3 minutes) and realize reset immediately, after having resetted, also need to inject regularly reshuffling the cycle of compared with normal.
Reshuffle the impact that circuit powers on and configures FPGA:
This reshuffles the configuration that powers on that circuit design can not affect FPGA.The address 0x01460000 of DSP is exclusively used in and reshuffles FPGA, other whenever only otherwise read/write operation is carried out in this address, the Y4 output pin of LVC138 is exactly high-impedance state, can not exert an influence to FPGA.
Extendability is analyzed
" DSP+FPGA " architecture design has become comparatively general high-Speed Digital Signal Processing Platform at present, has been widely used in the fields such as software radio that radar signal is followed the tracks of processing, realtime graphic processing, communication aspect, also has widely and use on satellite borne equipment.This FPGA configuration observation circuit all can be used in the design of any " DSP (or CPU)+SRAM type FPGA ", is a kind of simple and effective High Reliability Design.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is modified or is equal to replacement, do not depart from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (13)
1. the collocation method for the spaceborne SRAM type FPGA of long-term operation on orbit, for improving the reliability at the spaceborne SRAM type FPGA of the long-term work of the high radiation environment of space, wherein this FPGA adopts triplication redundancy design to improve its reliability, described method utilizes DSP to realize the FPGA configuration in described spaceborne SRAM type FPGA reliability, specifically comprises:
Regularly reshuffle step, this step is for the FPGA in surveying work, and DSP regularly carries out online reconfiguration to described FPGA;
The step of monitoring, this step comprises monitors power on configuration and online reconfiguration, described DSP monitors sub-step to the performance of the FPGA online reconfiguration that powers on configuration and controlled by DSP of FPGA, and the configuring condition of the FPGA in normal work is monitored to sub-step; When described DSP monitors described FPGA, fail normally to complete configuration or the FPGA in normal work while there is configuration error in official hour section, described DSP carries out online reconfiguration to described FPGA;
Wherein, the described cycle of regularly reshuffling is injected and is modified by ground data;
Described DSP carries out online reconfiguration process to described FPGA: the in the situation that of not power-off, described DSP startup is controlled the arrangement reset pin of described FPGA is applied to a low level pulse that is greater than 300ns, complete the reset operation to configuration logic, FPGA is configured process automatically afterwards;
After the powering on of described FPGA, adopt time delay collocation strategy to avoid booting moment power-supply fluctuation and cause configuration error.
2. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, is characterized in that, described time delay collocation strategy is:
Its output pin while utilizing house dog to power on
produce the low level of 200ms, should
pin is received FPGA's
pin just can be realized after FPGA powers on and postpone to configure after 200ms;
Wherein, described FPGA comprises: ground or spaceborne SRAM type FPGA.
3. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, it is characterized in that, described reconfiguration course comprises: the step of removing step, the step of elements with configuration data frame, the step of CRC check and the startup Start-Up of config memory.
4. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, it is characterized in that, the performance sub-step of the FPGA online reconfiguration that powers on configuration and controlled by DSP of described DSP monitoring FPGA: if described DSP does not detect its universal input mouth TINP1 mouth for ' 0 ' in the normally work that powers in latter 3 seconds, or its universal input mouth TINP1 mouth do not detected for ' 0 ' in after DSP startup FPGA online reconfiguration 3 seconds, represent FPGA configuration failure; If described DSP detected its universal input mouth TINP1 mouth for ' 0 ' in 3 seconds, represent this FPGA configuration successful, DSP notice FPGA enters normal surveying work state.
5. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, it is characterized in that, described DSP monitors sub-step to the configuring condition of the FPGA in normal surveying work: described DSP is by FPGA configuration pin described in its TINP1 mouth periodic monitoring, when FPGA enters normal operating conditions, its " DONE " pin should remain on ' height ' level, should through phase inverter, be connected to the TINP1 of DSP by " DONE " pin, TINP1 should remain on ' low ' level, if not then fault has occurred the configuration logic of known this FPGA.
6. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, is characterized in that, a described low level pulse that is greater than 300ns adopts following steps to obtain:
Described DSP arranges its sheet, and to select the sequential of writing of the external memory interface control register CE1CTL of 1 pin address space be its slowest sequential, " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle, add up to 81 DSP cycles, wherein cpu cycle is 9.6ns, and the time of described DSP mono-recordable is 81x9.6ns=777.6ns; When DSP need to reshuffle FPGA, described DSP selects certain address of 1 address space to carry out write operation to sheet, gating three or eight code translators are connecting the arrangement reset pin Na road output of FPGA, make this output produce a low level pulse that width is 777.6ns, this low level is applied to the arrangement reset pin of FPGA, and described FPGA starts online reconfiguration process.
7. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 1, it is characterized in that, before entering normal surveying work to DSP control FPGA after the described layoutprocedure that powers on, online reconfiguration process and configuration complete, be subject to the switch to the every other equipment of system that FPGA controls to be "off" state, for guaranteeing the safety of system.
8. the collocation method of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 7, is characterized in that, guarantees that security of system method is:
The system switching of system agreement FPGA control, level is controlled and is defined as high level pass, and low level is opened, and along controlling, is defined as negative edge pass, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground by a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch to the every other equipment of system of being controlled by FPGA during FPGA configuration is like this "off" state;
The initial value that described FPGA arranges all registers is ' 1 ', before entering normal surveying work, is subject to the switch to the every other equipment of system that described FPGA controls to be "off" state after FPGA has configured to DSP control FPGA.
9. for a configuration-system of the spaceborne SRAM type FPGA of long-term operation on orbit, comprise: DSP, FPGA and some PROM, it is characterized in that, described system also comprises:
Delayed collocation method, is connected to the configuration pin of FPGA with the reset output terminal mouth of house dog
postpone FPGA boot;
Configuration monitoring method, the configuration pin of FPGA " DONE " is linked DSP universal input port by phase inverter, after FPGA normal configuration completes, its configuration pin " DONE " can be drawn high automatically as ' 1 ', this configuration pin is connected to the universal input port of DSP through phase inverter, DSP judges by this universal input port of inquiry whether FPGA configuration is correct;
Method for reconfiguration, when described DSP monitors described FPGA configuration error or regularly reshuffles interruption arrival, the in the situation that of not power-off, described DSP starts the online reconfiguration to described FPGA;
The described cycle of regularly reshuffling is injected and is modified by ground data.
10. the configuration-system of the spaceborne SRAM type FPGA for long-term operation on orbit according to claim 9, is characterized in that, monitoring means physical circuit is:
The configuration pin of described FPGA " DONE " is linked DSP universal input port by phase inverter, after described FPGA normal configuration completes, configuration pin " DONE " can be drawn high automatically as ' 1 ', this configuration pin is connected to the universal input port of described DSP through described phase inverter, described DSP judges by this universal input port of inquiry whether FPGA configuration is correct.
The configuration-system of the 11. spaceborne SRAM type FPGA for long-term operation on orbit according to claim 9, is characterized in that, a low level pulse that is greater than 300ns adopts following steps to obtain:
Described DSP arranges its sheet, and to select the sequential of writing of the external memory interface control register CE1CTL of 1 address space be its slowest sequential, " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle, add up to 81 DSP cycles, wherein cpu cycle is 9.6ns, and the time of described DSP mono-recordable is 81x9.6ns=777.6ns; When described DSP need to reshuffle described FPGA, described DSP selects certain address of 1 address space to carry out write operation to sheet, gating three or eight code translators are connecting the arrangement reset pin Na road output of described FPGA, make this output produce a low level pulse that width is 777.6ns, this low level is applied to the arrangement reset pin of FPGA, and described FPGA starts online reconfiguration process.
The configuration-system of the 12. spaceborne SRAM type FPGA for long-term operation on orbit according to claim 9, it is characterized in that, power in configuration, online reconfiguration process, and before entering normal surveying work to DSP control FPGA after having configured, be subject to the switch to the every other equipment of system that described FPGA controls to be "off" state, for guaranteeing the safety of system.
The configuration-system of the 13. spaceborne SRAM type FPGA for long-term operation on orbit according to claim 12, is characterized in that, described assurance security of system method is:
The system switching of system agreement FPGA control, level is controlled and is defined as high level pass, and low level is opened, and along controlling, is defined as negative edge pass, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground by a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch to the every other equipment of system of being controlled by described FPGA during FPGA configuration is like this "off" state;
The initial value that described FPGA arranges all registers is ' 1 ', after described FPGA has configured, control before described FPGA enters normal surveying work to described DSP, be subject to the switch to the every other equipment of system that described FPGA controls to be "off" state.
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