CN107395327A - A kind of high reliability LDPC encoder suitable for satellite communication - Google Patents
A kind of high reliability LDPC encoder suitable for satellite communication Download PDFInfo
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- CN107395327A CN107395327A CN201710591406.5A CN201710591406A CN107395327A CN 107395327 A CN107395327 A CN 107395327A CN 201710591406 A CN201710591406 A CN 201710591406A CN 107395327 A CN107395327 A CN 107395327A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
- H04B7/18586—Arrangements for data transporting, e.g. for an end to end data transport or check
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Abstract
The invention discloses a kind of high reliability LDPC encoder suitable for satellite communication, the encoder includes data format judge module, reset processing module, coding module, framing scrambling module and output data handover module.The encoder shortens code using the 7/8 of CCSDS (consultative committee for space data system) standard recommendation, has universal LDPC encoding functions；Designed using monolithic anti-fuse FPGA, it is not necessary to additionally configure chip, with conventional based on compared with the design of SRAM type fpga chip, simple in construction, debugging is easy；Data format judge module carries out format discriminance, and reset processing block combiner application to input data, encoder is had self-recovering function after reception wrong data；United application with G matrix data fixed storage in coding module is handled by timing reset, improves encoder anti-single particle upset performance.
Description
Technical field
The invention belongs to wireless communication technology field, more particularly to a kind of high reliability LDPC suitable for satellite communication to compile
Code device.
Background technology
Channel coding technology is widely used in various communication systems as the effective means for ensureing information transmitting,
LDPC code is because with the error-correcting performance close to Shannon limits, turning into one of satellite communication error correction pattern of CCSDS recommendations.
Space environment is filled with the proton from universe, electronics, α particles and heavy ion etc., is radiated caused by Space Particle
Effect, especially single-particle inversion phenomenon serious threat the safety of electronic equipment.At present, limited by conditions such as device resources,
Satellite communication LDPC encoder mostly using SRAM type FPGA realize, logic function is realized by SRAM configuration modes, when by
Irradiation space, configuring area logical relation and Operational Zone flip-flop states are easily overturned by single-particle, cause program run-time error.
ACTEL chips use antifuse technology, by the technical cure that fuses are fixed logic relation condition during burning program, to single-particle
It is immune, but Operational Zone trigger can still be overturned by single-particle.If trigger is to do data storage application, after being overturned by single-particle
The individual data of present frame can be only influenceed, and data will not continue；If trigger is to do controller application, after being overturned by single-particle
Program operation rhythm can be upset, if not being acted upon, the coding rhythm of mistake will be accumulated in subsequent arithmetic, cause to continue
Property code error.
LDPC code is block code, and input data is continuous but is all independent computing per frame data.In program operation process,
If the frame format mistake of front end input data, it will local program operation rhythm is disturbed, it is untreated to cause to continue
Property code error.
The content of the invention
For above-mentioned technological deficiency, the present invention proposes a kind of high reliability LDPC encoder, and it is applied to satellite
The complex space environment of communication.
To achieve the above object of the invention, the present invention adopts the following technical scheme that：
A kind of high reliability LDPC encoder suitable for satellite communication, including data format judge module, reset processing
Module, coding module, framing scrambling module and output data handover module；The data format judge module is to input data lattice
Formula correctness is detected, and the correct data of form are sent into the coding module and carry out normal encoding, and the data of format error are entered
The transparent output of row；The reset processing module program is carried out respectively according to state electrification reset, input data error reset and
Correctly enter data fixed position reset processing；The coding module carries out LDPC codings to correct input data, and according to volume
Code stream journey reads G matrix data and participates in computing, generates verification data；The framing scrambling module presses frame lattice to the data after coding
Formula requires framing, and carries out scrambling processing to the data in addition to frame head；The output data handover module is according to input data lattice
Data after formula correctness switching output data transparent transmission or coding scrambling.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, the encoder uses
LDPC coding rules as defined in CCSDS standards, it is the universal coding mode of current satellite communication, makes this encoder in satellite communication
In there is versatility.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, the encoder uses
Anti-fuse FPGA single chip design, it is not necessary to exterior arrangement chip.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, the coding module
In G matrix data using curing mode store, with reference to anti-fuse FPGA characteristic, single-particle inversion phenomenon is not present after solidification,
The conventional G matrix data single-particle turning problem based on SRAM type FPGA programs can be efficiently solved, it is not necessary to extra to reinforce
Measure.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, when input data lattice
During formula mistake, the reset processing module is answered the coding module, framing scrambling module and output data handover module
Position processing；When input data form is correct, the reset processing module be fixed on frame head end position to the coding module,
Framing scrambling module and output data handover module carry out reset processing.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, the coding module
Including data buffer, shift register, verification data register, G matrix unit and control unit, described control unit control
The data for reading the ad-hoc location of the G matrix unit are temporarily stored in the shift register, by the number of the shift register
According to valid data to be encoded do mutually and computing, and with the number being deposited with the verification data register of previous operation result
According to XOR is carried out, operation result is temporarily stored in the verification data register, treats that current frame data completes coding, caused
Corresponding verification data is sent into buffer, while the verification data register is reset.
As a kind of improvement of high reliability LDPC encoder suitable for satellite communication of the present invention, the framing scrambling
Module includes control unit and output buffer unit, and described control unit controls frame head data, coded data and verification data
Output switching, the data buffer storage after framing scramble, after scrambling in the output buffer unit to the data in addition to frame head
Data divide I, Q two-way to export to modulator.
Compared with prior art, the advantageous effects of the technical solution adopted in the present invention are：
The LDPC encoder that the present invention designs is on the basis of LDPC encoding functions are realized, for aerospace environment spy
Point, encoder anti-single particle upset ability is enhanced, influence of the Introduced cases mistake to local program is effectively prevent, is not required to be remotely controlled
Reset can recover normal automatically, improve the dependable with function of encoder.
Brief description of the drawings
Fig. 1 is the external interface and internal structure block diagram of the present invention；
Fig. 2 is the schematic diagram of the data format judge module in Fig. 1；
Fig. 3 is the schematic diagram of the reset processing module in Fig. 1；
Fig. 4 is the LDPC coding module block diagrams in Fig. 1；
Fig. 5 is the framing scrambling module structure chart in Fig. 1.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, each reality below in conjunction with accompanying drawing to the present invention
The mode of applying is explained in detail.
It is encoder interfaces and internal structure block diagram as shown in Figure 1.
Encoder input interface includes clock signal, input data signal and power-on reset signal, and output interface includes I, Q
Data-signal, coded data are exported to modulator.
Decoder internal structure includes data format judge module, reset processing module, LDPC coding modules, framing scrambling
Module and output data handover module.
Data format judge module detects to input data (position of reserved verification data) form correctness, form
Correct data are sent into coding module and carry out normal encoding, the data transparency output of format error.Input data detection function can
Effectively to eliminate influence of the Introduced cases mistake to local program, can also in the temporary mistake of input data and after recovering normal,
Encoder is not required to remote control and resets and recover automatically normal；
It is correct that reset processing module carries out electrification reset, input error data reset and input according to state respectively to program
Data fixed position reset processing, can effectively eliminate because of single-particle inversion and caused by local program malfunction；
Coding module carries out LDPC codings to the data correctly entered by CCSDS required standards, generates verification data.Wherein
G matrix data are stored using curing mode, and read data according to coding flow.G matrix data are the core numbers of LDPC codings
According to, once the mistake that entirely encodes will be caused by single-particle inversion phenomenon occur.Conventional realizes that LDPC is compiled based on SRAM type FPGA
Code, it is often necessary to the larger single-particle inversion for undergoing and solving the problems, such as G matrix data is spent, as triplication redundancy, plug-in PROM are stored
Or the mode such as plug-in retaking of a year or grade refresh circuit.The present invention is stored in anti-fuse FPGA platform using curing mode, can be with easy and effective
Ground solves the problems, such as single-particle inversion；
Framing scrambling module carries out framing to coded data by frame format requirement, and in addition to frame head (1ACFFC1D)
Data carry out scrambling processing, and scrambling mode uses PN8 sequences as defined in CCSDS standards, in order to prevents in output data
Long " 0 " and the appearance of long " 1 " code；
Output data handover module exports data transparent transmission or coding according to the correct Sexual behavior mode of input data form and added
Rear data are disturbed, the transmission of transparent data can prevent the interruption of communication link, and ground staff can also be assisted to analyze error reason.
It is data format judge module as shown in Figure 2, is responsible for input data format detection, in order to prevent from inputting
Data formatting error causes coding to malfunction.
Encoder input data is wire transmission, and corrupt data probability is relatively low, but to prevent headend equipment from being turned over because of single-particle
Turn etc. reason occur temporary data format error influence encoder work rhythm, it is necessary to do correctness to input data form
Detection.Detection mode is to judge whether the interval of every group of frame head data is 8192bits, and the original position of counter is frame head number
According to original position.Input data form is correct, and then normal encoding, format error then export data transparency.
It is reset processing module as shown in Figure 3, is responsible for that program electrification reset, input data format error are resetted and inputted
Correct data fixed position reset processing.
It is stochastic regime after electricity on each trigger of anti-fuse FPGA, it is necessary to which carrying out electrification reset makes each trigger have initially
State；When input data format error, coding module, framing scrambling module and output data handover module are carried out at reset
Reason；When input data form is correct, it is fixed on frame head end position and coding module, framing scrambling module and output data is cut
Change the mold block and carry out reset processing, above-mentioned module error can be caused to be limited in single-particle inversion by fixed position reset processing
In present frame, error diffusion is effectively prevented.After above-mentioned reset processing, encoder can need not be remotely controlled reset signal.
It is LDPC coding module block diagrams as shown in Figure 4, is responsible for that data to be encoded and G matrix data operation will be inputted, draws
Corresponding check information data, export and give framing scrambling module.
What G matrix unit stored is each 511bits data that 28 submatrixs correspond to first trip in G matrix, by control unit
Control signal is produced, 2 submatrix first trip data is read every time and keeps in a shift register, every 14 times are a circulation.Often
Secondary computing is done mutually and computing by the data and valid data to be encoded of shift register, and is deposited with previous operation result
Data in verification data register carry out XOR, and operation result is temporarily stored in verification data register.Treat 14 circulations
After end, current frame data completes coding, and caused corresponding verification data is sent into buffer, while verification data register is clear
Zero, carry out coding for lower frame data and be ready.
If Fig. 5 is framing scrambling module, be responsible for frame head, coded data and verification data by frame format arrangement, and to except
Data outside frame head carry out scrambling processing, and then branch I, Q is exported to qpsk modulator.
The data of whole frame are collectively constituted by 32 frame head datas, 7136 coded datas and corresponding 1024 bit check data,
The output switching of frame head data, coded data and verification data is realized that the data buffer storage after framing is slow in output by control unit
In memory cell.In order to avoid length " 0 ", long " 1 " long code occur, pseudorandom permutation processing is carried out, the scrambler suggested using CCSDS is given birth to
Into multinomial F (x)=X8+X7+X5+X3+1.The pseudo-code sequence original state is complete " 1 ", every 255bits circulation primaries.It is right
8160bits in addition to frame head is scrambled, and is 32 scramble sequence length.Data divide I, Q two-way to export to modulation after scrambling
Device.
In summary, the present invention uses anti-fuse FPGA single chip design, realizes the LDPC codings based on CCSDS standards
Device.To meet satellite communication high reliability demand, outside basic coding function, judged by input data form, reset processing
It is combined with means such as G matrix data fixed storages, enhances anti-single particle upset performance, it is not necessary to which remote control resets and has mistake
Self-recovering function by mistake, improve the reliability of encoder.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
It is defined.
Claims (7)
- A kind of 1. high reliability LDPC encoder suitable for satellite communication, it is characterised in that：Including data format judge module, Reset processing module, coding module, framing scrambling module and output data handover module；The data format judge module is to defeated Enter data format correctness to be detected, the correct data of form are sent into the coding module and carry out normal encoding, format error Data carry out transparent output；It is wrong that the reset processing module carries out electrification reset, input data according to state respectively to program Reset by mistake and correctly enter data fixed position reset processing；The coding module carries out LDPC codings to correct input data, G matrix data are read according to coding flow and participate in computing, generate verification data；The framing scrambling module is to the data after coding Scrambling processing is carried out by frame format requirement framing, and to the data in addition to frame head；The output data handover module is according to input Data after data format correctness switching output data transparent transmission or coding scrambling.
- A kind of 2. high reliability LDPC encoder suitable for satellite communication as claimed in claim 1, it is characterised in that：Using LDPC coding rules as defined in CCSDS standards.
- A kind of 3. high reliability LDPC encoder suitable for satellite communication as claimed in claim 2, it is characterised in that：Using Anti-fuse FPGA single chip design.
- A kind of 4. high reliability LDPC encoder suitable for satellite communication as claimed in claim 3, it is characterised in that：It is described G matrix data in coding module are stored using curing mode.
- A kind of 5. high reliability LDPC encoder suitable for satellite communication as claimed in claim 1, it is characterised in that：When defeated When entering data formatting error, the reset processing module switches mould to the coding module, framing scrambling module and output data Block carries out reset processing；When input data form is correct, the reset processing module is fixed on frame head end position to described Coding module, framing scrambling module and output data handover module carry out reset processing.
- A kind of 6. high reliability LDPC encoder suitable for satellite communication as claimed in claim 1, it is characterised in that：It is described Coding module includes data buffer, shift register, verification data register, G matrix unit and control unit, the control The data for the ad-hoc location that the G matrix unit is read in unit control are temporarily stored in the shift register, and the displacement is posted The data of storage do phase and computing with valid data to be encoded, and are deposited with the verification data that is deposited with of previous operation result Data in device carry out XOR, and operation result is temporarily stored in the verification data register, treat that current frame data is completed to compile Code, caused corresponding verification data is sent into buffer, while the verification data register is reset.
- A kind of 7. high reliability LDPC encoder suitable for satellite communication as claimed in claim 1, it is characterised in that：It is described Framing scrambling module includes control unit and output buffer unit, described control unit control frame head data, coded data and school Test the output switching of data, the data buffer storage after framing adds in the output buffer unit to the data in addition to frame head Disturb, the data after scrambling divide I, Q two-way to export to modulator.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111313910A (en) * | 2019-11-19 | 2020-06-19 | 天津大学 | Low Density Parity Check Code Encoder Apparatus for Space Communication Applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111313910A (en) * | 2019-11-19 | 2020-06-19 | 天津大学 | Low Density Parity Check Code Encoder Apparatus for Space Communication Applications |
| CN111313910B (en) * | 2019-11-19 | 2021-12-07 | 天津大学 | Low density parity check code encoder device for space communication application |
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Application publication date: 20171124 |