CN102779079A - Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time - Google Patents
Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time Download PDFInfo
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Abstract
The invention relates to a configuration method and system used for a satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for a long time. The method comprises the following steps: electrification: a delay configuration strategy is adopted for the FPGA to avoid configuration errors caused by power supply fluctuation generated at the moment of the boot; configuration process monitoring: the configuration condition of the FPGA is monitored by a DSP (Digital Signal Processor), and when the configuration of the FPGA is monitored to be normally completed, the FPGA is informed of entering a normal measurement state by the DSP, and an on-line reconfiguration step is started if the configuration of the FPGA is monitored to be not completed in time; reconfiguration: a low-level pulse larger than 300ns is controlled to be applied to a configuration reset pin of the FPGA by the DSP under the condition of uninterruptible power supply, and then the configuration process is automatically completed by the FPGA; normal working process monitoring: whether the configuration of the FPGA is correct or not is monitored regularly by the DSP in a normal working process, and FPGA on-line reconfiguration is started by the DSP if the configuration of the FPGA is wrong; and regular reconfiguration: a triple modular redundancy design is adopted for the FPGA, and is matched with the regular reconfiguration to improve the reliability of the FPGA.
Description
Technical field
The present invention relates to SRAM type FPGA and be used for satellite borne equipment, the configuration of FPGA and monitoring design in the anti-single particle Design of Reinforcement when being operated in the high radiation environment of space are specifically related to a kind of collocation method and system that is used for for a long time at the spaceborne SRAM type FPGA of rail work.
Background technology
The spaceborne radar altitude gauge is a kind of active microwave remote sensor, and it can realize the effective measurement to sea level height, sea significant wave height, sea backscattering coefficient and sea wind speed.The further inverting of these data can be applicable to the research of aspects such as marine geophysics, ocean dynamics, marine climatology and the detection of utmost point ice.
The HY-2 radar altimeter is a dual-frequency radar; Two wave bands of Ku and C are arranged; Numerical control unit adopts this SRAM type of the 2V3000 FPGA of the Virtex II series of Xilinx company to realize the switching sequence control, receiver gain control, echoed signal collection of transmitter unit, microwave front end, power amplifier etc. to whole altitude gauge system and carries out tracking processing, important task such as platform and ground communication via satellite by DSP; And during rail, belong to for a long time and run without interruption, so the high reliability design relation of FPGA is to the safety of total system.But this SRAM type FPGA is the single-particle Sensitive Apparatus; The data and the domestic anti-irradiation test result that provide according to the official website of the said firm to this device; This device is operated on this track of this about 960Km of HY-2 satellite; Meet with about 4-6 time of single event every day, therefore anti-/ (alleviation) single particle effect is an importance that needs concern in the FPGA reliability design.
SRAM type FPGA is not the i.e. operation that powers on, but needs the configuration RAM of elder generation from the PROM loading procedure to FPGA.Configuration just gets into duty after accomplishing, and FPGA electrify restoration circuit (POR:power on reset) is the responsive part of single-particle function interruption (SEFI), and the layoutprocedure that powers on possibly lose efficacy; Though the probability that SEFI takes place is extremely low,, so works in the design of satellite borne equipment of space environment and also need the emphasis consideration in case the influence that causes is very serious.Whether the FPGA that is used for uphole equipment generally need not monitor the configuration successful of FPGA.Because as long as circuit and system design are reasonable, there is not the unsuccessful problem of configuration, owing to need not consider single particle effect, therefore needn't do triplication redundancy and reshuffle design simultaneously.
Single-particle inversion (SEU) is meant that high energy particle is beaten and on key node, causes the storage unit bit flipping; For SRAM type FPGA, the position that single-particle inversion takes place comprises the bit flipping of the config memory of FPGA, register itself, lut memory, BlockRAM storer etc.Single-particle transient pulse (SET) is owing to high energy particle produces the input that a transient current pulse has influence on the next stage logical circuit on routing path, causes this logical circuit output disorderly.SET causes the moment mistake of FPGA internal logic circuit, and its influence also is equivalent to SEU one time.SEU and SET are two types of higher single particle effects of occurrence frequency.
Prior art adopts the mode of " triplication redundancy design+is regularly reshuffled " to alleviate SEU effectively.The triplication redundancy design philosophy is that same function little module is copied into three parts, again by voting machine output, as long as wherein two parts normal, whole logic function is exactly correct; And what regularly reshuffle solution is the problem of error accumulation; Work in the FPGA of space environment at present, more or less all include the triplication redundancy design; For the FPGA that during rail, belongs to the work of short-term discontinuity, be anti-single particle effect, should do the triplication redundancy design, but need not be designed to regularly reshuffle; This is because for the FPGA of the discontinuity start work of short-term, because an on time is shorter, three parts of same logical block generation single-particle inversions unlikely are accumulated to 2 parts and cause output error in the work period.And for the FPGA of long-term work during rail, three parts of same logical blocks make a mistake and may be accumulated to 2 parts, finally cause this functional unit mistake so that total system to make a mistake.Therefore, regularly reshuffle the accumulation problem that can solve mistake.But existing reconfiguration technology generally realizes through sending out instruction program control, and function is not reshuffled in some design, if find that single particle effect can only close equipment, start shooting and eliminate.Can be reduced in the automatization level that the rail long-term work contains the equipment of this SRAM type FPGA greatly like this, repeated switching increases the frequency of utilization to relay simultaneously.Triplication redundancy design resource expense is big, but concerning the satellite borne equipment that works in space environment, reliability will consider that at first it is necessary adopting and exchanging reliability for more resources.
Summary of the invention
The objective of the invention is to; For the mistake of alleviation at the single particle effect of the FPGA generation of the SRAM type of the employing triplication redundancy design of the high radiation environment long-term work of space adds up; The method that the present invention provides a kind of FPGA regularly to reshuffle and its configuring condition is monitored is when monitor that configuration fails to accomplish or normal work period in time starts online reconfiguration when configuration error occurring on schedule; The present invention simultaneously also adopts a kind of means that go up the electric delay configuration to overcome the problem that configuration error that start moment power-supply fluctuation causes takes place.The SRAM type FPGA reliability that has effectively improved in the high radiation environment long-term work of space, i.e. the present invention provides a kind of collocation method and system that is used for for a long time at the spaceborne SRAM type FPGA of rail work.
For realizing the foregoing invention purpose, the present invention adopts DSP to realize the FPGA collocation method in the said spaceborne SRAM type FPGA reliability, comprises:
Powering on time-delay configuration, the back that powers on of FPGA adopt the moment power-supply fluctuation of avoiding starting shooting of time-delay collocation strategy to cause configuration error.
Regularly reshuffle step, this step is to the FPGA in the surveying work, and DSP is regularly to carrying out online reconfiguration to said FPGA;
The step of monitoring; This step comprises monitors power on configuration and online reconfiguration; Said DSP disposes the performance that reaches the FPGA online reconfiguration of being controlled by DSP to powering on of FPGA and monitors substep, and the configuring condition that is in the FPGA in the operate as normal is monitored substep; In the official hour section, fail normal accomplish configuration or be in FPGA in the operate as normal when configuration error takes place when said DSP monitors said FPGA, said DSP carries out online reconfiguration to said FPGA;
Said DSP carries out the online reconfiguration process to said FPGA: said DSP start-up control applies a low level pulse greater than 300ns to the configuration pin of said FPGA under the situation of not cutting off the power supply; Completion is to the reset operation of configuration logic, and FPGA is configured process automatically afterwards.
Wherein, the said cycle of regularly reshuffling can be injected through ground data and made amendment;
The step that the configuration logic that resets is reshuffled is: said DSP start-up control applies a low level pulse greater than 300ns to the arrangement reset pin of said FPGA under the situation of not cutting off the power supply; Completion is to the reset operation of configuration logic, and FPGA is configured process automatically afterwards.
In the technique scheme, described concrete configuration process comprises: step, the step of elements with configuration data frame, the step of CRC check and the step of Start-Up of removing config memory.
Described time-delay collocation strategy is: its output when utilizing house dog to power on
pin produces the low level of 200ms, this signal is received
pin of FPGA and just can be realized postponing to dispose behind the 200ms after FPGA powers on;
Wherein, the described FPGA of this mode comprises: ground or spaceborne SRAM type FPGA.
In the technique scheme; To power on configuration and carry out monitoring step of said FPGA by the performance of the FPGA online reconfiguration of DSP control; If detecting its general input port TINP1 mouth in 3 seconds after the operate as normal that powers on, said DSP is not ' 0 '; Or start by DSP and not detect its general input port TINP1 mouth in 3 seconds after the FPGA online reconfiguration and be ' 0 ', then represent the FPGA configuration failure; If detecting its general input port TINP1 mouth in 3 seconds, said DSP is ' 0 ', then expression and this FPGA configuration successful, and DSP notice FPGA gets into normal surveying work state.
A said low level pulse greater than 300ns adopts following steps to obtain:
The sequential of writing that DSP is provided with EMIF (being external memory interface) the control register CE1CTL of its
(being that sheet selects 1) address space is its slowest sequential; Promptly " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle; Add up to 81 DSP cycles; Wherein cpu cycle is 9.6ns, and the time of DSP mono-recordable is 81x 9.6ns=777.6ns like this.Like this when DSP need reshuffle FPGA; DSP carries out write operation to certain address of
address space; Gating three or eight code translators are connecting that road output of FPGA's
pin; Make this output produce the low level pulse that width is 777.6ns (=DSP instruction cycle 9.6ns x mono-recordable periodicity 81),
FPGA that this low level affacts FPGA will begin the online reconfiguration process.
Preferably, in the said configuration that powers on, the online reconfiguration process and configuration accomplish before the back gets into normal surveying work to DSP control FPGA, receive the switch to the every other equipment of system of FPGA control to be "off" state, guaranteed the safety of system.
Said assurance security of system method is: the system switching of system design agreement FPGA control, and the high level that is defined as of level control closes, and low level is opened, and the negative edge that is defined as of edge control closes, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground through a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch of being controlled by FPGA during the FPGA configuration like this of giving the every other equipment of system is "off" state;
The initial value that FPGA is provided with all registers is ' 1 ', accomplishes before the back gets into normal surveying work to DSP control FPGA in FPGA configuration like this, receives the switch to the every other equipment of system of FPGA control to be "off" state.
To method set forth above, a kind of configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work, comprise: DSP, FPGA and some PROM is characterized in that said system also comprises:
The time-delay collocation method that powers on, the configuration pin
that is connected to FPGA with the reset output terminal mouth of house dog is postponed the FPGA boot;
The configuration monitoring method; The configuration pin of FPGA " DONE " is linked the general input port of DSP through phase inverter; After the FPGA normal configuration is accomplished; Its configuration pin " DONE " can drawn high automatically be ' 1 ', and this configuration pin is connected to the general input port of DSP through phase inverter, and DSP judges through inquiry this general input port whether FPGA disposes correct.
Method for reconfiguration, when DSP monitored the FPGA configuration error or regularly reshuffles the interruption arrival, under the situation of not cutting off the power supply, DSP started the online reconfiguration to FPGA.PROM belongs to fuse-type high reliability device, and DSP and the equal long preservation of FPGA program are at separately PROM.All need be before DSP and the FPGA operate as normal from separately PROM boot to separately ram in slice.
Preferably, the said cycle of reshuffling regularly can be injected through ground data and made amendment.A said low level pulse greater than 300ns adopts following steps to obtain:
The sequential of writing that DSP is provided with EMIF (being external memory interface) the control register CE1CTL of its
(being that sheet selects 1) address space is its slowest sequential; Promptly " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle; Add up to 81 DSP cycles; Wherein cpu cycle is 9.6ns, and the time of DSP mono-recordable is 81x 9.6ns=777.6ns like this.Like this when DSP need reshuffle FPGA; DSP carries out write operation to certain address of
address space; Gating three or eight code translators are connecting that road output of FPGA's
pin; Make this output produce the low level pulse that width is 777.6ns (=DSP instruction cycle 9.6ns x mono-recordable periodicity 81),
FPGA that this low level affacts FPGA will begin the online reconfiguration process.
Preferably, in the said configuration that powers on, the online reconfiguration process and configuration accomplish before the back gets into normal surveying work to DSP control FPGA, receive the switch to the every other equipment of system of FPGA control to be "off" state, guaranteed the safety of system.
Said assurance security of system method is: the system design agreement is by the system switching of FPGA control, and the high level that is defined as of level control closes, and low level is opened, and the negative edge that is defined as of edge control closes, and rising edge is opened; The HSWAP EN pin of FPGA is pulled down to ground through a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch of being controlled by FPGA during the FPGA configuration like this of giving the every other equipment of system is "off" state;
The initial value of all registers of FPGA software setting is ' 1 ', accomplishes before the back gets into normal surveying work to DSP control FPGA in FPGA configuration like this, receives the switch to the every other equipment of system of FPGA control to be "off" state.
The invention has the advantages that, providing the time-delay configured strategy that powers on to avoid starting shooting moment, reduced simultaneously confession distribution designing requirement because power-supply fluctuation causes the generation of FPGA configuration error; Utilize DSP that the configuration performance of FPGA is monitored; Avoided in the high radiation environment of space the FPGA configuration and interrupted causing configuration to get nowhere causing the total system can not normal boot-strap work owing to meet with the single-particle function; Monitored in real time by DSP, the automatic startup of DSP meeting reshuffled when finding that the FPGA configuration is unsuccessful, do not need the ground artificial intervention; And recover much fast than manual intervention, also reduce the switch number of times of relay; Regularly reshuffle, adopt the SRAM type FPGA of triplication redundancy design, regularly reshuffle and prevent to make a mistake owing to adding up of single-particle inversion causes the function of FPGA in the high radiation environment of space, working for a long time; The cycle of regularly reshuffling can be injected through ground data and made amendment; Be operated in the satellite borne equipment of space environment like this,, obtain moderate reshuffling the cycle of frequency through the data accumulation of a period of time; Inject the default cycle of regularly reshuffling of revising software setting through ground data; Also can such as strengthening, can inject relatively short regularly reshuffling the cycle this moment simultaneously according to the variation of irradiation space level at the solar activity peak year radiation level.
Description of drawings
Fig. 1 is the schematic flow sheet of raising FPGA reliability of the present invention;
Fig. 2 is the implementation strategy of the present invention synoptic diagram that combines with the actual FPGA configuration flow;
Fig. 3 is the composition synoptic diagram of the configuration-system that specifically powers on provided by the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
As shown in Figure 1; The FPGA of spaceborne system of the present invention adopts the triplication redundancy design; Accumulation ground for fear of cause the FPGA local error owing to single-particle inversion takes place; The invention provides and comprise: the configuration that powers on, configuration monitoring, online reconfiguration and layout strategy such as regularly reshuffle, concrete workflow is:
The step that powers on, said FPGA adopts the moment power-supply fluctuation of avoiding starting shooting of time-delay collocation strategy to cause configuration error;
Monitoring powers on and accomplishes the step of back configuring condition, and said DSP monitors the said FPGA configuring condition after the end that powers on, if monitor configuration successful then notify said FPGA to get into normal measurement state; If said DSP monitors said FPGA configuration failure, then get into the step that the configuration logic that resets is reshuffled;
The online reconfiguration process is: said DSP start-up control applies a low level pulse greater than 300ns to the arrangement reset pin of said FPGA under the situation of not cutting off the power supply, and accomplishes the reset operation to configuration logic, and FPGA is configured process automatically afterwards.After DSP starts FPGA and reshuffles, equally still to monitor the performance of FPGA configuration, if monitor configuration successful then notify said FPGA to get into normal measurement state; If said DSP monitors said FPGA configuration failure, then get into the step that the configuration logic that resets starts the FPGA online reconfiguration;
Under the normal operating conditions, DSP periodically monitors FPGA whether configuration error has taken place, if then the DSP FPGA configuration logic that resets starts the FPGA online reconfiguration;
Under the normal operating conditions, when timer is regularly reshuffled when interrupt arriving in DSP inside, the DSP FPGA configuration logic that also resets starts the FPGA online reconfiguration;
Wherein, described reconfiguration course comprises: remove config memory, elements with configuration data frame, CRC check and Start-Up process.
As shown in Figure 2, this figure is the implementation strategy of the present invention synoptic diagram that combines with the actual FPGA configuration flow, is described below:
System powers on; As shown in Figure 1 when the FPGA supply voltage satisfy following condition: core voltage VCCINT greater than 1.2V, boosting voltage VCCAUX greater than the IO voltage VCCO of 2.5V, Bank4 greater than 1.5V after; Layoutprocedure enters into the config memory process of removing automatically, and
that remove FPGA in the config memory process is low level;
FPGA configuration pin
is a bi-directional pin; This pin can also utilize the outside to make it remain low level ' 0 '; FPGA is maintained know in the config memory process; House dog output signal of the present invention
is linked this pin; Its
keeps low level 200ms after utilizing house dog to power on; The FPGA configuration flow maintains the config memory process of removing in this 200ms; After
signal became high level ' 1 ', FPGA just began follow-up configuration process.When configuration process detects
for behind the high level ' 1 '; FPGA configuration process inspection configuration mode pin; The configuration RAM from program storage elements with configuration data frame to FPGA, carry out CRC check more afterwards.If the CRC check value does not match; Then
becomes low level sign CRC check failure, and layoutprocedure finishes.If CRC check is correct, then its configuration pin " DONE " becomes high level ' 1 '; Carry out Start-Up again, FPGA just gets into user's control model afterwards.The present invention links the general input pin of DSP with configuration pin " DONE " through phase inverter exactly, and DSP judges through inquiry this general input pin whether FPGA correctly disposes.
If desired FPGA is carried out online reconfiguration; Only need its arrangement reset pin
is applied the level of a width greater than 300ns; The configuration logic that just can reset,
begins the above-mentioned processes such as config memory, elements with configuration data frame, CRC check, Start-Up of knowing after uprising level automatically.
As shown in Figure 3, this figure is the composition synoptic diagram of a concrete FPGA configuration and monitoring system.Specifically describe as follows:
1) power on time-delay configuration design
The purpose of time-delay configuration be avoid powering on during owing to power-supply fluctuation causes configuration error; Method is the low level that its output when utilizing U1Max706 to power on
produces 200ms, this signal is received
pin of FPGA and just can be realized postponing to dispose behind the 200ms after FPGA powers on.
2) the reliability safeguard of output control during FPGA powers on and disposes
The system switching that system design agreement FPGA controls, the high level that is defined as of the flat control of level closes, and low level is opened, and closes along the negative edge of controlling that is defined as, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground through a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, receive the switch of giving the every other equipment of system of FPGA control to be "off" state like this during the FPGA configuration;
The initial value of all registers of FPGA software setting is ' 1 ', accomplishes before the back gets into normal surveying work to DSP control FPGA in FPGA configuration like this, receives the switch to the every other equipment of system of FPGA control to be "off" state.
3) DSP monitors design to the configuring condition of FPGA
The necessity that DSP monitors the configuration of FPGA is:
System powers on back DSP need be from PROM U9 boot to its sheet internal program RAM; FPGA also need be from its PROM U8 boot to the configuration RAM of FPGA simultaneously; Since the DSP boot adopt parallel mode, guiding speed fast, need the program of guiding little, so actual result is that DSP accomplished program designation in 2.8 seconds approximately in advance than FPGA.If DSP did not detect the TINP1 mouth for ' 0 ' during system power-up in 3 seconds, then represent the FPGA configuration failure that powers on.
FPGA load and operate as normal after, its " DONE " pin should remain on ' height ' level, as not then the configuration logic of explanation FPGA taken place to cause configuration error because of reasons such as SEU.Therefore DSP still need monitor the FPGA configuration pin through its TINP1 mouth at any time after the operate as normal.
If DSP loads because its watchdog reset causes; And the DSP program fleet causes one of possible reason of watchdog reset is that FPGA has met with the SEU mistake; Cause FPGA and DSP communication to be broken down; This moment is if DSP loads promptly to work after starting working of their own, do not find the fault of FPGA and handles, and its result only possibly be that DSP is ceaselessly from resetting.Can't from fault, recover.
The configuration pin of hardware designs FPGA " DONE " is linked DSP at this timer TINP1 mouth as general input port through phase inverter; Dsp software is designed to the DSP back of starting working and just ceaselessly inquires about its TINP1 mouth with 10ms interval; When inquiring the TINP1 mouth for ' 0 ', expression FPGA has disposed completion (configuration pin " DONE " that is FPGA is drawn high ' 1 '), and DSP write the height control word, measured AGC value, the control of DDS bandwidth etc. to FPGA this moment; Opens interrupters; And the sequential control of notice FPGA unlatching radar, DSP and FPGA all get into normal surveying work pattern, and whole radar altitude meter systems begins to measure.4) DSP reshuffles FPGA
Hardware designs
Under the situation of electricity its configuration pin
is not applied a low level that is not less than 300ns down at FPGA, FPGA will reconfigure; But must guarantee that design reshuffles circuit and should not influence the FPGA self-configuring that powers on.
The circuit hardware design is like Fig. 3.The EA17 of DSP, EA18 link two input end A, the B of code translator LVC138; DSP output chip enable signal CE1 drives LVTH16244 through line and is divided into two-way output, one tunnel
low level of giving code translator LVC138 effectively sheet select input end.It is that the Memory Mapped of DSP is MAP1 that the hardware designs of DSP makes BOOTMODE [4:0]=" 01101 ".
The dsp software design
The software design of DSP is provided with the read/write sequential of the EMIF control register CE1CTL of CE1 address space and uses its slowest default sequential; Be that Set/Strobe/Hold is respectively 15/63/3 DSP clock period; Because the clock period of hardware designs DSP is 9.6ns, when Memory Mapped is MAP1.The method for reconfiguration that DSP starts FPGA is that address 0x01460000 is carried out the single write operation; Corresponding like this CE1=' 0 '; EA17=' 1 ' EA18=' 1 '; Through three or eight code translator LVC138; Its output Y4 pin just produces the low level of a width for (15+63+3) Cycle * 9.6ns=777.6ns, and this low level width is greater than 300ns, through R4
pin to FPGA.
What this programme designed is regularly FPGA to be reshuffled; The superiority of regularly reshuffling is that satellite is after observation in orbit after a while; Obtain the cycle of more regularly reshuffling and finally receive and understand and carry out, just do not need manual intervention afterwards by DSP through annotating data block on the ground; Find the SEU mistake term of execution of on the other hand as if task, can also go up very short regularly the reshuffling the cycle of notes (about 3 minutes) and realize resetting immediately, also need inject more normally after having resetted and regularly reshuffle the cycle.
Reshuffle the influence that circuit powers on and disposes FPGA:
This reshuffles the configuration that powers on that circuit design can not influence FPGA.The address 0x01460000 of DSP is exclusively used in and reshuffles FPGA, other whenever only otherwise read/write operation is carried out in this address, the Y4 output pin of LVC138 is exactly a high-impedance state, can not exert an influence to FPGA.
Extendability is analyzed
" DSP+FPGA " architecture design has become comparatively general high-speed digital signal processing platform at present, has been widely used in the fields such as software radio of radar signal tracking processing, realtime graphic processing, communication aspect, and utilization is widely also arranged on satellite borne equipment.This FPGA configuration observation circuit all can use in the design of any " DSP (or CPU)+SRAM type FPGA ", is a kind of simple and effective high reliability design.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is specified with reference to embodiment; Those of ordinary skill in the art is to be understood that; Technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and the scope of technical scheme of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (14)
1. collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work; Be used to improve reliability at the spaceborne SRAM type FPGA of the medium-term and long-term work of the high radiation environment of space; Wherein this FPGA adopts the triplication redundancy design to improve its reliability; Said method utilizes DSP to realize the FPGA configuration in the said spaceborne SRAM type FPGA reliability, specifically comprises:
Regularly reshuffle step, this step is to the FPGA in the surveying work, and DSP regularly carries out online reconfiguration to said FPGA;
The step of monitoring; This step comprises monitors power on configuration and online reconfiguration; Said DSP is to the configuration and monitor substep by the performance of the FPGA online reconfiguration of DSP control of powering on of FPGA, and the configuring condition that is in the FPGA in the operate as normal is monitored substep; In the official hour section, fail normal accomplish configuration or be in FPGA in the operate as normal when configuration error takes place when said DSP monitors said FPGA, said DSP carries out online reconfiguration to said FPGA;
Wherein, the said cycle of regularly reshuffling can be injected through ground data and made amendment;
Said DSP carries out the online reconfiguration process to said FPGA: said DSP start-up control applies a low level pulse greater than 300ns to the arrangement reset pin of said FPGA under the situation of not cutting off the power supply; Completion is to the reset operation of configuration logic, and FPGA is configured process automatically afterwards.
2. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1 is characterized in that, the back that powers on of said FPGA adopts the moment power-supply fluctuation of avoiding starting shooting of time-delay collocation strategy to cause configuration error.
3. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1 is characterized in that described delaying policy is:
Its output pin when utilizing house dog to power on
produces the low level of 200ms, this signal is received
pin of FPGA and just can be realized postponing to dispose behind the 200ms after FPGA powers on;
Wherein, the described FPGA of this mode comprises: ground or spaceborne SRAM type FPGA.
4. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1; It is characterized in that described reconfiguration course comprises: step, the step of elements with configuration data frame, the step of CRC check and the step of Start-Up of removing config memory.
5. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1; It is characterized in that; The configuration that powers on of said DSP monitoring FPGA reaches the performance substep by the FPGA online reconfiguration of DSP control: be ' 0 ' if said DSP detects its general input port TINP1 mouth in 3 seconds after the operate as normal that powers on; Or start by DSP and not detect its general input port TINP1 mouth in 3 seconds after the FPGA online reconfiguration and be ' 0 ', then represent the FPGA configuration failure; Be ' 0 ' if said DSP detected its general input port TINP1 mouth in 3 seconds, then represent this FPGA configuration successful, DSP notice FPGA gets into normal surveying work state.
6. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1; It is characterized in that; Said DSP monitors substep to the configuring condition that is in the FPGA in the normal surveying work: said DSP is through the said FPGA configuration pin of its TINP1 mouth periodic monitoring; When FPGA got into normal operating conditions, its " DONE " pin should remain on ' height ' level, and this signal is connected to the TINP1 of DSP through phase inverter; TINP1 should remain on ' low ' level, as not then can know that fault has taken place the configuration logic of this FPGA.
7. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1 is characterized in that a said low level pulse greater than 300ns adopts following steps to obtain:
Said DSP is provided with its sheet and selects the sequential of writing of the external memory interface control register CE1CTL of 1 pin address space to be its slowest sequential; Promptly " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle; Add up to 81 DSP cycles; Wherein cpu cycle is 9.6ns, and the time of said DSP mono-recordable is 81x 9.6ns=777.6ns; When DSP need reshuffle FPGA; Said DSP selects certain address of 1 address space to carry out write operation to sheet; Gating three or eight code translators are connecting that road output of the arrangement reset pin of FPGA; Make this output produce the low level pulse that width is 777.6ns, this low level affacts the arrangement reset pin of FPGA, and said FPGA begins the online reconfiguration process.
8. the collocation method that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 1; It is characterized in that; The said layoutprocedure that powers on, online reconfiguration process and configuration are accomplished the back and are controlled FPGA to DSP and get into before the normal surveying work; Receive the switch of giving the every other equipment of system of FPGA control to be "off" state, be used to the safety of the system that guarantees.
9. said according to Claim 8 assurance security of system method is:
The system switching of system design agreement FPGA control, the high level that is defined as of level control closes, and low level is opened, and the negative edge that is defined as of edge control closes, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground through a resistance, can ensure that all I/O are high electricity ' 1 ' during FPGA powers on configuration, the switch of being controlled by FPGA during the FPGA configuration like this of giving the every other equipment of system is "off" state;
The initial value that said FPGA is provided with all registers is ' 1 ', accomplishes before the back gets into normal surveying work to DSP control FPGA in FPGA configuration, receives the switch to the every other equipment of system of said FPGA control to be "off" state.
10. configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work, comprise: DSP, FPGA and some PROM is characterized in that said system also comprises:
The time-delay collocation method that powers on, the configuration pin
that is connected to FPGA with the reset output terminal mouth of house dog is postponed the FPGA boot;
The configuration monitoring method; The configuration pin of FPGA " DONE " is linked the general input port of DSP through phase inverter; After the FPGA normal configuration is accomplished; Its configuration pin " DONE " can drawn high automatically be ' 1 ', and this configuration pin is connected to the general input port of DSP through phase inverter, and DSP judges through inquiry this general input port whether FPGA disposes correct;
Method for reconfiguration, when said DSP monitored said FPGA configuration error or regularly reshuffles the interruption arrival, under the situation of not cutting off the power supply, said DSP started the online reconfiguration to said FPGA;
The said cycle of reshuffling regularly can be injected through ground data and made amendment.
11. the configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 10 is characterized in that said monitoring means physical circuit is:
The configuration pin of said FPGA " DONE " is linked the general input port of DSP through phase inverter; After said FPGA normal configuration is accomplished; Configuration pin " DONE " can be drawn high automatically is ' 1 '; This configuration pin is connected to the general input port of said DSP through said phase inverter, and said DSP judges through inquiry this general input port whether FPGA disposes correct.
12. the configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 10 is characterized in that a said low level pulse greater than 300ns adopts following steps to obtain:
Said DSP is provided with its sheet and selects the sequential of writing of the external memory interface control register CE1CTL of 1 address space to be its slowest sequential; Promptly " foundation/gating/maintenance " time is respectively " 15/63/3 " individual DSP cycle; Add up to 81 DSP cycles; Wherein cpu cycle is 9.6ns, and the time of said DSP mono-recordable is 81x 9.6ns=777.6ns; When said DSP need reshuffle said FPGA; Said DSP selects certain address of 1 address space to carry out write operation to sheet; Gating three or eight code translators are connecting that road output of the arrangement reset pin of said FPGA; Make this output produce the low level pulse that width is 777.6ns, this low level affacts the arrangement reset pin of FPGA, and said FPGA begins the online reconfiguration process.
13. the configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 10; It is characterized in that; In configuration, the online reconfiguration process of powering on; And configuration accomplishes before the back gets into normal surveying work to DSP control FPGA, receives the switch to the every other equipment of system of said FPGA control to be "off" state, is used to the safety of the system that guarantees.
14. the configuration-system that is used for for a long time at the spaceborne SRAM type FPGA of rail work according to claim 13 is characterized in that said assurance security of system method is:
The system switching that system design agreement FPGA controls, the high level that is defined as of the flat control of level closes, and low level is opened, and closes along the negative edge of controlling that is defined as, and rising edge is opened;
The HSWAP_EN pin of FPGA is pulled down to ground through a resistance; Can ensure that all I/0 are high electricity ' 1 ' during FPGA powers on configuration, the switch of being controlled by said FPGA during the FPGA configuration like this of giving the every other equipment of system is "off" state;
The initial value that said FPGA is provided with all registers is ' 1 '; Accomplish the back in said FPGA configuration and control to said DSP before said FPGA gets into normal surveying work, receive the switch to the every other equipment of system of said FPGA control to be "off" state.
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Address after: 100190 No. two south of Zhongguancun, Haidian District, Beijing 1 Patentee after: NATIONAL SPACE SCIENCE CENTER, CAS Address before: 100190 No. two south of Zhongguancun, Haidian District, Beijing 1 Patentee before: Space Science & Applied Research Centre, Chinese Academy of Sciences |
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