CN105260001B - Reset circuit for field programmable gate array - Google Patents
Reset circuit for field programmable gate array Download PDFInfo
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- CN105260001B CN105260001B CN201510591528.5A CN201510591528A CN105260001B CN 105260001 B CN105260001 B CN 105260001B CN 201510591528 A CN201510591528 A CN 201510591528A CN 105260001 B CN105260001 B CN 105260001B
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- threshold value
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Abstract
The invention discloses the reset circuits for field programmable gate array, the reset circuit includes: read-only memory, it is provided with the log-on data for field programmable gate array in read-only memory, and is configured with the port matched with field programmable gate array；The output end of power circuit, power circuit is connected to read-only memory and field programmable gate array；The reset circuit overcomes the problem of field programmable gate array load failure in the prior art, avoids field programmable gate array and load fault occurs.
Description
Technical field
The present invention relates to the gain and loss electrical domains of electric elements, and in particular, to one kind is used for field programmable gate battle array
The reset circuit of column.
Background technique
Since FPGA (field programmable gate array) technology is more and more mature, so that the function of FPGA is also increasingly stronger
Greatly, it due to its good real-time and sampling property, has been obtained in terms of video frequency signal processing, light sensing extensive
Using.It can be improved the precision of sampled data and the real-time of adjusting using FPGA.
The more and more outfit LCD liquid crystal display screens of electronic product, such as display in mobile phone, TV, military project avionics system,
The part such as LCD driving, signal processing, backlight driver has used FPGA, FPGA to will appear weight when power supply has low voltage pulse
The phenomenon that new load, may sometimes result in FPGA and be in the abnormal work phenomenon loaded always, once FPGA load failure, can lead to
Phenomena such as backlight is extinguished, signal picture cannot normally be shown, product will be unable to normal use, if display in military project avionics system
In there is this phenomenon, influence extremely serious.
Electronic product, since power-type device and capacitor moment take electricity, can cause power supply a few tens of milliseconds occur in the moment that is powered
Low voltage pulse, the low voltage pulse of this kind of a few tens of milliseconds can allow field programmable gate array showing for load fault occur
As.
Summary of the invention
The object of the present invention is to provide a kind of reset circuit for field programmable gate array, the reset circuits gram
The problem of having taken field programmable gate array load failure in the prior art, avoids field programmable gate array and goes out
Existing load fault.
To achieve the goals above, the present invention provides a kind of reset circuit for field programmable gate array,
It is characterized in that, the reset circuit includes: read-only memory, it is provided in the read-only memory for field programmable logic
The log-on data of gate array, and it is configured with the port matched with the field programmable gate array；Power circuit, institute
The output end for stating power circuit is connected to the read-only memory and the field programmable gate array；
The power circuit includes: threshold value wave detector, first capacitor, the second capacitor, first resistor, second resistance and third
Capacitor, the 4th of the first pin of the threshold value wave detector, the second pin of the threshold value wave detector and the threshold value wave detector the
Pin is both connected to the first power supply, passes through first electricity between the second pin and the first power supply of the threshold value wave detector respectively
Hold and the second capacity earth, the third pin are grounded；7th pin of the threshold value wave detector is extended by first resistor
Output end；The of 5th pin of the threshold value wave detector, the 6th pin of the threshold value wave detector and the threshold value wave detector
Eight pin skies connect.
Preferably, the first capacitor is tantalum capacitor, and second capacitor and the third capacitor are ceramic condenser.
Preferably, the threshold value wave detector is the chip of model ADM706P.
Preferably, the threshold value wave detector is the chip of model ADM706R.
Preferably, the read-only memory includes: the read-only chip of model XCF04SVOG20C, 3rd resistor, the 4th
Resistance and the 5th resistance, the 7th pin of the read-only chip are connected to the output end of the power circuit, and power supply electricity
The output end on road is connected to one end of the 3rd resistor, and the other end of the 3rd resistor is connected to second source, institute
One end of the 4th resistance and one end of the 5th resistance are stated, the other end of the 4th resistance is connected to the read-only chip
The other end of tenth pin, the 5th resistance is connected to the 8th pin of the read-only chip.
Preferably, the second pin of the read-only chip, the 9th pin of read-only chip, read-only chip the 12nd draw
Foot, the 13rd pin of read-only chip, the 14th pin of read-only chip, the 15th pin of read-only chip and read-only chip
16th pin is all that sky connects.
Preferably, the 19th pin of the read-only chip and the 20th pin are connected to the second source.
Preferably, the 18th pin of the read-only chip is connected to the second source.
Preferably, the voltage of first power supply is 3.3V；The voltage of first power supply is 2.5V.
By above-mentioned specific embodiment, power circuit of the invention detects voltage value lower than required voltage value
When, chip will export the low level of 200ms, it ensure that the working properly of electronic device, when power supply power supply is normal after 200ms,
The voltage continuity of power circuit can be effectively avoided the electronic device as caused by voltage fluctuation and be constantly in job failure shape
The phenomenon that state, in addition, on the one hand the reset circuit for field programmable gate array of the invention can be effectively avoided
The phenomenon of the failure that the field programmable gate array as caused by voltage fluctuation is constantly in stress state occurs, on the other hand
The programmable gate array can be given with enabling signal by read-only memory, to be started.
Other features and advantages of the present invention will the following detailed description will be given in the detailed implementation section.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 (a) is the circuit connection diagram for illustrating a kind of power circuit of preferred embodiment of the invention；
Fig. 1 (b) is the circuit connection diagram for illustrating a kind of read-only memory of preferred embodiment of the invention；And
Fig. 2 be illustrate a kind of preferred embodiment of the invention power circuit work after ADM706P or ADM706R work
Make waveform diagram.
Specific embodiment
Below in conjunction with attached drawing, detailed description of the preferred embodiments.It should be understood that this place is retouched
The specific embodiment stated is merely to illustrate and explain the present invention, and is not intended to restrict the invention.
The present invention provides a kind of power circuit, and as shown in Fig. 1 (a), Fig. 1 (b) and Fig. 2, the present invention provides one kind to be used for
The reset circuit of field programmable gate array, which is characterized in that the reset circuit includes: read-only memory, described read-only
It is provided with the log-on data for field programmable gate array in memory, and is configured with and is patrolled with the field-programmable
Collect the port that gate array matches；Power circuit, the output end of the power circuit be connected to the read-only memory and
The field programmable gate array；
The power circuit includes: threshold value wave detector, first capacitor, the second capacitor, first resistor, second resistance and third electricity
Hold, the first pin of the threshold value wave detector, the second pin of the threshold value wave detector and the threshold value wave detector the 4th draw
Foot is both connected to the first power supply, passes through the first capacitor respectively between the second pin and the first power supply of the threshold value wave detector
With the second capacity earth, the third pin ground connection；7th pin of the threshold value wave detector is extended defeated by first resistor
Outlet；The 8th of 5th pin of the threshold value wave detector, the 6th pin of the threshold value wave detector and the threshold value wave detector
Pin sky connects.
By above-mentioned power circuit, can to avoid electronic product in the moment that is powered due to power-type device and capacitor moment
Electricity is taken, power supply can be caused the problem of low voltage pulse of a few tens of milliseconds occur, when power circuit detects voltage value lower than required
Voltage value when, chip will export the low level of 200ms, ensure that the working properly of electronic device, power supply power supply after 200ms
When normal, the voltage continuity of power circuit, certain 200ms is setting value, it can be changed therewith, by resetting electricity
On the one hand road can be effectively avoided generation field programmable gate array as caused by voltage fluctuation and be constantly in load shape
The phenomenon of the failure of state, on the other hand can also by read-only memory to the programmable gate array with enabling signal, from
And started, the present invention can effectively solve that FPGA (field programmable gate array) is caused to be constantly in due to power-supply fluctuation
The failure of stress state.As shown in Fig. 1 (a), 7 feet of U1 are connected with the load pin PROG_B (7 feet of U2) of FPGA, 200ms
Interior FPGA is not loaded with, and power supply power supply is normal after 200ms, and FPGA can be loaded smoothly.
The present invention will be further described below with reference to FIG. 1 and FIG. 2, in the accompanying drawings,
R1~R5 is respectively first resistor, second resistance, 3rd resistor, the 4th resistance and the 5th resistance；
C1~C3 is respectively first capacitor, the second capacitor and third capacitor；
U1, ADM706P/R；
U2, XCF04SVOG20C.
In a kind of specific embodiment of the invention, in order to realize that above-mentioned effect, the first capacitor are tantalum capacitor,
And second capacitor and the third capacitor are ceramic condenser.
In this embodiment, the threshold value wave detector is the chip of model ADM706P, certainly, the threshold value inspection
Wave device can also be the chip of model ADM706R.
In this embodiment, the read-only memory includes: the read-only chip of model XCF04SVOG20C, third
Resistance, the 4th resistance and the 5th resistance, the 7th pin of the read-only chip are connected to the output end of the power circuit, and institute
The output end for stating power circuit is connected to one end of the 3rd resistor, and the other end of the 3rd resistor is connected to second
Power supply, one end of the 4th resistance and the 5th resistance one end, the other end of the 4th resistance be connected to it is described only
The tenth pin of chip is read, the other end of the 5th resistance is connected to the 8th pin of the read-only chip.
In addition, remaining pin connection of read-only chip is as shown in Fig. 1 (b), it is all to be attached with the effective port of FPGA,
It should be noted that in this way, FPGA can read effective start-up parameter in read-only chip, realize final
Starting.
In a kind of specific embodiment of the invention, the second pin of the read-only chip, the 9th of read-only chip draw
Foot, the 12nd pin of read-only chip, the 13rd pin of read-only chip, the 14th pin of read-only chip, read-only chip
16th pin of the 15th pin and read-only chip is all that sky connects.
In this embodiment, the 19th pin of the read-only chip and the 20th pin are connected to described
Two power supplys.
In this embodiment, the 18th pin of the read-only chip is connected to first power supply.
In this embodiment, the voltage of first power supply is 3.3V；The voltage of the second source is 2.5V.
Circuit of the invention realizes that simply pure hardware circuit composition does not use controller, and cost of implementation is cheap.
It is described the prefered embodiments of the present invention in detail above in conjunction with attached drawing, still, the present invention is not limited to above-mentioned realities
The detail in mode is applied, within the scope of the technical concept of the present invention, a variety of letters can be carried out to technical solution of the present invention
Monotropic type, these simple variants all belong to the scope of protection of the present invention.
It is further to note that specific technical features described in the above specific embodiments, in not lance
In the case where shield, can be combined in any appropriate way, in order to avoid unnecessary repetition, the present invention to it is various can
No further explanation will be given for the combination of energy.
In addition, various embodiments of the present invention can be combined randomly, as long as it is without prejudice to originally
The thought of invention, it should also be regarded as the disclosure of the present invention.
Claims (8)
1. a kind of reset circuit for field programmable gate array, which is characterized in that the reset circuit includes: read-only deposits
Reservoir is provided with the log-on data for field programmable gate array in the read-only memory, and is configured with and institute
State the port that field programmable gate array matches；Power circuit, the output end of the power circuit are connected to institute
State read-only memory and the field programmable gate array；
The power circuit includes: threshold value wave detector, first capacitor, the second capacitor, first resistor, second resistance and third electricity
Hold, the first pin of the threshold value wave detector, the second pin of the threshold value wave detector and the threshold value wave detector the 4th draw
Foot is both connected to the first power supply, passes through the first capacitor respectively between the second pin and the first power supply of the threshold value wave detector
It is grounded with the third pin of the second capacity earth, the threshold value wave detector；7th pin of the threshold value wave detector passes through first
Resistance extends output end；5th pin of the threshold value wave detector, the 6th pin of the threshold value wave detector and the threshold value
8th pin sky of wave detector connects.
2. reset circuit according to claim 1, which is characterized in that the first capacitor is tantalum capacitor, and described second
Capacitor and the third capacitor are ceramic condenser.
3. reset circuit according to claim 1, which is characterized in that the threshold value wave detector is model ADM706P's
Chip.
4. reset circuit according to claim 1, which is characterized in that the read-only memory includes: model
Read-only chip, 3rd resistor, the 4th resistance and the 5th resistance of XCF04SVOG20C, the 7th pin connection of the read-only chip
One end of the 3rd resistor is connected in the output end of the output end of the power circuit, and the power circuit, described
The other end of three resistance is connected to one end of second source, one end of the 4th resistance and the 5th resistance, described
The other end of 4th resistance is connected to the tenth pin of the read-only chip, and the other end of the 5th resistance is connected to described
Read the 8th pin of chip.
5. reset circuit according to claim 4, which is characterized in that the second pin of the read-only chip, read-only chip
The 9th pin, the 12nd pin of read-only chip, the 13rd pin of read-only chip, read-only chip the 14th pin, only
16th pin of the 15th pin and read-only chip of reading chip is all that sky connects.
6. reset circuit according to claim 4, which is characterized in that the 19th pin of the read-only chip and the 20th
Pin is connected to the second source.
7. reset circuit according to claim 4, which is characterized in that the 18th pin of the read-only chip is connected to institute
State the first power supply.
8. reset circuit according to claim 4, which is characterized in that the voltage of first power supply is 3.3V；Described
The voltage of two power supplys is 2.5V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510591528.5A CN105260001B (en) | 2015-09-15 | 2015-09-15 | Reset circuit for field programmable gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510591528.5A CN105260001B (en) | 2015-09-15 | 2015-09-15 | Reset circuit for field programmable gate array |
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| Publication Number | Publication Date |
|---|---|
| CN105260001A CN105260001A (en) | 2016-01-20 |
| CN105260001B true CN105260001B (en) | 2019-02-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510591528.5A Active CN105260001B (en) | 2015-09-15 | 2015-09-15 | Reset circuit for field programmable gate array |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106843435A (en) * | 2016-12-21 | 2017-06-13 | 深圳市紫光同创电子有限公司 | A kind of chip reset circuit and method for PLD |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499340A (en) * | 2002-11-08 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Loading method for ensuring to load programmable part reliably |
| CN102779079A (en) * | 2011-05-12 | 2012-11-14 | 中国科学院空间科学与应用研究中心 | Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time |
| CN103218025A (en) * | 2013-04-25 | 2013-07-24 | 北京空间机电研究所 | Modified Xilinx FPGA power-on reset circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9515643B2 (en) * | 2014-01-06 | 2016-12-06 | Lattice Semiconductor Corporation | Hot-socket circuitry |
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2015
- 2015-09-15 CN CN201510591528.5A patent/CN105260001B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499340A (en) * | 2002-11-08 | 2004-05-26 | 深圳市中兴通讯股份有限公司 | Loading method for ensuring to load programmable part reliably |
| CN102779079A (en) * | 2011-05-12 | 2012-11-14 | 中国科学院空间科学与应用研究中心 | Configuration method and system used for satellite-bone SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) working on track for long time |
| CN103218025A (en) * | 2013-04-25 | 2013-07-24 | 北京空间机电研究所 | Modified Xilinx FPGA power-on reset circuit |
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| CN105260001A (en) | 2016-01-20 |
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