CN215449918U - Circuit structure for realizing power-off time sequence of power supply - Google Patents
Circuit structure for realizing power-off time sequence of power supply Download PDFInfo
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- CN215449918U CN215449918U CN202122058200.0U CN202122058200U CN215449918U CN 215449918 U CN215449918 U CN 215449918U CN 202122058200 U CN202122058200 U CN 202122058200U CN 215449918 U CN215449918 U CN 215449918U
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Abstract
The utility model relates to a circuit structure for realizing power-off time sequence of a power supply, which comprises a first DC-DC power supply chip, a second DC-DC power supply chip and a power supply monitoring module, wherein the first DC-DC power supply chip, the second DC-DC power supply chip and the power supply monitoring module all receive 12V input voltage, the first DC-DC power supply chip is connected with 3.3V power supply voltage, the second DC-DC power supply chip is connected with 1.8V power supply voltage, and the power supply monitoring module is connected with the second DC-DC power supply chip. Compared with the design scheme adopting the special chip control, the scheme has the advantage that the cost is only 1/5 of the latter, and the scheme can realize the power supply power-off control at low cost.
Description
Technical Field
The utility model relates to the field of power-on and power-off sequential circuits, in particular to a power-on and power-off sequential circuit structure.
Background
The power supply time sequence design is an important ring in hardware design, and various time sequence requirements are met for a chip on a single board so as to ensure that the whole circuit structure can be started and operated normally; usually, a chip has a requirement on a power-on time sequence, the design of the power supply is easy to realize, and for some special chips such as an FPGA, the power-off time sequence is required besides the power-on time sequence, namely, the power supply which is powered on later needs to be powered off later:
electrifying sequence: group1> group 2;
the power-off sequence is as follows: group1< group 2;
such timing control designs are relatively complex, with a common scheme using a dedicated controllable timing control chip; the utility model provides a power supply power-off time sequence scheme, which can effectively realize power-off time sequence control under the condition of low cost, and only one reset chip SGM706 is needed to be added.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome the defects of the prior art and provides a circuit structure for realizing the power-off time sequence of a power supply, which has the advantages of simple circuit, accurate control and wider application range.
In order to achieve the above object, the power down sequence circuit structure of the present invention is as follows:
the circuit structure for realizing power-off of the power supply is mainly characterized by comprising a first DC-DC power supply chip, a second DC-DC power supply chip and a power supply monitoring module, wherein the first DC-DC power supply chip, the second DC-DC power supply chip and the power supply monitoring module all receive 12V input voltage, the first DC-DC power supply chip is connected with 3.3V power supply voltage, the second DC-DC power supply chip is connected with 1.8V power supply voltage, and the power supply monitoring module is connected with the second DC-DC power supply chip.
Preferably, the power supply monitoring module is an SGM706 power supply chip.
Preferably, the chip of the power supply monitoring module has a PFO pin, a PFI pin, an MR pin, a VCC pin, and a GND pin, the PFI pin is connected to a resistance voltage dividing circuit structure, the PFO pin is connected to an output level, the VCC pin is connected to a 3.3V voltage, the MR pin is connected to a 3.3V voltage through a resistance, and the GND pin is connected to ground.
Preferably, when the circuit structure is started, the first DC-DC power supply chip is powered on to start, supply power and enable the power supply monitoring module.
Preferably, the trigger voltage of the circuit structure is 7.5V, and when the power supply monitoring module monitors that the power supply voltage is reduced to 7.5V, the chip pin of the power supply monitoring module outputs a low level, and pulls down the EN pin of the second DC-DC power supply chip to turn off the power supply.
Preferably, the comparison level of the PFI pin of the power monitoring module is 1.25V, and when the external input voltage is lower than 1.25V, the PFO pin changes level.
Compared with the design scheme adopting the special chip control, the scheme has the advantage that the cost is only 1/5 of the latter, and the scheme can realize the power supply power-off control at low cost.
Drawings
Fig. 1 is a circuit schematic diagram of an FPGA chip power supply for implementing a power-off timing circuit structure of the power supply of the present invention.
Fig. 2 is a circuit diagram of a DC-DC power supply chip for implementing a power-down timing circuit structure according to the present invention.
Fig. 3 is a circuit diagram of an SGM706 power supply chip implementing a power-down timing circuit structure according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
Referring to fig. 1 to 3, the power supply power-down sequence circuit structure of the present invention includes a first DC-DC power chip, a second DC-DC power chip, and a power supply monitoring module, where the first DC-DC power chip, the second DC-DC power chip, and the power supply monitoring module all receive a 12V input voltage, the first DC-DC power chip is connected to a 3.3V power supply voltage, the second DC-DC power chip is connected to a 1.8V power supply voltage, and the power supply monitoring module is connected to the second DC-DC power chip.
As a preferred embodiment of the present invention, the power supply monitoring module is an SGM706 power supply chip.
As a preferred embodiment of the present invention, the chip of the power supply monitoring module has a PFO pin, a PFI pin, an MR pin, a VCC pin, and a GND pin, the PFI pin is connected to a resistance voltage dividing circuit structure, the PFO pin is connected to an output level, the VCC pin is connected to a 3.3V voltage, the MR pin is connected to a 3.3V voltage through a resistance, and the GND pin is connected to a ground.
As a preferred embodiment of the present invention, when the circuit structure is started, the first DC-DC power supply chip is powered on to start, supply power, and enable the power supply monitoring module.
As a preferred embodiment of the present invention, the trigger voltage of the circuit structure is 7.5V, and when the power supply monitoring module monitors that the power supply voltage is reduced to 7.5V, the chip pin of the power supply monitoring module outputs a low level, and pulls down the EN pin of the second DC-DC power supply chip to turn off the power supply.
As a preferred embodiment of the present invention, the comparison level of the PFI pin of the power supply monitoring module is 1.25V, and when the external input voltage is lower than 1.25V, the PFO pin changes level.
In the specific implementation mode of the utility model, the whole circuit structure consists of a DC-DC power supply chip and an SGM706 power supply chip, the SGM706 can monitor the 12V power supply state in real time, when the SGM706 monitors that the 12V power supply falls (7.5V), a PFO (power fail output) pin of the chip outputs low level, an EN pin of the power supply chip is pulled down in advance to turn off the power supply, and the other power supply starts to be powered down when the 12V power supply falls to 4V, so that the power-down time sequence control is realized.
Fig. 1 is a schematic circuit diagram of a power supply design of an FPGA chip, fig. 2 and fig. 3 are specific circuits designed for a power-off timing sequence of a power supply, and the main working principle is as follows:
the circuit comprises a DC-DC power supply chip PU1 and a power supply monitoring chip U45, and also comprises a resistance capacitance inductance component on the circuit. When the circuit structure starts, 3.3V is firstly electrified and started, power is supplied to U45 and a power chip PU1 is enabled, and the control of an electrifying time sequence is ensured: 3.3V is powered up before 1.8V;
the SGM706 chip is used for realizing the function of power supply monitoring in the design, the comparison level of a PFI pin is 1.25V, and if the external input voltage is lower than 1.25V, the PFO will act to change the level;
according to the scheme, through the resistor voltage division design, the trigger voltage is set at 7.5V, when a 12V power supply is adjusted to 7.5V, the PFO pin of the chip outputs a low level, the EN pin of the PU1 is pulled low, the EN pin of the chip is a switch for enabling the chip, the high level is opened, the low level is closed, and the PU1 power supply output is turned off at the moment, so that the design goal that the power supply which is electrified later is powered off firstly is realized.
Compared with the design scheme adopting the special chip control, the scheme has the advantage that the cost is only 1/5 of the latter, and the scheme can realize the power supply power-off control at low cost.
In this specification, the utility model has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the utility model. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (6)
1. The circuit structure is characterized by comprising a first DC-DC power supply chip, a second DC-DC power supply chip and a power supply monitoring module, wherein the first DC-DC power supply chip, the second DC-DC power supply chip and the power supply monitoring module all receive 12V input voltage, the first DC-DC power supply chip is connected with 3.3V power supply voltage, the second DC-DC power supply chip is connected with 1.8V power supply voltage, and the power supply monitoring module is connected with the second DC-DC power supply chip.
2. The circuit structure for realizing power-off sequence of claim 1, wherein the power monitoring module is an SGM706 power chip.
3. The circuit structure for realizing power-off timing sequence according to claim 1, wherein the chip of the power monitoring module has a PFO pin, a PFI pin, an MR pin, a VCC pin and a GND pin, the PFI pin is connected to a resistance voltage dividing circuit structure, the PFO pin is connected to an output level, the VCC pin is connected to a 3.3V voltage, the MR pin is connected to a 3.3V voltage through a resistance, and the GND pin is grounded.
4. The circuit structure for realizing power-off sequence of claim 1, wherein when the circuit structure is started, the first DC-DC power supply chip is powered on to start, power and enable the power monitoring module.
5. The circuit structure for realizing power-off sequential circuit according to claim 1, wherein the trigger voltage of the circuit structure is 7.5V, and when the power monitoring module monitors that the power voltage is reduced to 7.5V, the chip pin of the power monitoring module outputs a low level, and pulls down the EN pin of the second DC-DC power chip to turn off the power supply.
6. The circuit structure for realizing power-off timing sequence according to claim 1, wherein the comparison level of the PFI pin of the power monitoring module is 1.25V, and when the external input voltage is lower than 1.25V, the PFO pin changes level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122058200.0U CN215449918U (en) | 2021-08-30 | 2021-08-30 | Circuit structure for realizing power-off time sequence of power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122058200.0U CN215449918U (en) | 2021-08-30 | 2021-08-30 | Circuit structure for realizing power-off time sequence of power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215449918U true CN215449918U (en) | 2022-01-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122058200.0U Active CN215449918U (en) | 2021-08-30 | 2021-08-30 | Circuit structure for realizing power-off time sequence of power supply |
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| Country | Link |
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| CN (1) | CN215449918U (en) |
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2021
- 2021-08-30 CN CN202122058200.0U patent/CN215449918U/en active Active
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