CN210091159U - Pure hardware watchdog circuit - Google Patents
Pure hardware watchdog circuit Download PDFInfo
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- CN210091159U CN210091159U CN201920980704.8U CN201920980704U CN210091159U CN 210091159 U CN210091159 U CN 210091159U CN 201920980704 U CN201920980704 U CN 201920980704U CN 210091159 U CN210091159 U CN 210091159U
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Abstract
The utility model discloses a pure hardware watchdog circuit, include: the system comprises a reset watchdog unit, a first switch unit, a second switch unit and a delay unit; the reset watchdog unit comprises a reset watchdog chip U1, a resistor R1, a resistor R2 and a capacitor C1; the manual reset input end of the reset watchdog chip U1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a capacitor C1, the other end of the capacitor C1 is connected to the ground, the monitor output end of the reset watchdog chip U1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected to a power supply, and the monitor input end of the reset watchdog chip U1 is connected with the dog feeding signal output end of the CPU; the utility model discloses a pure hardware watchdog circuit includes under the compatible condition of watchdog function in the past, the CPU problem of resetting when also can solving CPU and dying of action totally.
Description
Technical Field
The utility model relates to an electronic equipment technical field, concretely relates to pure hardware watchdog circuit.
Background
In an electronic system composed of a CPU, since the operation of the CPU is often disturbed by external factors, data confusion of various registers and memories may be caused, a program pointer may be wrong, the program pointer is not in a program area, a wrong program instruction is fetched, and the like, which may cause a dead cycle, normal operation of the program is interrupted, the system controlled by the CPU cannot continue to operate normally, and the whole system may be caused to be in a dead state, with unpredictable results. The watchdog is a circuit which periodically checks the internal condition of the chip and sends a restart signal to the chip once an error occurs. The watchdog command has the highest priority among the interrupts of the program.
However, most of the watchdog circuits in the market are software watchdog circuits, and as shown in fig. 1, when the CPU is completely halted, the watchdog module is halted, and the watchdog cannot be reset. Later, a pure software watchdog circuit was developed, and as shown in fig. 2, a reset chip, such as MAX706, was added between the CPU watchdog and the CPU reset pin. After the reset chip MAX706 is added, when the CPU is completely halted, the WDT _ RST _ OUT signal of the CPU does not feed a dog, after the WDI signal of the MAX706 does not receive the dog feeding signal, a reset signal is output to the CPU through the RST _ OUT, and under the condition of no Switch, the reset signal is directly connected to a reset pin of the CPU to complete the reset of the CPU. However, the CPU will provide the dog feeding signal to the MAX706 only after the software is completely started, and when the device is just powered on, the MAX706 is started earlier than the CPU, and at this time, the CPU cannot provide the dog feeding signal to the MAX706, and without Switch, the MAX706 will frequently reset the CPU, which causes the CPU to be unable to start normally. Under the condition of adding the Switch, the Switch must be ensured to be closed before the CPU is not completely started, and the Switch is opened after the CPU is started; at this time, if the CPU is in a dead halt state, the outputs of all the control pins are disordered, and the Switch is in an off state, the MAX706 still cannot reset the CPU.
Therefore, there is a need in the industry to develop a method or circuit for solving the problem that the CPU cannot be reset when completely halted.
SUMMERY OF THE UTILITY MODEL
The utility model aims at overcoming the not enough of above prior art existence, provide a pure hardware watchdog circuit.
The purpose of the utility model is realized through the following technical scheme:
a hardware-only watchdog circuit, comprising: the system comprises a reset watchdog unit, a first switch unit, a second switch unit and a delay unit; the reset watchdog unit comprises a reset watchdog chip U1, a resistor R1, a resistor R2 and a capacitor C1; the manual reset input end of the reset watchdog chip U1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a capacitor C1, the other end of the capacitor C1 is connected to the ground, the monitor output end of the reset watchdog chip U1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected to a power supply, and the power supply end of the reset watchdog chip U1 is connected with the power supply; the reset output end of the reset watchdog chip U1 is connected with the reset end of the CPU, and the monitor input end of the reset watchdog chip U1 is connected with the dog feeding signal output end of the CPU; the delay unit comprises a delay IC chip U2, a resistor R3, a resistor R4 and a capacitor C2; the reset end of the delay IC chip U2 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with a power supply; the KEY end of the delay IC chip U2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected to the ground, the power supply end of the delay IC chip U2 is connected with one end of the power supply and one end of the capacitor C2, and the other end of the capacitor C2 and the VSS end of the delay IC chip U2 are connected to the ground; the first switch unit comprises a single-pole double-throw switch U3, a resistor R5 and a capacitor C3; the serial port end of the single-pole double-throw switch U3 is connected with the reset manual input end of the reset watchdog chip U1, the NO end of the single-pole double-throw switch U3 is connected with the LED1 end of the delay IC chip U2 and one end of the resistor R5, the other end of the resistor R5 is connected with the power supply, the grounding end of the single-pole double-throw switch U3 is connected to the ground, the V + end of the single-pole double-throw switch U3 is connected with the power supply and one end of the capacitor C3, the other end of the capacitor C3 is connected to the ground, and the IN end of the single-pole double-throw switch U3 is connected with the monitor output end of the reset watchdog chip U1; the second switch unit comprises a single-pole double-throw switch U4, a resistor R6, a resistor R7, a capacitor C5 and a capacitor C6; the serial port end of the single-pole double-throw switch U4 is connected with the KEY end of the delay IC chip U2, the NO end of the single-pole double-throw switch U4 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the monitor output end of the reset watchdog chip U1, the grounding end of the single-pole double-throw switch U4 is connected to the ground through the capacitor C5, the V + end of the single-pole double-throw switch U4 is connected with one end of the power supply and one end of the capacitor C6, the other end of the capacitor C6 is connected to the ground, and the IN end of the single-pole double-throw switch U4 is connected with the power supply through the resistor R7.
Preferably, the model of the reset watchdog chip U1 is MAX706REPA, the model of the delay IC chip U2 is 6368-30E0, and the models of the single-pole double-throw switch U3 and the single-pole double-throw switch U4 are MAX 4586.
The utility model discloses for prior art have following advantage:
the utility model discloses a pure hardware watchdog circuit includes: the reset watchdog unit, the first switch unit, the second switch unit and the delay unit can also solve the problem of CPU reset when the CPU is completely halted under the condition of being compatible with the function of the previous watchdog.
Drawings
Fig. 1 is a schematic diagram of a prior art software-only watchdog circuit.
Fig. 2 is a schematic diagram of a prior art watchdog circuit with an added reset chip.
Fig. 3 is a schematic diagram of the hardware-only watchdog circuit of the present invention.
Fig. 4 is a circuit diagram of the hardware-only watchdog circuit of the present invention.
Detailed Description
The present invention will be further explained with reference to the drawings and examples.
Referring to fig. 3-4, a pure hardware watchdog circuit includes: the system comprises a reset watchdog unit, a first switch unit, a second switch unit and a delay unit; the reset watchdog unit comprises a reset watchdog chip U1, a resistor R1, a resistor R2 and a capacitor C1; a reset manual input end (MR 'end) of the reset watchdog chip U1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a capacitor C1, the other end of the capacitor C1 is connected with the ground, a monitor output end (WDO' end) of the reset watchdog chip U1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with a power supply, and a power supply end (VCC end) of the reset watchdog chip U1 is connected with the power supply; the RESET output end (RESET' end) of the RESET watchdog chip U1 is connected with the RESET end (Hard _ RST _ IN end) of the CPU, and the monitor input end (WDI end) of the RESET watchdog chip U1 is connected with the dog feeding signal output end (WDT _ RST _ OUT end) of the CPU; the delay unit comprises a delay IC chip U2, a resistor R3, a resistor R4 and a capacitor C2; a reset terminal (RST terminal) of the delay IC chip U2 is connected with one end of the resistor R4, and the other end of the resistor R4 is connected with a power supply; the KEY end of the delay IC chip U2 is connected with one end of a resistor R3, the other end of the resistor R3 is connected to the ground, a power supply end (VDD end) of the delay IC chip U2 is connected with one end of a power supply and a capacitor C2, and the other end of the capacitor C2 and the VSS end of the delay IC chip U2 are connected to the ground; the first switch unit comprises a single-pole double-throw switch U3, a resistor R5 and a capacitor C3; a serial port end (COM end) of a single-pole double-throw switch U3 is connected with a reset manual input end (MR 'end) of a reset watchdog chip U1, an NO end of the single-pole double-throw switch U3 is connected with an LED1 end of a delay IC chip U2 and one end of a resistor R5, the other end of the resistor R5 is connected with a power supply, a grounding end (GND) of a single-pole double-throw switch U3 is connected with the ground, a V + end of the single-pole double-throw switch U3 is connected with the power supply and one end of a capacitor C3, the other end of the capacitor C3 is connected with the ground, and an IN end of the single-pole double-throw switch U3 is connected with a monitor output end (WDO' end) of the reset watchdog chip U1; the second switch unit comprises a single-pole double-throw switch U4, a resistor R6, a resistor R7, a capacitor C5 and a capacitor C6; the serial port end (COM end) of the single-pole double-throw switch U4 is connected with the KEY end of the delay IC chip U2, the NO end of the single-pole double-throw switch U4 is connected with one end of a resistor R6, the other end of the resistor R6 is connected with the monitor output end (WDO' end) of the reset watchdog chip U1, the ground end (GND) of the single-pole double-throw switch U4 is connected to the ground through a capacitor C5, the V + end of the single-pole double-throw switch U4 is connected with one end of a power supply and a capacitor C6, the other end of the capacitor C6 is connected to the ground, and the IN end of the single-pole double-throw switch U4 is connected with the power supply through the resistor R7.
In this embodiment, the model of the reset watchdog chip U1 is MAX706REPA, the model of the delay IC chip U2 is 6368-30E0, and the models of the single-pole double-throw switch U3 and the single-pole double-throw switch U4 are MAX 4586. The power supply is + 3.3V.
The CPU _ GPIO _ OUT is an input signal of the reset watchdog chip U1, and is a dog feeding signal output by the CPU to the reset watchdog chip U1, and requires 1.6 seconds to output a pulse. CPU _ RST is the output signal of reset watchdog chip U1, the reset signal output to the CPU, active low. WDO is the output signal of reset watchdog chip U1, and WDO output is low when the 6-pin WDI terminal of reset watchdog chip U1 does not receive the feed dog signal CPU _ GPIO _ OUT. MR is the input signal to the RESET watchdog chip U1, which when low, will set the 7-pin RESET output (RESET' terminal) of the RESET watchdog chip U1 low.
The 6368_30E0 delay IC chip U2 is a 60-second delay IC chip, the LED1 end and the LED2 end are two paths of outputs of 6368_30E0, one path outputs low level, the other path outputs high level, power-on does not work, one key control is used to trigger, the two paths of signals work synchronously, 60 seconds are delayed, the time is up to automatic stop working, and the re-trigger works for 60 seconds. The trigger is invalid in operation. The delay time is 60S, which can ensure that the reset signal is output to reset the CPU when the reset watchdog chip U1 is not controlled by the CPU in the power-on stage.
The circuit function of the pure hardware watchdog circuit of the scheme is described as follows:
1. and (3) electrifying:
(1) when the power-on state is just started, the WDO signal output by the reset watchdog chip U1 slowly becomes high, the single-pole double-throw switch U4 is not conducted, the judgment requirement of the single-pole double-throw switch U4 on the high logic level is more than 2.4V, and the judgment requirement is met according to an RC charging circuit formula
(VtThe value on the capacitor at any time t; v0Is the initial value of the capacitance; vuFor a capacitor full termination voltage value) can calculate that the WDO signal takes 130ms to reach 2.4V.
(2) The single-pole double-throw switch U4 is not conducted, a KEY signal of the single-pole double-throw switch U4 is pulled low through the resistor R3, the time-delay IC chip U2 works, the LED1 end is at a low level when being electrified, and the LED1 end becomes a high resistance after the duration of 60 seconds.
(3) When the signal of the LED1 output by the single-pole double-throw switch U4 is low, the single-pole double-throw switch U3 is not conducted for 60 seconds, and no matter how the WDO signal output by the RESET watchdog chip U1 changes within 60 seconds, the MR signal output by the RESET watchdog chip U1 does not change, at this time, it is the resistor R1 that determines the MR level, and it is always kept high, then the output of the 7-pin RESET output end (RESET' end) of the RESET watchdog chip U1 is high, and the CPU is normally started.
2. The working stage is as follows:
(1) the reset watchdog chip U1 is not fed by the CPU after being powered on, and the WDO signal outputs a low level after being powered on for 1.6S, but does not affect the MR signal and CPU _ RST signal levels of the reset watchdog chip U1. After the CPU is normally started, the reset watchdog chip U1 is fed with dogs, the WDO output is high, and all the operations are normal.
(2) After the level of the WDO signal is high, the NO end of the pin 2 of the single-pole double-throw switch U4 meets the conducting level, at the moment, the KEY signal is pulled up strongly and pulled down weakly, the pin 2 of the U3 is high, and the U3 does not work.
(3) When the delay IC chip U2 does not operate, the LED1 signal goes from resistor R5 to high, WDO goes to MR, WDO is high, MR is high, and CPU _ RST is high.
3. And (3) halting:
(1) after the CPU crashes, the reset watchdog chip U1 is not fed with dogs, the WDO is changed from high to low, the NO end of the 2 pin of the single-pole double-throw switch U4 needs to be reduced from 3.3V to below 2.4V, the single-pole double-throw switch U4 is turned off, before the single-pole double-throw switch U4 is turned off, the KEY signal is still high, the LED1 is still high, the low signal of the WDO is transmitted to the MR' end of the reset watchdog chip U1 through the single-pole double-throw switch U3, the MR signal is low, the CPU _ RST signal is low, and the CPU is restarted.
(2) After 70mS, the level of a 2-pin NO end of the single-pole double-throw switch U4 is reduced to be below 2.4V, at the moment, a KEY signal is not pulled up strongly, only weak pull-down is performed, the time delay IC chip U2 starts to work, the output of the LED1 end is low, the single-pole double-throw switch U3 is turned off, an MR signal is pulled up to be high through a resistor R1, a CPU _ RST signal is changed to be high, the period lasts for 60 seconds, the CPU is restarted, and the CPU enters the power-on period again.
Therefore, when the CPU is completely halted (the progress of the CPU watchdog is hung up), the pure hardware watchdog circuit of the scheme still can start the CPU by the hardware watchdog circuit. In addition, by adjusting the relevant parameters of the delay IC chip U2, the delay time of the hardware watchdog circuit can be set arbitrarily, and different starting times required by different types of CPUs can be met.
The advantages and disadvantages of the existing watchdog and the pure hardware watchdog circuit of the scheme are compared as follows:
the pure hardware watchdog circuit of the scheme is simple to realize and low in price, and the cost of all BOMs is not more than 10 RMBs; the whole circuit is successfully verified by board punching, can be used under the conditions of-20 ℃ to +85 ℃, and the delay time of the circuit can be flexibly adjusted, so that the starting of hardware watchdog of most single boards can be met.
The above-mentioned specific implementation is the preferred embodiment of the present invention, can not be right the utility model discloses the limit, any other does not deviate from the technical scheme of the utility model and the change or other equivalent replacement modes of doing all contain within the scope of protection of the utility model.
Claims (2)
1. A hardware-only watchdog circuit, comprising: the system comprises a reset watchdog unit, a first switch unit, a second switch unit and a delay unit;
the reset watchdog unit comprises a reset watchdog chip U1, a resistor R1, a resistor R2 and a capacitor C1; the manual reset input end of the reset watchdog chip U1 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a capacitor C1, the other end of the capacitor C1 is connected to the ground, the monitor output end of the reset watchdog chip U1 is connected with one end of a resistor R2, the other end of the resistor R2 is connected to a power supply, and the power supply end of the reset watchdog chip U1 is connected with the power supply; the reset output end of the reset watchdog chip U1 is connected with the reset end of the CPU, and the monitor input end of the reset watchdog chip U1 is connected with the dog feeding signal output end of the CPU;
the delay unit comprises a delay IC chip U2, a resistor R3, a resistor R4 and a capacitor C2; the reset end of the delay IC chip U2 is connected with one end of a resistor R4, and the other end of the resistor R4 is connected with a power supply; the KEY end of the delay IC chip U2 is connected with one end of the resistor R3, the other end of the resistor R3 is connected to the ground, the power supply end of the delay IC chip U2 is connected with one end of the power supply and one end of the capacitor C2, and the other end of the capacitor C2 and the VSS end of the delay IC chip U2 are connected to the ground;
the first switch unit comprises a single-pole double-throw switch U3, a resistor R5 and a capacitor C3; the serial port end of the single-pole double-throw switch U3 is connected with the reset manual input end of the reset watchdog chip U1, the NO end of the single-pole double-throw switch U3 is connected with the LED1 end of the delay IC chip U2 and one end of the resistor R5, the other end of the resistor R5 is connected with the power supply, the grounding end of the single-pole double-throw switch U3 is connected to the ground, the V + end of the single-pole double-throw switch U3 is connected with the power supply and one end of the capacitor C3, the other end of the capacitor C3 is connected to the ground, and the IN end of the single-pole double-throw switch U3 is connected with the monitor output end of the reset watchdog chip U1;
the second switch unit comprises a single-pole double-throw switch U4, a resistor R6, a resistor R7, a capacitor C5 and a capacitor C6; the serial port end of the single-pole double-throw switch U4 is connected with the KEY end of the delay IC chip U2, the NO end of the single-pole double-throw switch U4 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the monitor output end of the reset watchdog chip U1, the grounding end of the single-pole double-throw switch U4 is connected to the ground through the capacitor C5, the V + end of the single-pole double-throw switch U4 is connected with one end of the power supply and one end of the capacitor C6, the other end of the capacitor C6 is connected to the ground, and the IN end of the single-pole double-throw switch U4 is connected with the power supply through the resistor R7.
2. The pure hardware watchdog circuit of claim 1, wherein the reset watchdog chip U1 is of a model MAX706REPA, the delay IC chip U2 is of a model 6368-30E0, and the single pole double throw switch U3 and the single pole double throw switch U4 are of a model MAX 4586.
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| CN201920980704.8U CN210091159U (en) | 2019-06-26 | 2019-06-26 | Pure hardware watchdog circuit |
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| CN201920980704.8U CN210091159U (en) | 2019-06-26 | 2019-06-26 | Pure hardware watchdog circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113377186A (en) * | 2021-08-13 | 2021-09-10 | 深圳市有为信息技术发展有限公司 | Power management circuit, control method thereof, vehicle-mounted equipment and motor vehicle |
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- 2019-06-26 CN CN201920980704.8U patent/CN210091159U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113377186A (en) * | 2021-08-13 | 2021-09-10 | 深圳市有为信息技术发展有限公司 | Power management circuit, control method thereof, vehicle-mounted equipment and motor vehicle |
| CN113377186B (en) * | 2021-08-13 | 2021-11-19 | 深圳市有为信息技术发展有限公司 | Power management circuit, control method thereof, vehicle-mounted equipment and motor vehicle |
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