CN103389917B - A kind of method of repairing during SRAM type FPGA SEU runs - Google Patents

Abstract

Do you the invention discloses a kind of SRAM type FPGA? the method of repairing during SEU runs, belongs to the configuring technical field of SRAM type FPGA.The method comprises the steps: the first step, SRAM type FPGA is powered on after, use configuration management FPGA first to carry out a global configuration to SRAM type FPGA; Second step, configuration management FPGA read configuration bit stream file, detect this bit stream file and are handled as follows: when the write of the frame in bit stream file order FDRI being detected, frame number of words subsidiary in FDRI is replaced with logic and interconnect frame number of words; When content configuration data Block being detected? during RAM, then no operation command is used to replace Block? RAM; When register reset command GRESTORE being detected, then when using no operation command to replace GRESTORE; When I/O startup command STARTUP being detected, then no operation command is used to replace STARTUP; 3rd step, by after second step process bit stream file write SRAM type FPGA; 4th step, repetition second step and the 3rd step are until SRAM type FPGA quits work.Does is this method applicable to SRAM type FPGA? SEU repairs in running.

Description

A kind of method of repairing during SRAM type FPGA SEU runs

Technical field

The present invention relates to the configuring technical field of SRAM type FPGA, a kind of method of particularly repairing in SRAM type FPGASEU operation.

Background technology

Virtex-5 Series FPGA is the novel FPGA based on SRAM technique that Xilinx company releases, and its integrated level is high, and logic function is strong, is widely used in Modern Digital System design.The logic function configuration of Virtex-5FPGA is realized by the data of its SRAM type configuring area,

SRAM attribute determines configuring area data and can lose after a power failure, therefore must be kept in nonvolatile external memory by configuration data, reconfigure after FPGA powers on to it.

In aerospace applications, Energetic particle bombardment causes SRAM type FPGA configuring area single-particle inversion SEU may cause fpga logic mistake, must carry out repairing the normal operation that can ensure FPGA to the configuring area single-particle inversion of FPGA.Usually following several strategy is had at the single-particle inversion of the configuring area of traditional reply FPGA:

1), regular global reconfiguration

SEU is a kind of soft error, and it can not cause the permanent damages of hardware, and after FPGA reloads configuration data, the impact of SEU can be removed.The application not bery high to some reliability requirements, system has certain tolerance to a small amount of SEU, and regular FPGA global reconfiguration can eliminate again the accumulation of SEU, substantially can ensure that system is in normal operating conditions.Thus, the application general to reliability requirement, solving SEU effect by the global reconfiguration of FPGA is a kind of acceptable scheme.

2), urgent global reconfiguration

In the occasion that some is higher to reliability requirement, regular global reconfiguration becomes can not accept owing to cannot eliminate SEU impact fast.Urgent global reconfiguration system must possess corresponding SEU error-detecting and errorlevel judgment mechanism, determines to carry out global reconfiguration immediately or postpone global reconfiguration until current key has operated after generation SEU mistake.

Requiring in the application that FPGA is highly reliable, long-time continuous is run, regularly reshuffle strategy, promptly reshuffle strategy all become inapplicable because the normal operation of FPGA can be interrupted, how when not interrupting the operation of FPGA, the reparation carrying out SEU mistake will be the development trend of configuring technical of SRAM type FPGA.

Repair in the operation of SEU, traditional method adopts " retaking of a year or grade-compare-write-back " mode, wherein need to use a shielding file .msk and retaking of a year or grade file .rbb, actual process is: use retaking of a year or grade file .rbb and original configuration file .bit to compare, if the two difference, utilizes shielding file .msk to be write in FPGA by retaking of a year or grade file .rbb.This mode is except the logic of relative complex, and maximum shortcoming is that .msk with .rbb file all has the size identical with original configuration file .bit, and what cause storage space takies three times that reach original; And due to the retaking of a year or grade holding time of configuring area longer, do not reach the real-time of carrying out required for middle reparation.Therefore the mode of above " retaking of a year or grade-compare-write-back " impracticable.

Summary of the invention

In view of this, the invention provides during a kind of SRAM type FPGASEU runs the method for repairing, object is the global configuration that powers on realizing SRAM type FPGA, and repairs in running the SEU of configuring area, and takies less storage space, possesses real-time.

For achieving the above object, the method comprises the steps:

The first step, after SRAM type FPGA powers on, configuration management FPGA is used to carry out a global configuration to SRAM type FPGA;

Second step, configuration management FPGA read configuration bit stream file, detect this bit stream file and are handled as follows:

When the write of the frame in bit stream file order FDRI being detected, frame number of words subsidiary in FDRI is replaced with logic and interconnect frame number of words;

When content configuration data BlockRAM being detected, then no operation command is used to replace BlockRAM;

When register reset command GRESTORE being detected, then no operation command is used to replace GRESTORE;

When I/O startup command STARTUP being detected, then no operation command is used to replace STARTUP;

3rd step, by after second step process bit stream file write SRAM type FPGA;

4th step, repetition second step and the 3rd step are until SRAM type FPGA quits work.

Beneficial effect:

1, present invention employs the method for carrying out " washing " to SEU mistake to repair in the operation realizing SEU.The data write with a brush dipped in Chinese ink configuring area are still from original configuration bit stream file, its central principle is when writing data to configuration frame data entrance register FDRI, only write the logic data relevant with interconnection configuration, BlockRAM content-data is masked, so namely, achieve the washing of SEU, also can not destroy the data in user RAM.The order simultaneously interrupting FPGA operation also will mask, and as GRESTORE order, this and order interrupts the normal operation of FPGA.Therefore the method can be in operation and to repair the SEU mistake of FPGA.

2, because the method does not detect SEU mistake, but repeatedly write with a brush dipped in Chinese ink to configuring area into correct configuration data, SEU mistake " washing " is fallen.Compare " retaking of a year or grade-compare-write-back " mode of classic method, do not use shielding file .msk and retaking of a year or grade file .rbb, use original configuration bit stream file, therefore take less storage space; Simultaneously owing to eliminating the retaking of a year or grade time of configuring area, SEU also wants shorter from occurring to the time be repaired relative to classic method, possesses real-time;

Accompanying drawing explanation

Fig. 1 circuit connection diagram;

Fig. 2 bit stream file and SEU wash the transforming relationship of bit stream;

Fig. 3 SEU washing flow figure.

Embodiment

To develop simultaneously embodiment below in conjunction with accompanying drawing, describe the present invention.

The method of repairing during the SEU for SRAM type FPGA used in the present invention runs, wherein the method connects can complete based on traditional FPGA circuit, and its circuit connects as shown in Figure 1.

The SRAM type FPGA used in the present embodiment is Virtex-5 Series FPGA;

The configuration bit stream file of this Virtex-5FPGA is deposited in nonvolatile external memory, and in practical operation, normally used nonvolatile external memory is PROM;

The configuration of this Virtex-5FPGA is controlled by configuration management FPGA, and the configuration management FPGA used in the present embodiment is anti-fuse type, does not affect by SEU;

Wherein be connected by SlvaeSelectMAP interface between Virtex-5FPGA with configuration management FPGA.

The method specific works step of repairing during the SEU for SRAM type FPGA provided by the present invention runs as shown in Figure 3, comprises following concrete steps:

The first step, power on after, use configuration management FPGA to start to carry out a global configuration to SRAM type FPGA; Its former state, for read configuration bit stream file from nonvolatile external memory PROM, is flowed to SRAM type FPGA to carry out global configuration by global configuration method; After completing global configuration, the DONE signal of SRAM type FPGA is driven high, and mark SRAM type FPGA global configuration completes;

Second step, the first step global configuration success after configuration management FPGA enter washers' SEU operation mode.

In the present embodiment, configuration management FPGA mono-aspect needs to carry out global configuration to RAM type FPGA, namely realizes the first step; Need the process of configuration bit-stream document analysis and write RAM type FPGA to carry out SEU washing on the other hand, namely realizing second step.Therefore configuration management FPGA inside has the circuit the write direct setting of a road bit stream file in the present embodiment, and have a road bit stream document analysis circuit, concrete configuration management FPGA structure as shown in Figure 1 simultaneously.

Configuration management FPGA reads configuration bit stream file, via bit stream document analysis circuit, real-time process is done to bit stream file, when configuration management FPGA detects that the settling signal DONE of SRAM type FPGA is driven high, i.e. global configuration success, flows to SRAM type FPGA by the bit stream file after process in real time.APA600 restarts to read bit stream from XCF16P first address, and bit stream parser circuitry is resolved bit road, replaces and shielding processing partial order in bit stream and data, detects in bit stream after DESYNC order, and one time SEU has washed.

In this step, analyze the Structure composing of bit stream file, as shown in Figure 2, bit stream file comprise front and back command group, logic and interconnected configuration data and, the operation that FDRI includes frame number of words, register reset command GRESTORE and startup command START can have influence on SRAM type FPGA is ordered in the frame write wherein in command group.

Real-time process wherein in this step comprises:

If when the frame write order FDRI in bit stream file being detected, in FDRI with frame number of words contain the frame number of words summation of logic and interconnect frame number of words and content configuration data, during owing to washing in the present invention, that repeats to write with a brush dipped in Chinese ink should be only logic and interconnected configuration data, do not need to comprise content configuration data, so frame number of words subsidiary in this order is replaced with logic and interconnect frame number of words herein;

If content configuration data BlockRAM detected, then use no operation command to replace BlockRAM, because in SRAM type FPGA, BlockRAM describes user data, does not therefore need washing.Make BlockRAM content initial value be written into SRAM type FPGA so use no operation command to replace BlockRAM, then the user data in SRAM type FPGA is preserved, and only configuring area SEU is washed;

If register reset command GRESTORE order detected, then use no operation command to replace GRESTORE order, the register avoided in SRAM type FPGA resets the SRAM type FPGA interruption caused;

If startup command START order detected, then no operation command is used to replace START order.Because START order can start the flow process of a series of FPGA startup, and some of them flow process can make I/O be in high-impedance state within a period of time, thus destroy the normal operation of I/O, therefore START order is not write with a brush dipped in Chinese ink as SRAM type FPGA by this method, thus avoids starting the SRAM type FPGA interruption brought;

Bit stream file after the acquisition process of this step is designated as SEU and washs bit stream.

3rd step, SEU washed bit stream write SRAM type FPGA;

4th step, repetition second step and the 3rd step are until FPGA quits work.Namely, after a SEU has washed, SEU washing next time starts immediately, till washing work should be continued until that FPGA quits work.

As can be seen from above-mentioned flow process, except having done except replacement and shielding processing to partial order in bit stream and data, the process of washing SEU has been consistent with the process of the global configuration that powers on.

The present invention also can use timer, washers' operation mode of SEU by timer is specified after timing, after having washed each time, washs by timer is specified after timing next time.Equally also can use peripheral control unit, send SEU wash instruction to configuration management FPGA by peripheral control unit, configuration management FPGA receives the washers' operation mode starting SEU after SEU washs instruction.In the implementation process of reality, can select flexibly according to the demand of application scenario.

In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (1)

1. a method of repairing in SRAM type FPGA single particle upset SEU operation, it is characterized in that, the method comprises the steps:

The first step, after SRAM type FPGA powers on, configuration management FPGA is used to carry out a global configuration to SRAM type FPGA; Its former state, for read configuration bit stream file from nonvolatile external memory PROM, is flowed to SRAM type FPGA to carry out global configuration by global configuration method;

Second step, configuration management FPGA read configuration bit stream file, detect this bit stream file and are handled as follows:

When the write of the frame in bit stream file order FDRI order being detected, frame number of words subsidiary in FDRI is replaced with logic and interconnect frame number of words;

When content configuration data BlockRAM being detected, then no operation command is used to replace BlockRAM;

When the GRESTORE order of register reset command being detected, then no operation command is used to replace GRESTORE;

When startup command START order being detected, then no operation command is used to replace START;

3rd step, by after second step process bit stream file write SRAM type FPGA;

4th step, repetition second step and the 3rd step are until SRAM type FPGA quits work.