CN205193785U - Self -check and recovery device of duplication redundancy assembly line - Google Patents
Self -check and recovery device of duplication redundancy assembly line Download PDFInfo
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- CN205193785U CN205193785U CN201520998848.8U CN201520998848U CN205193785U CN 205193785 U CN205193785 U CN 205193785U CN 201520998848 U CN201520998848 U CN 201520998848U CN 205193785 U CN205193785 U CN 205193785U
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Abstract
The utility model provides a self -check and recovery device of duplication redundancy assembly line which characterized in that: self -check and recovery device of duplication redundancy assembly line includes interstage register A, interstage register B, checker A, checker B, function logic A, function logic B, encoder A, encoder B, assembly line recovery module, the self -check of two redundant assembly linies and recovery device adoption self -check are carried out the check -up to the interstage register of two assembly linies and are used for orienting the failure flow waterline, and the error message that provides according to the self -check is launched the assembly line and is resumeed mechanism, with the method of the wrong assembly line of executive mode replacement of correct assembly line, carry on fault -tolerantly to the trouble that single event effect causes.
Description
Technical field
The utility model relates to a kind of self checking and recovery device of microprocessor pipeline, particularly relates to self checking and the recovery device of streamline in a kind of SPARCV8 processor.
Background technology
Single-particle inversion (SingleEventUpset, SEU) be under the applied environment of space, because single-particle incidence causes the event of storage unit generation Data flipping mistake in integrated circuit, be that under space environment, electronic system breaks down and one of the major incentive of operation irregularity.Along with the fast development of semiconductor process techniques, the size of chip is in continuous reduction, processor working frequency improves constantly, the reduction of node operating voltage makes single-particle inversion phenomenon more and more serious, research is pointed out, in nanoscale chip, long numeric data upset (MBU) probability that single-particle inversion causes is also in rapid raising.Maximum 8 random data upset mistake can be caused, larger harm is produced to the electronic system of space application.In microprocessor and electronic system, take reinforcement measure to carry out to SEU fault the technological means that fault-tolerant design become important.
As the important component part of Modern microprocessor, the instruction stream that streamline mainly completes program code performs, and execution result is write data storage and register file.If the misdata that single-particle bombarding stream waterline causes grade inter-register to occur to overturn or single-event transients (SET) causes is latched, streamline execution result will be caused incorrect, when not having pipeline unit to carry out fault-tolerant reinforcing, the execution result of mistake will be diffused into the instruction stream of data storage and register file or execution error, and then cause much more uncontrollable mistakes to produce, therefore, for the highly reliable microprocessor of space application, the fault-tolerant design carrying out pipelined units has great importance.
The existing reinforcement technique to space microprocessor has following three kinds of schemes: adopt time-based fault-tolerance approach, can effectively solve MBU problem, but processor performance reduces greatly; Adopt the fault-tolerance approach based on coding, can only the correctness of effective verification computation part, and different coded systems can not all process for different single-particle faults, and fault-tolerant ability is limited; Adopt the scheme based on hardware redundancy, register stage triplication redundancy cannot tackle MBU fault, and pipeline stages triplication redundancy can orient failure flow waterline, but the expenses such as hardware resource power consumption are larger, pipeline stages duplication redundancy can tackle MBU fault, but cannot locate, and does not have the ability of shielding fault, each streamline rollback that all carries out significantly can increase track performance expense, especially bulk treatment speed can be caused obviously to reduce when single-particle fault is day by day common.
The two redundancy streamline (Self-RecoveryDualPipeline) of selfreparing, be called for short SRDP, under the prerequisite considering Time and place expense, based on the thought of hardware redundancy, traditional pipeline stages dual modular redundancy is improved, comparer pipeline unit is set between two streamlines and carries out fault detect, utilize self checking module to carry out verification to level inter-register and orient failure flow waterline, recover according to comparative result and self checking error message pipeline, the SEU that single particle effect is caused is realized with low area overhead, SET and MBU fault detects, location and recovery.When single-particle fault is more and more serious, break down for avoiding pipelined units and can only carry out the situation of rollback operation, be badly in need of exploring the method positioned failure flow waterline, self checking is carried out by pipeline level inter-register, and the executing state of the correct streamline of error message provided according to self checking replaces error pipeline, thus reduce the performance cost of streamline, improve the overall performance of processor.
Summary of the invention
The purpose of this utility model is the self checking and the recovery device that design a kind of duplication redundancy streamline, self checking can be carried out to pipeline stages inter-register in dual modular redundancy, enable streamline recovery according to the information that self checking provides, thus carry out fault-tolerant to single-particle fault.
For achieving the above object, the technical scheme that the utility model adopts is:
The self checking of duplication redundancy streamline and a recovery device, is characterized in that: the self checking of described duplication redundancy streamline and recovery device comprise a grade inter-register A, level inter-register B, checker A, checker B, function logic A, function logic B, scrambler A, scrambler B and streamline and recover module; The information that described level inter-register A provides for depositing previous pipelining-stage function logic, and the check information after the encoded device coding of this information; The information that described level inter-register B provides for depositing previous pipelining-stage function logic, and the check information after the encoded device coding of this information; Described checker A verifies the information of depositing in level inter-register A according to the check information in level inter-register A, and generation error information is sent into streamline and recovered module; Described checker B verifies the information of depositing in level inter-register B according to the check information in level inter-register B, and generation error information is sent into streamline and recovered module; Described function logic A is the function logic executive agent of pipelining-stage, and after the function according to the information and executing pipelining-stage in level inter-register A, the information of level inter-register deposited by the needs being given to next pipelining-stage, and is encoded by this information feeding scrambler A; Described function logic B is the function logic executive agent of pipelining-stage, and after the function according to the information and executing pipelining-stage in level inter-register B, the information of level inter-register deposited by the needs being given to next pipelining-stage, and is encoded by this information feeding scrambler B; Described scrambler A encodes to the information that function logic A provides according to the coded system selected, and generates check information, sends in level inter-register and deposits; Described scrambler B encodes to the information that function logic B provides according to the coded system selected, and generates check information, sends in level inter-register and deposits; Described streamline recovers the error message that module provides according to checker A and checker B, determines the streamline occurring mistake, uses the executing state of correct streamline to recover error pipeline.
The self checking of a kind of embedded microprocessor duplication redundancy streamline that the utility model realizes and recovery device, failure flow waterline is oriented by carrying out self checking to level inter-register in embedded microprocessor, enable streamline to recover, SEU and the MBU fault that single-particle bombarding stream pipeline units causes can be shielded, thus the reliability that microprocessor applies under the rugged surroundings such as space can be improved.
Accompanying drawing explanation
Fig. 1 is according to the self checking of the two redundancy streamline of the utility model and recovers structural drawing;
Fig. 2 is the structural drawing of the two redundancy streamline of selfreparing;
Fig. 3 is the structural drawing that streamline recovers;
Fig. 4 is the sequential chart that streamline recovers.
Embodiment
The present embodiment is described embodiment of the present utility model in conjunction with a kind of embedded microprocessor LEON2 of SPARCV8 architecture.The embedded microprocessor LEON2 of this SPARCV8 architecture adopts the RISC framework of 32, its pipelined units to be classical five-stage pipeline, and each pipelining-stage of streamline and instruction buffer memory, data buffer storage and register file can carry out data interaction.
The pipelined units of LEON2 processor comprises fetching (IF), decoding (ID), performs (EX), memory access (ME), writes back (WR) five combinatorial logic unit, and five groups of level inter-registers IF, IF/ID, ID/EX, EX/ME, ME/WR arranging between each pipelining-stage.The combinational logic part of single-particle bombarding stream waterline, producing burr may be there is SET fault by inter-stage registers latch, can directly cause register to occur SEU or MBU fault during bombardment level inter-register.The key message that combinational logic produces is deposited and in inter-stage transmission by level inter-register, deposit the execution result that error message level inter-register can lead to errors, and error result can be written into data-carrier store or register file in ME or WR section, the execution of the instruction stream that simultaneously may make the mistake.
In order to effectively tackle the single-particle soft error that radiation causes, especially MBU problem, consider each scheme Time and place expense, based on the thought of hardware redundancy, propose a kind of SEU realizing that with low area overhead single particle effect is caused, SET and MBU fault detects, location and recovery streamline ruggedized construction, the two redundancy streamline (Self-RecoveryDualPipeline) of selfreparing, be called for short SRDP, traditional pipeline stages dual modular redundancy is improved, comparer pipeline unit is set between two streamlines and carries out fault detect, utilize self checking to carry out verification to level inter-register and orient failure flow waterline, recover according to comparative result and self checking error message pipeline.The utility model is directed to how to carry out self checking to two pipeline stages inter-registers IF, IF/ID, ID/EX, EX/ME, ME/WR, once pipelined units is subject to single-particle bombardment and causes streamline to break down, if the streamline broken down is oriented in the error message that can provide according to self checking, streamline Restoration Mechanism is enabled at current period, the executing state of correct streamline is copied to error pipeline, re-executes current operation in the next clock period.
By analyzing LEON2 processor pipeline unit, the level inter-register details of streamline are as shown in table 1, find that signal number and the signal figure place of the level inter-register that streamline is at different levels are all different, need to carry out dividing into groups and and bit manipulation according to the self checking bit wide arranged.Meanwhile, the utility model can select the code encoding/decoding mode of self checking according to real needs, such as, if just need to detect odd number or even bit mistake, then self checking can be set to parity checking; If need detection two bit-errors and correct a bit-errors, then can select self checking to be set to EDAC verification; If need to entangle inspection multi-bit error, then self checking can be selected to be set to the verification modes such as BCH.
Table 1 pipeline stages inter-register
Based on above-mentioned ultimate principle and setting, a kind of embodiment of the self checking of duplication redundancy streamline of the present utility model and recovery device is as follows:
In the embedded microprocessor of SPARCV8 architecture, be arranged to as shown in Figure 1 by each flowing water section in streamline, main level inter-register A, level inter-register B, checker A, checker B, function logic A, function logic B, scrambler A, scrambler B, streamline recover module.
The information that the pipelining-stage function logic depositing two streamlines respectively in level inter-register A and level inter-register B provides and the rear check information of this information encoded device coding.
Checker A verifies the information of depositing in level inter-register A according to the check information in level inter-register A, and generation error information is sent into streamline and recovered module.
Checker B verifies the information of depositing in level inter-register B according to the check information in level inter-register B, and generation error information is sent into streamline and recovered module.
Function logic A is the function logic executive agent of pipelining-stage, after the function according to the information and executing pipelining-stage in level inter-register A, provides the information needing to deposit level inter-register, and is encoded by this information feeding scrambler A.
Function logic B is the function logic executive agent of pipelining-stage, after the function according to the information and executing pipelining-stage in level inter-register B, provides the information needing to deposit level inter-register, and is encoded by this information feeding scrambler B.
Scrambler A encodes to the information that function logic A provides according to the coded system selected, and generates check information, sends in level inter-register and deposits.
Scrambler B encodes to the information that function logic B provides according to the coded system selected, and generates check information, sends in level inter-register and deposits.
Streamline recovers the error message that module provides according to checker A and checker B, after streamline mistake appears in location, is recovered by the state of replacing error pipeline pipeline unit by the executing state of correct streamline.
The self checking of described duplication redundancy streamline and recovery device adopt the streamline occurred due to single particle effect causing trouble in following steps and method pipeline level dual modular redundancy position and recover:
(1) when instruction performs, pipelined units, to Instruction Register output order address and control information, takes out instruction from instruction buffer, is distributed to two pipeline parallel methods and performs; In each clock period, article two, after the function logic of five flowing water sections of streamline operates from the information in the level inter-register of a upper flowing water section respectively, provide the information needing to be deposited with next flowing water section level inter-register, the information that five flowing water section function logics provide can be deposited in corresponding flowing water section level inter-register when next clock period rising edge arrives;
(2) in each pipelining-stage of two streamlines, divide into groups by the encoding and decoding bit wide of setting to the information bit of level inter-register, insufficient section ' 0 ' polishing, for each grouping arranges a scrambler and a checker; Scrambler is encoded to the grouping information position that function logic exports, and output verification code writes a grade inter-register together with grouping information, verifies for next pipelining-stage;
(3) while the function logic of pipelining-stage carries out function computing, checker A, checker B press coding rule, verify by grouping the input information of level inter-register and check code, if checker A, checker B verification is all correct, pipelining-stage normally runs; If all made mistakes, arrange streamline error flag, streamline down continues flowing, carries out abnormality processing when streamline is flowed out in instruction; If wherein only have a verification to make mistakes, start streamline recovery module and carry out streamline recovery;
(4) if one in checker A or checker B occurs check errors, explanation has a streamline to occur mistake, streamline recovers module and all inserts a latent period to two streamlines, copy in the streamline of makeing mistakes by the inter-stage content of registers of the correct streamline of verification, next cycle restarts the execution of streamline.
The structural drawing that streamline recovers as shown in Figure 3, after self checking is completed to the inter-stage register check of two streamlines, streamline recovery module is oriented assembly line A according to the error message that self checking provides and is broken down, then the signal replacing assembly line A is set to ' 1 ', if orient streamline B to break down, then the signal replacing streamline B is set to ' 1 ', and replacement signal is sent into two streamlines respectively, if the signal replacing assembly line A is effective, then the executing state of assembly line A is replaced to the executing state of streamline B, if it is effective to replace streamline B signal, then the executing state of streamline B is replaced to the executing state of assembly line A, memory access section in streamline and the section of writing back instruction are enablely set to disarmed state to writing of data buffer storage and register file simultaneously, stop execution result write data buffer storage and the register file of mistake, current operation is re-executed at following clock cycle, consuming a clock period realizes fault masking.The sequential chart that streamline recovers as shown in Figure 4, in N number of clock period, the section of the writing back instruction of streamline is broken down, self checking is carried out to its section of writing back level inter-register, orient failure flow waterline, streamline recovers module and uses the executing state of correct streamline to replace error pipeline, re-executes the operation of N number of clock period N+1 clock period, and streamline continues to perform downwards.
The self checking of embedded microprocessor duplication redundancy streamline that the utility model realizes and the device of recovery, self checking pipeline level inter-register is utilized to verify, carry out information redundancy, the streamline broken down is positioned, streamline recovery is enabled according to the check information that self checking provides, solve embedded microprocessor pipeline stages duplication redundancy causes occurring SEU, MBU fault streamline Fault-Tolerant Problems to single-particle bombardment, the reliability that embedded microprocessor works under space environment can be improved.
In the scope not departing from the utility model spirit, the utility model can have various deformation, as: the bit wide of encoding and decoding, the selection etc. of self checking decoding method, all can change in different enforcement.These distortion are also contained within the utility model scope required for protection.
Claims (1)
1. the self checking of duplication redundancy streamline and a recovery device, is characterized in that: the self checking of described duplication redundancy streamline and recovery device comprise a grade inter-register A, level inter-register B, checker A, checker B, function logic A, function logic B, scrambler A, scrambler B and streamline and recover module; The information that described level inter-register A provides for depositing previous pipelining-stage function logic, and the check information after the encoded device coding of this information; The information that described level inter-register B provides for depositing previous pipelining-stage function logic, and the check information after the encoded device coding of this information; Described checker A verifies the information of depositing in level inter-register A according to the check information in level inter-register A, and generation error information is sent into streamline and recovered module; Described checker B verifies the information of depositing in level inter-register B according to the check information in level inter-register B, and generation error information is sent into streamline and recovered module; Described function logic A is the function logic executive agent of pipelining-stage, and after the function according to the information and executing pipelining-stage in level inter-register A, the information of level inter-register deposited by the needs being given to next pipelining-stage, and is encoded by this information feeding scrambler A; Described function logic B is the function logic executive agent of pipelining-stage, and after the function according to the information and executing pipelining-stage in level inter-register B, the information of level inter-register deposited by the needs being given to next pipelining-stage, and is encoded by this information feeding scrambler B; Described scrambler A encodes to the information that function logic A provides according to the coded system selected, and generates check information, sends in level inter-register and deposits; Described scrambler B encodes to the information that function logic B provides according to the coded system selected, and generates check information, sends in level inter-register and deposits; Described streamline recovers the error message that module provides according to checker A and checker B, determines the streamline occurring mistake, uses the executing state of correct streamline to recover error pipeline.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320575A (en) * | 2015-10-27 | 2016-02-10 | 首都师范大学 | Self-checking and recovering device and method for dual-modular redundancy assembly lines |
| CN116974813A (en) * | 2023-09-25 | 2023-10-31 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
| CN116974813B (en) * | 2023-09-25 | 2024-04-19 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
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- 2015-12-07 CN CN201520998848.8U patent/CN205193785U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320575A (en) * | 2015-10-27 | 2016-02-10 | 首都师范大学 | Self-checking and recovering device and method for dual-modular redundancy assembly lines |
| CN105320575B (en) * | 2015-10-27 | 2018-03-23 | 首都师范大学 | A kind of self checking of duplication redundancy streamline and recovery device and method |
| CN116974813A (en) * | 2023-09-25 | 2023-10-31 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
| CN116974813B (en) * | 2023-09-25 | 2024-04-19 | 南方电网数字电网研究院有限公司 | Register data management method and device, register module and computer equipment |
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