CN101551764B - An anti-SEE system and method based on synchronizing redundant threads and coding technique - Google Patents
An anti-SEE system and method based on synchronizing redundant threads and coding technique Download PDFInfo
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Abstract
Through the research and improvement of error-correcting codes and error-detecting codes, the anti-SEE system and method based on synchronizing redundant threads and coding technique enables this coding technique to quickly detect the SEU (single event upset) occurring in register file and meanwhile design the both-threaded mechanism of the processor into a redundant both-threaded mechanism. When the register file of a thread is found with SEU, the register data with upset error will be corrected through replacing this register file with the register file of the other redundant thread; throughthe comparison mechanism of synchronous execution results in the layer of redundant both-threaded instructions, the pipelined circuit is judged whether there is SET (single-event transient) error. If such error occurs, it will be quickly eliminated from the pipeline through the designed redundant thread pipeline restart mechanism. This method satisfactorily solves the two frequent and difficult p roblems: SMU of register file in processor and pipeline SET.
Description
Technical field
The present invention relates to system and its implementation of a kind of anti-single particle effect.
Background technology
In recent years, along with technological development, device size is more and more littler, operating voltage is more and more lower, single particle effect become more and more sternly come serious more.Especially along with the increase of clock frequency, the linear increase of the error rate that SET caused, even surpass SEU, thus limited the increase of processor system clock frequency.Studies show that the pulsewidth order of magnitude of SET is 350ps～1.3ns, surpass 1ns so work as pulsewidth, clock frequency just is limited in below the 1GHz, otherwise the SET effect may take place.On the other hand, under the sub-micro technology, the probability of memory circuit generation multidigit upset increases, and the design that processor carries out anti-single particle effect seems very important.
Carry out radioresistance research at processor, the processor internal circuit can be divided into memory circuit (sequential circuit) and combinational circuit on type, wherein memory circuit mainly is register file and cache, and processor bosom register, the main streamline that concentrates on of combinational circuit is because computing circuit and critical data passage mainly concentrate on the pipeline unit.Therefore, at the radioresistance research of processor, need focus on the memory circuit and flow line circuit of processor.
At present, carry out radioresistance research from the system logic level, mainly adopt following method at memory circuit anti-single particle overturn in the processor: to the Cache error correction and detection, the general parity check code that uses detects mistake, correct the single-particle inversion mistake by forcing location contents that cache visit disappearance is read in the external memory storage correspondence to refill then, because parity check code is simple, can big influence not arranged to the cache accessing time sequence, therefore, just can reasonable solution cache single-particle inversion mistake by this method.For the design of processor bosom register radioresistance, generally use the triplication redundancy voting formula, solve.To the design of register file radioresistance, use the Hamming code that entangles 1 inspection 2.To the anti-single particle transition of combinational circuit in the processor, mainly adopt arithmetic code method (as residue code and AN sign indicating number) and redundancy approach.This method mainly is fit to the fairly simple algorithm of the less demanding algorithm of sequential, and dissimilar algorithms (as multiplication, addition) need different arithmetic codes.Redundancy approach mainly is that whole combinational circuit is adopted bimodulus or triplication redundancy, detects by the result being compared voting whether the single-event transients mistake has taken place.
Along with processor and operating frequency of integrated circuit and integrated level significantly improve, and it is more and more responsive in the practical application to power consumption and area, employed error correction and detection coding method in the above-mentioned designing technique, if directly be attached in the register file access mechanism to frequency sensitive, can become the restraining factors of entire circuit frequency.Directly then cause IC power consumption and area significantly to increase with two moulds or multimode circuit redundancy approach.Therefore, in order to overcome the shortcoming of classic method and technology, utilize synchronizing multiple threads technology SMT (Simultaneous Multithreading) to constitute two redundant threads in recent years and come anti-single particle effect to become a kind of Study on new method focus.Performance potential advantages and the characteristics of redundant granulometric facies to less (only carry out relevant resource with inner streamline and just need redundancy) that this method mainly utilizes multithreading to have reduce the negative effect of anti-single particle effect to performance and area.In the redundant threads, two threads have the execution pipeline of oneself separately, and one is referred to as leading thread (Leading Thread), and one is referred to as track thread (TrailingThread), the two carries out same program code redundantly, complete back comparative result.
But this method has following shortcoming:
The one, the single-event transients SET mistake of inspection combinational circuit can only be entangled, and single-particle inversion SEU mistake in the inspection processor can't be entangled; The 2nd, two threads of this method need whole streamline redundancies, need and write back level in storage level and leading thread execution result is set preserves buffer zone, so that the result of track thread and leading thread result comparison; The 3rd, be turned back to the reference position of performed program segment when preserving two thread error correction, a bigger preservation need be set turn round on-the-spot buffer zone.The 4th, produce free time between leading thread and the track thread, and this free time may have influence on whole performance, as the patent No. is CN200480039553, use speculative memory by name support is managed the external memory storage that is used for the fault detect of redundant threads system and is upgraded, described synchronous and redundant threads architecture, this method need be considered the upper limit of free time when design.
Therefore, this Fully-pipelined redundant fashion just needs a plurality of buffer zones, so just increased the hardware spending of system greatly, the more important thing is, this memory circuit of buffer zone is very responsive to single-particle inversion, can make when having solved combinational circuit single-event transients SET problem, bring the hidden danger of single-particle inversion.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of anti-single particle effect system and method based on synchronizing redundant threads and coding techniques is provided, this system and method is by combining synchronizing redundant threads with coding techniques, adopt partial redundance, with less relatively cost, detect and correct processor register file single-particle inversion SEU, combinational circuit single-event transients SET, improve reliability of processor.
The technical solution of system of the present invention is: based on the anti-single particle effect system of synchronizing redundant threads and coding techniques, comprise and get finger print piece, thread gating module, decoding module I, execution module I, decoding module II, execution module II, error detection circuit I, error detection circuit II, register file I, register file II, comparison module, memory module and system controller;
Get the finger print piece, according to system controller from the CACHE that hits or from external memory storage reading command, and with the Instructions Cache that reads;
Thread gating module reads the instruction of getting the finger print block cache, launches after this instruction is write the redundant threads instruction buffer; Simultaneously with decoding module I, decoding module II gating;
Decoding module I, decoding module II decipher the instruction of thread gating module emission respectively, and the result after will deciphering sends to execution module I, execution module II respectively;
Execution module I, execution module II, according to the result after the decoding that receives, reading of data from register file I, register file II respectively, and the data that read are sent to error detection circuit I, error detection circuit II; According to the control of system controller, carry out corresponding operating;
Error detection circuit I, error detection circuit II detect the data that read whether single-particle inversion take place, and the error detection result is sent to system controller;
System controller, according to the error detection result, control and executive module I, execution module II utilize described reading of data to carry out present instruction, perhaps control register heap I, register file II replace the data that single-particle inversion takes place with correct data, and the data after will replacing send to execution module I, execution module II respectively; Perhaps control and executive module I, execution module II quit work, and control is simultaneously got the finger print piece and read this instruction again; According to the current state of comparison module notice, control is got the finger print piece and is read present instruction again;
Comparison module compares the result after execution module I, the execution module II execution command, if unanimity as a result then sends to this result the memory module storage; Otherwise, with current state reporting system controller.
Also comprise writing back module, write back module the result of memory module storage is write back register file I, register file II.
The scheme of the inventive method is: based on the anti-single particle effect method of synchronizing redundant threads and coding techniques, this method is carried out synchronously by two thread branch Pyatyi flowing water, the shared resource of two threads refers to level, thread gating stage, storage level for getting, and redundant resource is decode stage and execution level; Method step is as follows:
(1) get refer to level from the CACHE that hits or from external memory storage reading command, and with the Instructions Cache that reads;
(2) instruction of buffer memory in the thread gating stage read step (1) will be launched behind this Instructions Cache; Simultaneously with described redundant resource gating;
(3) instruction that sends of the decode stage receiving thread gating stage in the redundant resource, and this instruction deciphered, send to execution level after the decoding;
(4) redundant execution level is according to described instruction, reading of data from the register file of place thread separately respectively, read in the process, judge whether the data that read single-particle inversion takes place, if single-particle inversion does not all take place in the data that redundant execution level reads from register file, then redundant execution level utilizes the data that read to carry out this instruction respectively, changes step (5); If single-particle inversion all takes place in the data that redundant execution level reads from register file, stop two thread pipeline, begin to re-execute from step (1); Otherwise, stopping two thread pipeline earlier, the data of the data replacement generation single-particle inversion of single-particle inversion will not take place in redundant execution level, restart described streamline, and utilize the data that read to carry out this instruction respectively, change step (5);
(5) storage level compares redundant execution level execution result, if unanimity is as a result then stored this result; Otherwise, show the single-particle transient state takes place, stop streamline and carry out, begin to re-execute from step (1).
The shared resource of described two threads also comprises and writes back level, writes back level the execution result of storage in the step (5) is write back in the described register file.
The present invention compared with prior art beneficial effect is:
1) the inventive method has designed synchronizing multiple threads (SMT) technology and Error Checking and Correcting technology (ErrorDetection And Correction), realizes the architecture of mechanism of the error correction and detection of soft error jointly.The error correction and detection of register file circuit error correction and detection and combinational circuit streamline is unified in realization and control in the thread, make error correction and detection realization mechanism and each parts of processor execution and control relatively independent, parallel control, the error propagation control of processor self streamline and error correction and detection logic in the classic method, the complex process of sequential control have been avoided, make entire process device anti-single particle overturn wrong structure modularization, control is simple.
2) the two redundant threads of the inventive method design have only partial function circuit redundancy, and most of functional circuit can be shared, thereby it is littler than the hardware spending of two redundant threads methods of redundant dual core processor radioresistance method for designing and fully redundance, utilize the multithreading inherent characteristic simultaneously, register file reasonable in design and CACHE error correction and detection encoding mechanism have reduced the hardware spending that the memory circuit error correction and detection expends greatly.
3) the inventive method adopts the error detection of quick error detection coding method by register file error correction and detection circuit, having set up data exchange channel between two register files of two threads is used for register data and replace realizes error correction, correct the single-event transients mistake that streamline takes place by restarting pipelining technique, error correction is real-time, avoids performance loss effectively.
4) the inventive method, the corresponding memory word of two registers in redundant two-wire journey has only under the situation of a memory word generation single-particle inversion, how many memory words that no matter makes a mistake has overturn, all can correct a mistake by the corresponding stored device data of replacing correct storer heap, its correction rate reaches 100%.For two redundant threads streamlines, if 1 streamline generation single-event transients mistake is wherein then corrected fully by restarting pipelining technique.Therefore, radiation-induced upset of this method error correction and detection and transition mistake have very high coverage rate.
5) this method is the radiation hardening method that realizes on architecture logical design layer, do not rely on concrete processing line and cell library, compare with the radioresistance method that adopts in domain level, device level and circuit stages, design cost and production cost reduce greatly, have very strong practical value.
Description of drawings
Fig. 1 is a system schematic of the present invention;
Fig. 2 is system controller workflow diagram in the system of the present invention;
Fig. 3 is an error detection circuit synoptic diagram of the present invention;
Fig. 4 is the inventive method process flow diagram.
Embodiment
As shown in Figure 1, system of the present invention comprises gets finger print piece, thread gating module, decoding module I, execution module I, decoding module II, execution module II, error detection circuit I, error detection circuit II, register file I (Regfile I), register file II (Regfile II), comparison module, memory module and system controller;
Get the finger print piece, according to system controller from the CACHE that hits or from external memory storage reading command A, and the instruction A buffer memory that will read; Described instruction of reading from external memory storage need be handled through the EDAC error correcting and detecting; The instruction of reading from the CACHE that hits is handled through parity checking; These two kinds of disposal routes are to well known to a person skilled in the art technology, here no longer describe in detail, handling about the EDAC error correcting and detecting can be referring to Chinese patent 200510041617.9, title " primary particle inversion resistant storer error correction and detection of space computer and automatic write back method ", parity checking is handled can be referring to Northwestern Polytechnical University's PhD dissertation, Xin Mingrui, the relevant introduction in " the fault-tolerant risc processor architectural study that use the space-oriented ".Thread gating module reads the instruction A that gets the finger print block cache, launches after should instructing A to write the redundant threads instruction buffer; Simultaneously with decoding module I and decoding module II gating; Decoding module I deciphers the instruction A of thread gating module emission, and the result after will deciphering sends to execution module I; Decoding module II deciphers the instruction A of thread gating module emission, and the result after will deciphering sends to execution module II; Execution module I, according to the result after the decoding that receives, reading of data from register file I, and the data that read are sent to error detection circuit I; Execution module II, according to the result after the decoding that receives, reading of data from register file II, and the data that read are sent to error detection circuit II; Execution module I and execution module II carry out corresponding operating according to the control of system controller; Error detection circuit I and error detection circuit II detect the data that read respectively whether single-particle inversion take place, and the error detection result is sent to system controller; System controller, according to the error detection result, control and executive module I and execution module II utilize described reading of data to carry out present instruction A, perhaps control register heap I and register file II replace the data that single-particle inversion takes place with correct data, and the data after will replacing send to execution module I and execution module II respectively; Perhaps control and executive module I and execution module II quit work, and control is simultaneously got the finger print piece and read this instruction A again; According to the current state of comparison module notice, control is got the finger print piece and is read present instruction A again; Comparison module compares the result after execution module I and the execution module II execution command, if unanimity as a result then sends to this result the memory module storage; Otherwise, with current state reporting system controller.
For the result in the later use native system, can also be provided with in the system and write back module, write back module the result of memory module storage is write back register file I and register file II.
As shown in Figure 2, the system controller course of work is as follows in the native system:
The first step judges whether to receive the error detection result of error detection circuit I, error detection circuit II transmission, if receive this error detection result, then changeed for second step, otherwise, judge the current state information that is subjected to not receive the comparison module transmission, if receive current state information, then control is got the finger print piece and is read this instruction A again; If do not receive current state information, then continue to wait for;
In second step, if the error detection result shows that single-particle inversion does not all take place the data that execution module I and execution module II read from register file I, register file II, then control and executive module I and execution module II utilize the data that read to carry out present instruction A;
If the error detection result shows that single-particle inversion all takes place the data that execution module I and execution module II read from register file I, register file II, then control and executive module I and execution module II quit work, and control is simultaneously got the finger print piece and read present instruction A again;
If the error detection result shows the data generation single-particle inversion that has only an execution module to read from its register file, the data of now establishing among the Regfile1 make a mistake, the current instruction that will carry out is instruction A, control is stopped execution module I to system controller and execution module II quits work, and the data exchange channel L of gating Regfile2 and Regfile1, correct data corresponding among the Regfile2 is replaced misdata corresponding among the Regfile1 through the data channel between two register files, like this, just realized the single-particle inversion error correcting among the Regfile1, restart execution module I and execution module II, utilize the data of replacing to carry out present instruction A by execution module I and execution module II.
The error detection process of above-mentioned error detection circuit I, error detection circuit II: at first the data that write are encoded, and generate corresponding check bit, these data and check bit are stored in the relevant register heap; When data were read, error detection circuit I, error detection circuit II decoded to the data of reading, and the check bit that generates when soon the check bit that generates is with coding compares, and when the two unanimity, proved that data are correct, otherwise, data generation single-particle inversion mistake is described.The implementation of above-mentioned coding, decoding is the XOR tree, specifically referring to Fig. 3.
As shown in Figure 4, anti-single particle effect method based on synchronizing redundant threads and coding techniques, this method is carried out synchronously by two thread branch Pyatyi flowing water, and the shared resource of two threads refers to level, thread gating stage, storage level for getting, and redundant resource is decode stage and execution level; Method step is as follows:
(1) get refer to level from the CACHE that hits or from external memory storage reading command, and with the Instructions Cache that reads; The instruction of reading from external memory storage need be handled through the EDAC error correcting and detecting; The instruction of reading from the CACHE that hits is handled through parity checking.
(2) instruction of buffer memory in the thread gating stage read step (1) will be launched behind this Instructions Cache; Simultaneously with described redundant resource gating;
(3) instruction that sends of the decode stage receiving thread gating stage in the redundant resource, and this instruction deciphered, send to execution level after the decoding;
(4) redundant execution level is according to described instruction, reading of data from the register file of place thread separately respectively, read in the process, judge whether the data that read single-particle inversion takes place, if single-particle inversion does not all take place in the data that redundant execution level reads from register file, then redundant execution level utilizes the data that read to carry out this instruction respectively, changes step (5); If single-particle inversion all takes place in the data that redundant execution level reads from register file, stop two thread pipeline, begin to re-execute from step (1); Otherwise, stopping two thread pipeline earlier, the data of the data replacement generation single-particle inversion of single-particle inversion will not take place in redundant execution level, restart described streamline, and utilize the data that read to carry out this instruction respectively, change step (5);
(5) storage level compares redundant execution level execution result, if unanimity is as a result then stored this result; Otherwise, show the single-particle transient state takes place, stop streamline and carry out, begin to re-execute from step (1).
The shared resource of described two threads also comprises and writes back level, writes back level the execution result of storage in the step (5) is write back in the described register file.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (6)
1. based on the anti-single particle effect system of synchronizing redundant threads and coding techniques, it is characterized in that: comprise and get finger print piece, thread gating module, decoding module I, execution module I, decoding module II, execution module II, error detection circuit I, error detection circuit II, register file I, register file II, comparison module, memory module and system controller;
Get the finger print piece, according to the control of system controller, from the CACHE that hits or from external memory storage reading command, and with the Instructions Cache that reads;
Thread gating module reads the instruction of getting the finger print block cache, launches after this instruction is write the redundant threads instruction buffer; Simultaneously with decoding module I, decoding module II gating;
Decoding module I, decoding module II decipher the instruction of thread gating module emission respectively, and the result after will deciphering sends to execution module I, execution module II respectively;
Execution module I, execution module II, according to the result after the decoding that receives, reading of data from register file I, register file II respectively, and the data that read are sent to error detection circuit I, error detection circuit II; According to the control of system controller, carry out corresponding operating;
Error detection circuit I, error detection circuit II detect the data that read whether single-particle inversion take place, and the error detection result is sent to system controller;
Comparison module compares the result after execution module I, the execution module II execution command, if unanimity as a result then sends to this result the memory module storage; Otherwise, with current state reporting system controller;
The system controller course of work: the first step, judge whether to receive the error detection result of error detection circuit I, error detection circuit II transmission, if receive this error detection result, then changeed for second step, otherwise, judge the current state information that is subjected to not receive the comparison module transmission, if receive current state information, then control is got the finger print piece and is read this instruction again; If do not receive current state information, then continue to wait for;
In second step, if the error detection result shows that single-particle inversion does not all take place the data that execution module I, execution module II read from register file I, register file II, then control and executive module I, execution module II utilize the data that read to carry out present instruction;
If the error detection result shows that single-particle inversion all takes place the data that execution module I, execution module II read from register file I, register file II, then control and executive module I, execution module II quit work, and control is simultaneously got the finger print piece and read present instruction again;
If the error detection result shows the data generation single-particle inversion that has only an execution module to read from its register file, then first control and executive module I, execution module II quit work, the data that the correct data that read with another execution module are replaced this generation single-particle inversion, and the data after will replacing send to execution module I, execution module II respectively, restart execution module I, execution module II, utilize the data of replacing to carry out present instruction by execution module I, execution module II.
2. the anti-single particle effect system based on synchronizing redundant threads and coding techniques according to claim 1 is characterized in that: also comprise writing back module, write back module the result of memory module storage is write back register file I, register file II.
3. the anti-single particle effect system based on synchronizing redundant threads and coding techniques according to claim 1 and 2 is characterized in that: describedly get the instruction that the finger print piece reads need handle through the EDAC error correcting and detecting from external memory storage; The instruction of reading from the CACHE that hits is handled through parity checking.
4. based on the anti-single particle effect method of synchronizing redundant threads and coding techniques, it is characterized in that: this method is carried out synchronously by two thread branch Pyatyi flowing water, the shared resource of two threads refers to level, thread gating stage, storage level for getting, and redundant resource is decode stage and execution level; Method step is as follows:
(1) get refer to level from the CACHE that hits or from external memory storage reading command, and with the Instructions Cache that reads;
(2) instruction of buffer memory in the thread gating stage read step (1) will be launched behind this Instructions Cache; Simultaneously with described redundant resource gating;
(3) instruction that sends of the decode stage receiving thread gating stage in the redundant resource, and this instruction deciphered, send to execution level after the decoding;
(4) instruction after redundant execution level is deciphered according to step (3), reading of data from the register file of place thread separately respectively, read in the process, judge whether the data that read single-particle inversion takes place, if single-particle inversion does not all take place in the data that redundant execution level reads from register file, then redundant execution level utilizes the data that read to carry out this instruction respectively, changes step (5); If single-particle inversion all takes place in the data that redundant execution level reads from register file, stop two thread pipeline, begin to re-execute from step (1); If the data that redundant execution level reads from register file have only a thread generation single-particle inversion, stop two thread pipeline earlier, the data of the data replacement generation single-particle inversion of single-particle inversion will not take place in redundant execution level, restart described streamline, and utilize the data that read to carry out this instruction respectively, change step (5);
(5) storage level compares redundant execution level execution result, if unanimity is as a result then stored this result; Otherwise, show the single-particle transient state takes place, stop streamline and carry out, begin to re-execute from step (1).
5. the anti-single particle effect method based on synchronizing redundant threads and coding techniques according to claim 1, it is characterized in that: the shared resource of described two threads also comprises and writes back level, writes back level the execution result of storage in the step (5) is write back in the described register file.
6. the anti-single particle effect method based on synchronizing redundant threads and coding techniques according to claim 4 is characterized in that: getting in the described step (1) refers to that the instruction that level reads need be through the processing of EDAC error correcting and detecting from external memory storage; The instruction of reading from the CACHE that hits is handled through parity checking.
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| EP1038211B1 (en) * | 1998-06-25 | 2005-02-09 | Koninklijke Philips Electronics N.V. | Dynamic memory space allocation |
| CN1902593A (en) * | 2003-12-30 | 2007-01-24 | 英特尔公司 | Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support |
| CN101031887A (en) * | 2004-09-29 | 2007-09-05 | 英特尔公司 | Executing checker instructions in redundant multithreading environments |
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