CN104731666B - It is a kind of primary particle inversion resistant from error correction integrated circuit and its error correction method - Google Patents
It is a kind of primary particle inversion resistant from error correction integrated circuit and its error correction method Download PDFInfo
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- CN104731666B CN104731666B CN201310718909.6A CN201310718909A CN104731666B CN 104731666 B CN104731666 B CN 104731666B CN 201310718909 A CN201310718909 A CN 201310718909A CN 104731666 B CN104731666 B CN 104731666B
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Abstract
The invention belongs to single-particle inversion fault-toleranr technique field, there is provided a kind of primary particle inversion resistant from error correction integrated circuit and its error correction method.Should be that integrated circuit is reinforced using dual model redundancy model from error correction integrated circuit and its error correction method, each functional unit group includes two functional units being mutually redundant, streamline management function is integrated in a wherein functional unit, Pipeline control is carried out to the functional unit from error correction unit, so that the functional unit performs twice, two implementing results are obtained.Then only occurred in based on mistake in functional unit group on the premise of a certain moment of a certain functional unit, by the implementing result twice of the functional unit compared with the implementing result of another functional unit, you can realize from error correction.Relative to existing triplication redundancy reinforcement technique, functional module and wiring that addition is needed in the primary particle inversion resistant integrated circuit from error correction are reduced, and reduce the area of integrated circuit, so as to improve the reliability of system work.
Description
Technical field
The invention belongs to single-particle inversion fault-toleranr technique field, more particularly to it is a kind of be mainly used in it is anti-in Space Facilities
Single-particle inversion from error correction integrated circuit and its error correction method.
Background technology
Microprocessor is all kinds of Space Facilities（Such as：Satellite, carrier rocket, spaceship etc.）In one of core devices.
In the outer space, the cosmic ray being made up of a variety of rays and single heavy ion has extremely strong penetration power, microprocessor can be made
Into very big infringement, easily make it that single-particle inversion occurs in semiconductor devices in microprocessor, that is, causes the logic of semiconductor devices
State is overturn, so as to cause the disabler of microprocessor.Therefore, the Radiation hardness of microprocessor is outstanding in Space Facilities
To be important.
To solve the problems, such as the single-particle inversion of microprocessor in Space Facilities, prior art proposes a kind of triplication redundancy and added
Gu technology.The technology is to carry out function division to microprocessor, and utilizes three same work(of the Implement of Function Module being mutually redundant
Can, in the output port for the functional module that three are realized identical function, increase by a majority voting device, to three functional modules
The data of output are selected to realize the purpose of error correction.
But foregoing triplication redundancy reinforcement technique needs the functional module additionally added and connected up more so that hardware resource and
Systemic-function consumption is larger, and causes microprocessor area to be increased to original three times.Simultaneously as area increases, so as to phase
Irradiated area should be added, reduces the reliability of microprocessor.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of primary particle inversion resistant from error correction integrated circuit, it is intended to solves existing
The functional module and connect up more that some triplication redundancy reinforcement techniques need to add so that the area of microprocessor increases more, work
The problem of making reliability reduction.
The embodiment of the present invention is achieved in that one kind is primary particle inversion resistant from error correction integrated circuit, described from error correction
Integrated circuit includes：
At least one functional unit group, each functional unit group include the first functional unit and the second function being mutually redundant
Unit；
With the functional unit group connect one to one from error correction unit, respective error correction unit cascade Connection, and upper one
Input signal of the level from the output signal of error correction unit as next stage from error correction unit, it is described defeated for receiving from error correction unit
Enter signal, the input signal is sent to corresponding first functional unit and second functional unit, and control institute
State the first functional unit to perform twice, if the first time implementing result of first functional unit and second functional unit
Implementing result is inconsistent, then by the first time implementing result of first functional unit and the execution knot of second functional unit
As output signal output in fruit, with second of implementing result identical result of first functional unit.
The another object of the embodiment of the present invention is to provide a kind of as described above primary particle inversion resistant integrated from error correction
The error correction method of circuit, the described method comprises the following steps：
Input signal is received from error correction unit, the input signal is sent to corresponding first functional unit and the second work(
Energy unit, and control first functional unit to perform twice；
If the first time implementing result of first functional unit and the implementing result of second functional unit are inconsistent,
Then it is described from error correction unit by the first time implementing result of first functional unit and the execution knot of second functional unit
As output signal output in fruit, with second of implementing result identical result of first functional unit.
It is provided in an embodiment of the present invention it is primary particle inversion resistant from error correction integrated circuit and its error correction method be to use bimodulus
Redundant fashion is reinforced to integrated circuit, and each functional unit group includes two functional units being mutually redundant, meanwhile, at it
Streamline management function is integrated in middle One function unit, Pipeline control is carried out to the functional unit from error correction unit so that
The functional unit performs twice, obtains two implementing results.So, a certain work(in functional unit group is being only occurred in based on mistake
The implementing result twice and the implementing result of another functional unit of the functional unit can be passed through on the premise of a certain moment of unit
It is compared, you can realize from error correction.Relative to existing triplication redundancy reinforcement technique, the primary particle inversion resistant self-picketing
The functional module and wiring that addition is needed in wrong integrated circuit are reduced, and the area of integrated circuit are reduced, so as to improve system work
The reliability of work.
Brief description of the drawings
Fig. 1 is the primary particle inversion resistant schematic diagram from error correction integrated circuit that the embodiment of the present invention one provides；
Fig. 2 is from the cut-away view of error correction unit in Fig. 1；
Fig. 3 is the flow for the primary particle inversion resistant error correction method from error correction integrated circuit that the embodiment of the present invention two provides
Figure；
Fig. 4 is that input signal is sent into corresponding first functional unit and from error correction unit in the embodiment of the present invention two
Two functional units simultaneously control the detail flowchart of the first functional unit execution twice.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
The problem of existing for existing triplication redundancy reinforcement technique, the present invention propose a kind of primary particle inversion resistant self-picketing
Wrong integrated circuit.The integrated circuit is that integrated circuit is reinforced using dual model redundancy model, and incorporating pipeline controlling party
Formula is realized from error correction.Describe the implementation of the present invention in detail below with reference to embodiment：
Embodiment one
The embodiment of the present invention one provide it is a kind of primary particle inversion resistant from error correction integrated circuit, as shown in figure 1, in order to just
In explanation, the part related to the embodiment of the present invention one illustrate only.
Specifically, this primary particle inversion resistant includes from error correction integrated circuit：At least one functional unit group, Mei Yigong
Energy unit group includes the first functional unit 1 and the second functional unit 2 being mutually redundant；Connected one to one with functional unit group
It is each from the cascade Connection of error correction unit 3 from error correction unit 3, and upper level from the output signal of error correction unit 3 as next stage from
The input signal of error correction unit 3, it is used to receive input signal from error correction unit 3, input signal is sent to corresponding first work(
The energy functional unit 2 of unit 1 and second, and control the first functional unit 1 to perform twice, if the first time of the first functional unit 1 holds
Row result and the implementing result of the second functional unit 2 are inconsistent, then by the first time implementing result and second of the first functional unit 1
In the implementing result of functional unit 2, it is defeated as output signal with second of implementing result identical result of the first functional unit 1
Go out, if the first time implementing result of the first functional unit 1 is consistent with the implementing result of the second functional unit 2, by the first function
The first time implementing result of unit 1 or the implementing result of the second functional unit 2 export as output signal.Preferably, from error correction
Integrated circuit is the microprocessor in Space Facilities.
In the embodiment of the present invention one, each functional unit group is divided in integrated circuit, according to the difference of completed function
Obtained functional module, such as memory module, computing module, interface module etc..Meanwhile have between adjacent functional unit group
Priority execution sequence, each functional unit group realize the function of integrated circuit jointly, i other words, the functional unit group of previous stage is held
Input signal of the row result as the functional unit group of rear stage, the functional unit group of rear stage is according to the implementing result of previous stage
Perform corresponding function.For example, the functional unit group of previous stage can be computing module, the functional unit group of its rear stage can be
Interface module, then the computing module of previous stage is to input letter of the operation result of input signal as the interface module of rear stage
Number, interface module exports input signal.
In the embodiment of the present invention one, the input signal of the first functional unit group in integrated circuit comes from integrated circuit
Outside input, the output signal of the end functional unit group in integrated circuit is output to the outside of integrated circuit.
Further, as shown in Fig. 2 may include from error correction unit 3：Signal caches and pipeline control module 31, is used for
Input signal is received, input signal is cached, and input signal is synchronously sent to corresponding first functional unit 1 and the
Two functional units 2, the current operating conditions information returned afterwards according to the first functional unit 1, sky is in the first functional unit 1
During not busy state, the input signal of caching is sent to corresponding first functional unit 1 again；Comparison and output module 32, are used for
Returned after latching second the first time implementing result returned after the first functional unit 1 performs for the first time, the first functional unit 1 of execution
The implementing result that second of the implementing result returned and the second functional unit 2 return, and compare the first of the first functional unit 1
Secondary implementing result and the implementing result of the second functional unit 2, if the first time implementing result of the first functional unit 1 and the second function
The implementing result of unit 2 is inconsistent, then compare the first functional unit 1 first time implementing result, the second of the first functional unit 1
The implementing result of secondary implementing result and the second functional unit 2, and by the first time implementing result and the second work(of the first functional unit 1
Can unit 2 implementing result in, it is defeated as output signal with second of implementing result identical result of the first functional unit 1
Go out, if the first time implementing result of the first functional unit 1 is consistent with the implementing result of the second functional unit 2, by the first function
The first time implementing result of unit 1 or the implementing result of the second functional unit 2 export as output signal.
The embodiment of the present invention one propose it is primary particle inversion resistant from error correction integrated circuit be to use dual model redundancy model pair
Integrated circuit is reinforced, and each functional unit group includes two functional units being mutually redundant, meanwhile, in the first functional unit
Streamline management function is integrated in 1, the current operating conditions information such as idle condition or busy condition can be provided to from error correction unit 3,
Pipeline control mode from error correction unit 3 according to current operating conditions information realization to the first functional unit 1 so that the first work(
Energy unit 1 performs twice, obtains two implementing results.So, a certain function in functional unit group is being only occurred in based on mistake
On the premise of a certain moment of unit, by by the execution of the implementing result twice of the first functional unit 1 and the second functional unit 2
As a result it is compared, you can realize from error correction.Relative to existing triplication redundancy reinforcement technique, this is primary particle inversion resistant
The functional module and wiring that addition is needed from error correction integrated circuit are reduced, and are reduced the area of integrated circuit, are so as to improve
The reliability of system work.
Embodiment two
The embodiment of the present invention two provides a kind of primary particle inversion resistant from error correction integrated circuit as described in embodiment one
Error correction method, as shown in figure 3, including：
Step S1：Input signal is received from error correction unit, input signal is sent to corresponding first functional unit and the
Two functional units, and control the first functional unit to perform twice.
Further, as shown in figure 4, step S1 may include following steps：
S11：Input signal is received from error correction unit.
S12：Input signal is cached from error correction unit, and input signal is synchronously sent to corresponding first function
Unit and the second functional unit.
S13：The current operating conditions information returned from error correction unit according to the first functional unit, at the first functional unit
When idle condition, the input signal of caching is sent to corresponding first functional unit again.
Step S2：If the first time implementing result and the implementing result of the second functional unit of the first functional unit are inconsistent,
Then from error correction unit by the first time implementing result of the first functional unit and the implementing result of the second functional unit, with the first work(
Second of implementing result identical result of energy unit exports as output signal.
In addition, after step S1, may also include：
Step S3：If the first time implementing result of the first functional unit is consistent with the implementing result of the second functional unit,
From error correction unit using the first time implementing result of the first functional unit or the implementing result of the second functional unit as output signal
Output.
The primary particle inversion resistant error correction method from error correction integrated circuit that the embodiment of the present invention two proposes is to use bimodulus
Redundant fashion is reinforced to integrated circuit, and combines the pipeline control mode from error correction unit so that the first functional unit
Perform twice, obtain two implementing results.So, only occurred in based on mistake a certain functional unit in functional unit group certain
On the premise of one moment, by the way that the implementing result twice of the first functional unit and the implementing result of the second functional unit are compared
Compared with, you can realize from error correction.Relative to existing triplication redundancy reinforcement technique, this is primary particle inversion resistant to integrate from error correction
The functional module and wiring that addition is needed in circuit are reduced, and reduce the area of integrated circuit, can so as to improve system work
By property.
Can be with one of ordinary skill in the art will appreciate that realizing that all or part of step in above-described embodiment method is
By program come control correlation hardware complete, described program can in a computer read/write memory medium is stored in,
Described storage medium, such as ROM/RAM, disk, CD.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (8)
- It is 1. a kind of primary particle inversion resistant from error correction integrated circuit, it is characterised in that described to include from error correction integrated circuit：At least one functional unit group, each functional unit group include the first functional unit and the second function list being mutually redundant Member；With the functional unit group connect one to one from error correction unit, respective error correction unit cascade Connection, and upper level from Input signal of the output signal of error correction unit as next stage from error correction unit, it is described to be used to receive input letter from error correction unit Number, the input signal is sent to corresponding first functional unit and second functional unit, while described in reception The current operating conditions information of first functional unit output simultaneously controls first function according to the current operating conditions information Unit performs twice, and the implementing result output signal output of the functional unit group according to corresponding connection；If described first The first time implementing result of functional unit and the implementing result of second functional unit are inconsistent, then by the first function list Held for the second time in the first time implementing result of member and the implementing result of second functional unit, with first functional unit Row result identical result exports as output signal.
- It is 2. as claimed in claim 1 primary particle inversion resistant from error correction integrated circuit, it is characterised in that described from error correction unit It is additionally operable to when the first time implementing result of first functional unit is consistent with the implementing result of second functional unit, will The first time implementing result of first functional unit or the implementing result of second functional unit export as output signal.
- It is 3. as claimed in claim 1 primary particle inversion resistant from error correction integrated circuit, it is characterised in that described from error correction unit Including：Signal caches and pipeline control module, and for receiving the input signal, the input signal is cached, and will The input signal is synchronously sent to corresponding first functional unit and second functional unit, afterwards according to described the The current operating conditions information that one functional unit returns, when first functional unit is in idle condition, by the institute of caching State input signal and be sent to corresponding first functional unit again；Comparison and output module, for latch the first time implementing result returned after first functional unit performs for the first time, What second of the implementing result and second functional unit returned after first functional unit, second of execution returned holds Row result, and the first time implementing result of first functional unit and the implementing result of second functional unit, if The first time implementing result of first functional unit and the implementing result of second functional unit are inconsistent, then relatively more described Second of implementing result and the second function list of the first time implementing result of first functional unit, first functional unit The implementing result of member, and by the first time implementing result of first functional unit and the implementing result of second functional unit In, with second of implementing result identical result of first functional unit as output signal output.
- It is 4. as claimed in claim 3 primary particle inversion resistant from error correction integrated circuit, it is characterised in that the comparison and output Module is additionally operable to when the first time implementing result of first functional unit is consistent with the implementing result of second functional unit When, using the first time implementing result of first functional unit or the implementing result of second functional unit as output signal Output.
- It is 5. as claimed in claim 1 primary particle inversion resistant from error correction integrated circuit, it is characterised in that described to be integrated from error correction Circuit is the microprocessor in Space Facilities.
- 6. a kind of primary particle inversion resistant error correction method from error correction integrated circuit as described in any one of claim 1 to 5, its It is characterised by, the described method comprises the following steps：Input signal is received from error correction unit, the input signal is sent to corresponding first functional unit and the second function list Member, while receive the current operating conditions information of first functional unit output and according to the current operating conditions information control First functional unit is made to perform twice；If the first time implementing result of first functional unit and the implementing result of second functional unit are inconsistent, institute State from error correction unit by the first time implementing result of first functional unit and the implementing result of second functional unit, Exported with second of implementing result identical result of first functional unit as output signal.
- 7. the primary particle inversion resistant error correction method from error correction integrated circuit as claimed in claim 6, it is characterised in that described Input signal is received from error correction unit, the input signal is sent to corresponding first functional unit and the second functional unit, And the step of controlling first functional unit to perform twice, comprises the following steps again：It is described to receive the input signal from error correction unit；It is described that the input signal is cached from error correction unit, and the input signal is synchronously sent to corresponding described First functional unit and second functional unit；The current operating conditions information returned from error correction unit according to first functional unit, in the first function list When member is in idle condition, the input signal of caching is sent to corresponding first functional unit again.
- 8. the primary particle inversion resistant error correction method from error correction integrated circuit as claimed in claim 6, it is characterised in that in institute State from error correction unit and receive input signal, the input signal is sent to corresponding first functional unit and the second function list Member, and the step of control first functional unit to perform twice after, methods described is further comprising the steps of：If the first time implementing result of first functional unit is consistent with the implementing result of second functional unit, described From error correction unit using the first time implementing result of first functional unit or the implementing result of second functional unit as Output signal exports.
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| CN105320575B (en) * | 2015-10-27 | 2018-03-23 | 首都师范大学 | A kind of self checking of duplication redundancy streamline and recovery device and method |
| CN109271282B (en) * | 2018-09-06 | 2022-01-11 | 北京时代民芯科技有限公司 | Single-particle multi-dislocation autonomous repair triple-redundancy assembly line and design method |
| CN111459712B (en) * | 2020-04-16 | 2021-04-02 | 上海安路信息科技股份有限公司 | SRAM type FPGA single event upset error correction method and single event upset error correction circuit |
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