CN106301352B - A kind of Anti-radioactive Fault-tolerant circuit design method based on door or door and selector - Google Patents
A kind of Anti-radioactive Fault-tolerant circuit design method based on door or door and selector Download PDFInfo
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- CN106301352B CN106301352B CN201510252467.XA CN201510252467A CN106301352B CN 106301352 B CN106301352 B CN 106301352B CN 201510252467 A CN201510252467 A CN 201510252467A CN 106301352 B CN106301352 B CN 106301352B
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Abstract
The invention belongs to integrated circuit fields, it is related to resisting the circuit design method of radiation, and in particular to a kind of Anti-radioactive Fault-tolerant circuit design method based on door or door and selector.The present invention with one with door, one or and one 2 select 1 selector construct one compared with voting circuit; then by by the main output of protection circuit, two input ports of voting circuit are connected compared with respectively with redundancy output; when leading to its main output with redundancy output numerical value difference by the radiation of protection circuit because; compare voting circuit output and maintain initial value, output valve that may be wrong by protection circuit will not be exported.The experimental results showed that, the wrong frequency of the present invention and triplication redundancy scheme is all less and suitable after tested, their capability of resistance to radiation is close, but area and the area of power dissipation ratio triplication redundancy scheme and the comparison of small power consumption of the invention is more.
Description
Technical field
The invention belongs to integrated circuit fields, be related to resisting the circuit design method of radiation, and in particular to one kind based on
The Anti-radioactive Fault-tolerant circuit design method of door or door and selector.
Background technique
With the reduction of process, integrated circuit in chip high-rise space or near-earth spherical space be increasingly easy by
It is influenced to heavy particle or proton irradiation and generates mistake.Studies have shown that radiation may cause simple grain in case of in circuit node
Sub- transient pulse changes the logic state of circuit node.Error value caused by the single event transient pulse is conducted to memory also
May be captured storage.So single event transient pulse can change the logic state of circuit node, circuit function mistake may cause
Accidentally.Therefore, circuit design method of this field in relation to needing to propose to resist radiation in working practice.
The design method of the radiation hardened integrated circuit of the prior art mainly includes multi-mode redundant, error correcting code and anti-radiation storage
Unit etc., wherein multi-mode redundant method uses redundant circuit module and majority voter screen using triplication redundancy technology as representative
The output of erroneous circuits module is covered, but this method can bring very big area overhead；Error correction code approach using Hamming code as representative,
By the check value of calculation code, the position of error bit is positioned；Anti-radiation storage unit method is with double interlock storage unit
To represent, increase extra transistor and mutually twisted interconnection line on the basis of basic unit of storage structure, enhances sensitive section
The capability of resistance to radiation of point；But error correcting code and anti-radiation storage unit can bring biggish area overhead, and reduce circuit performance.
Based on this, present inventor is quasi- to be directed to integrated circuit, proposes a kind of based on anti-with door or door and selector
Radiate fault tolerable circuit design method.
Bibliography related to the present invention has:
[1]Baumann R.Soft Errors in Advanced Computer Systems[J],IEEE
Transactions on Device and Materials Reliability,2005,22(3),pp.258-266
[2] Oliveira R., Jagirdar A., Chakraborty T.J.:A TMR Scheme for SEU
Mitigation in Scan Flip-Flops [C], in International Symposium on Quality
Electronic Design,2007,pp.905–910
[3]Tausch H.J.Simplified Birthday Statistics and Hamming EDAC[J],IEEE
Transactions on Nuclear Science,2009,56(2),pp.474–478
[4]Calin T.,Nicolaidis M.,Velazco R.Upset hardened memory design for
submicron CMOS technology[J],IEEE Transactions on Nuclear Science,1996,43(6),
pp.2874–2878
[5]S.Yang.Logic Synthesis and Optimization Benchmarks User Guide,
Research Triangle Park,NC:Microelectronics Center of North Carolina(MCNC),
1991。
Summary of the invention
The purpose of the present invention is being directed to integrated circuit, a kind of circuit design method for resisting radiation, especially one kind are proposed
Based on the Anti-radioactive Fault-tolerant circuit design method with door or door and selector.
The present invention using one with door, one or and one 2 select 1 selector construct one compared with voting circuit；This ratio
It is connected respectively with by one, protection circuit main output and a redundancy output compared with two input terminals of voting circuit；When by protection electricity
The main output on road is identical as redundancy output numerical value, compares voting circuit output by the main output numerical value of protection circuit, but work as and protected
When protection circuit leads to its main output with redundancy output numerical value difference because of radiation, compares voting circuit output and maintain initial value, it will not be defeated
Out by the output valve of the possible mistake of protection circuit.
Specifically, a kind of Anti-radioactive Fault-tolerant circuit design method packet based on door or door and selector of the invention
Containing two steps, it is described in detail separately below.
Step 1: according to circuit structure shown in Fig. 1, using traditional integrated circuit design method design comparison voting circuit,
Circuit structure as shown in Figure 1, design comparison voting circuit, Fig. 1 include one and door A1, one or A2 and one
2 select 1 selector M1；Input port with door A1 is I1 and I2, and output port is O, realizes logical AND circuit function or door A2
Input port is I1 and I2, and output port is O, realizes logic or circuit function；2 select the input port of 1 selector M1 be I1 with
I2, output port are O, and selection port is S；In selector M1, when S value is 0, O value is the value of I1；When S is 1, O value is
The value of I2；Select 1 selector M1 that the realization of traditional integrated circuit design method all can be used with door A1 or door A2 and 2 in Fig. 1；Fig. 1
In, when n1 is identical as n2 value, n7 can export n1 value, for example, n5 and n6 value is all 0 when n1 and n2 are 0, so regardless of
Value is 0 or 1 to n7 in the past, and selector M1 can export 0, i.e. n7 value will be 0；Similarly, when n1 and n2 are 1, n5 and n6
Value is all 1, so selector M1 can export 1 regardless of value is 0 or 1 to n7 in the past, i.e. n7 value will be 1；In Fig. 1, when n1 with
When n2 value difference, n7 can maintain to be worth in the past, for example, when n1 and n2 are 0, n7 0, it is assumed that subsequent time n1 is because radiating from 0
Become 1, n2 and still remain 0, then n5 is 0, n6 1, is 0 due to being worth before n7, selector M1 still can export 0, i.e. n7 value
It will stay in that 0, it will not output error value 1；Similarly, when n1 and n2 are 1, n7 1, it is assumed that subsequent time n1 is because radiating from 1
Become 0, n2 and still remain 1, then n5 is 0, n6 1, is 1 due to being worth before n7, selector M1 still can export 1, i.e. n7 value
It will stay in that 1, it will not output error value 0；
Step 2: circuit input end mouth is decided by vote compared with (in Fig. 1 respectively by being exported by the main output of protection circuit with redundancy
N1 be connected with n2),
Wherein, a kind of method of use is will to be copied into two parts by protection circuit, and portion is main circuit, another is redundancy
The function of circuit, main circuit and redundant circuit is identical；The output of the main circuit and redundant circuit voting circuit compared with respectively
Input port is connected, and is redundant circuit, main circuit by protection circuit 2 as shown in Fig. 2, being main circuit by protection circuit 1 in Fig. 2
It is identical with redundant circuit function, but circuit structure can it is identical can also be different；Under normal circumstances, main circuit output and redundancy
Circuit output is identical, and the output valve of main circuit can be exported by comparing voting circuit, it is assumed that main circuit because radiation leads to output error, but
Redundant circuit output keeps correct, then comparing voting circuit output n7 still can keep the output valve of redundant circuit, i.e. right value；
Assuming that redundant circuit is because radiation leads to output error, but main circuit output keeps correct, then compares voting circuit output n7 still
It can keep the output valve of main circuit, i.e. right value；
Another method used is that a reverse phase of upper even number (such as 2,4,6,8 ...) will be connected by protection circuit output port
Device constitutes redundancy output end, and by protection circuit original output port as main output end, by main output and redundancy output respectively with
Compare voting circuit input end mouth to be connected, as shown in figure 3, being n1 by the main output of protection circuit in Fig. 3, connects two reverse phases
The output n2 of device is redundancy output, and when leading to main output n1 when the error occurs by the radiation of protection circuit because, the mistake is because multiple
The delayed-action of phase inverter will not immediately appear in n2, so n2 is still temporarily maintained at right value；Since n1 and n2 value is temporary
Difference, comparing voting circuit output n7 still can temporarily keep original right value；If n1 is appeared in the inverted device of mistake
Before n2, because radiation effect disappearance revert to original right value, then when n2 when the error occurs, n1 has reverted to right value；
Since n1 is different from n2 value, comparing voting circuit output n7 still can keep original right value；Finally, when n2 is because of radiation effect
After disappearance also reverts to right value, n1 is identical with n2 value, compares and decides by vote circuit output n7 and still maintain right value, in Fig. 3, is protected
The quantity of protection circuit redundancy output the connected phase inverter of n2 is 2 but it is also possible to be other even numbers, such as 4,6,8 ...；Redundancy exports institute
The quantity of connection phase inverter should ensure that the delay that these phase inverters generate is greater than the duration of radiation pulse, can just make to compare voting electricity
Road output keeps right value.
The invention has the following advantages that
(1) present invention propose a kind of voting circuit compared with constituting with door or door and selector, when by protection circuit by
When radiation effect leads to its main output valve and redundancy output valve difference, which can maintain original right value, will not be defeated
Make mistake value, to make that circuit is protected to have Anti-radioactive Fault-tolerant characteristic.
(2) comparison voting circuit of the invention only include one with door, one or and one 2 select 1 selector, with the ratio
When protecting complicated circuit compared with voting circuit, the additional areas expense of generation is small, and bring extra delay is short.
Detailed description of the invention
Fig. 1 is the schematic diagram of comparison voting circuit of the invention.
Fig. 2 is the identical electrical block diagram that voting circuit is connected compared with by protection circuit of two parts of functions.
Fig. 3 is a electrical block diagram that voting circuit is connected compared with by protection circuit.
Specific embodiment
1 area of embodiment, power consumption and capability of resistance to radiation comparative experiments
Test experiments result:
In experiment, 6 benchmark test circuits without capability of resistance to radiation are realized using traditional standard circuit design method first
Bigkey, dsip, S38417, S13207.1, S15850.1, S38584.1 [5] then use triplication redundancy scheme and the present invention again
These benchmark test circuits are realized respectively, with capability of resistance to radiation；Respectively to the benchmark that these use different schemes to realize
It is as shown in table 1 to test resulting wrong frequency, area and power consumption average value for test circuit random radiation 1000 times；In table 1
Area and power consumption have passed through normalized, numerical value is the area and power consumption relative to the realized circuit of the present invention program
Multiple；From the test experiments of table 1, the result shows that, the wrong frequency of the present invention and triplication redundancy scheme is all less and phase
When so their capability of resistance to radiation is close, but the area and small power consumption of area and power dissipation ratio triplication redundancy scheme of the invention
Comparison it is more.
1 area of table, power consumption and capability of resistance to radiation compare
| Scheme | Mistake frequency | Area | Power consumption |
| Traditional standard design method without capability of resistance to radiation | 256 | 0.95 | 0.88 |
| Radiation-hardened design method of the invention | 4 | 1 | 1 |
| The radiation-hardened design method of triplication redundancy | 6 | 2.88 | 2.82 |
Claims (3)
1. a kind of Anti-radioactive Fault-tolerant circuit design method based on door or door and selector, which is characterized in that it includes step
It is rapid:
Step 1: by the circuit structure for selecting 1 selector M1 with door A1, one or A2 and one 2 comprising one, design comparison table
Certainly circuit；
Step 2: circuit input end mouth will be decided by vote respectively with redundancy output compared with described by the main output of protection circuit and be connected.
2. method according to claim 1, which is characterized in that in the step 1), by the circuit structure, using biography
System method of designing integrated circuit design comparison voting circuit；The circuit structure include one with door A1, one or A2 and
Select 1 selector M1 for one 2, wherein the input port with door A1 is I1 and I2, and output port is O, realizes logical AND circuit function
The input port of energy or door A2 are I1 and I2, and output port is O, realize logic or circuit function, 2 select the input of 1 selector M1
Port is I1 and I2, and output port is O, and selection port is S, and in selector M1, when S value is 0, O value is the value of I1；Work as S
When being 1, O value is the value of I2；Wherein, when voting comparison circuit input terminal n1 is identical as n2 value, decide by vote comparison circuit output end
N7 can export n1 value, when deciding by vote comparison circuit input terminal n1 and when n2 value difference, voting comparison circuit output end n7 can maintain with
Preceding value.
3. method according to claim 1, which is characterized in that in the step 2), comprising:
A kind of method is will to be copied into two parts by protection circuit, and portion is main circuit, another is redundant circuit, main circuit and superfluous
The function of remaining circuit is identical, and the output of main circuit and redundant circuit decides by vote circuit input end mouth respectively compared with and is connected,
In, it is main circuit by protection circuit 1, is redundant circuit by protection circuit 2, main circuit is identical with redundant circuit function, electricity
Line structure can be identical or different；Under normal circumstances, main circuit output is same with redundant circuit output phase, and comparing voting circuit can be defeated
The output valve of main circuit out, it is assumed that main circuit is because radiation leads to output error, but redundant circuit output keeps correct, then comparison sheet
Certainly circuit output n7 still can keep the output valve of redundant circuit, i.e. right value；Assuming that redundant circuit causes output wrong because of radiation
Accidentally, but main circuit output keeps correct, then comparing voting circuit output n7 still can keep the output valve of main circuit, i.e., correctly
Value；
Another method is will to connect upper even number of inverters by protection circuit output port to constitute redundancy output end, and protected
Main output is decided by vote compared with circuit input end mouth respectively with redundancy output and is connected by circuit original output port as main output end,
It wherein, is n1 by the main output of protection circuit, the output n2 for connecting two phase inverters is redundancy output, when by protection circuit because spoke
Penetrating causes main output n1 or redundancy to export n2 when the error occurs, compares voting circuit output n7 and still maintains right value；It is protected
The quantity that circuit redundancy exports the connected phase inverter of n2 is 2 or other even numbers；The quantity that redundancy exports connected phase inverter is protected
The delay for demonstrate,proving the phase inverter generation is greater than the duration of radiation pulse, makes to compare voting circuit output holding right value.
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| RU2756577C1 (en) * | 2020-12-18 | 2021-10-01 | Федеральное государственное бюджетное учреждение "Национальный исследовательский центр "Курчатовский институт" | Method for indirect measurement of fault tolerance of irradiated test digital microcircuits, built by method for constant redundancy, and functional structure of test microcircuit intended for implementation of this method |
| CN113721135B (en) * | 2021-07-22 | 2022-05-13 | 南京航空航天大学 | SRAM type FPGA fault online fault tolerance method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901176A (en) * | 2010-07-22 | 2010-12-01 | 北京交通大学 | Redundant clock system |
| CN101943910A (en) * | 2009-07-07 | 2011-01-12 | 华东理工大学 | Self-checking method for fault-tolerant control |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
| CN103731130A (en) * | 2013-12-27 | 2014-04-16 | 华为技术有限公司 | Universal fault-tolerant error-correction circuit, universal decoder and triple-module redundancy circuit |
| CN104917498A (en) * | 2015-06-05 | 2015-09-16 | 中国航天科技集团公司第九研究院第七七一研究所 | Three-mode clock generation circuit based on phase difference |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090230988A1 (en) * | 2004-12-01 | 2009-09-17 | Koninklijke Philips Electronics, N.V. | Electronic device having logic circuitry and method for designing logic circuitry |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101943910A (en) * | 2009-07-07 | 2011-01-12 | 华东理工大学 | Self-checking method for fault-tolerant control |
| CN101901176A (en) * | 2010-07-22 | 2010-12-01 | 北京交通大学 | Redundant clock system |
| CN103578567A (en) * | 2013-11-18 | 2014-02-12 | 中国电子科技集团公司第五十八研究所 | Triplication redundancy-based anti-radiation self-refreshing register |
| CN103731130A (en) * | 2013-12-27 | 2014-04-16 | 华为技术有限公司 | Universal fault-tolerant error-correction circuit, universal decoder and triple-module redundancy circuit |
| CN104917498A (en) * | 2015-06-05 | 2015-09-16 | 中国航天科技集团公司第九研究院第七七一研究所 | Three-mode clock generation circuit based on phase difference |
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